Considering that there is more than enough easily available nuclear fuel to power civilization for several time longer than we have had civilization so far, I give it a pass and in its case consider being truly renewable a distinction without a difference.
Magnetic media is not so prone to this. But this makes me wonder if the SSD drives, we are all using now, are having this problem??
Maybe SSDs have better data check and correction functions, but maybe we should keep a hard drive in our computers to reload the SSD, if necessary.
Both hard disk drives and solid state drives use block based error correction. Several bad bits can be corrected in each sector and sectors may even be considered good with several bad bits below a specified threshold.
Where SSDs compare poorly to HDDs is endurance and retention time but as long as they are not used for unpowered offline storage like a hard drive might be, retention time is not a problem and few users are going to reach endurance limits. There is a new standard for SSD retention time but I do not think any actually meet it.
Cosmic rays causing ram errors, is a thing. Scientists estimate it will happen to PCs, at ground level, about once a year. Surprisingly, which year does not matter much because as the tech gets smaller, the capacity gets larger, so the die size stays about the same.
Moore's law is about economics and includes cost reduction per transistor from increasing die size so I wonder if the total die area of memory has actually increased at the high end of consumer hardware.
Once a year might not sound like much, but that is not "at the end of the year", it can happen right away. Chance is strange that way. 8-)
MS should probably -not- have commented it out...
A couple of DRAM generations ago it was something like 1 bit per year per gigabyte but later DRAM generations actually improved slightly. My workstations went from 2GB to 8GB in my current one and my next will likely be 64GB but they all use 4 x dual sided DIMMs so the same number of chips but the silicon chips themselves have increased in area with better packaging.
Some of the idle processing on AS/400s would periodically re-write the microcode from disk. When I asked a core developer why, they cited gamma rays flipping a bit. I then asked if a lead umbrella wouldn't do the job better, and they said yes, but the umbrella would have to be about six feet thick.
Cache and memory scrubbing is a standard feature even on x86 consumer desktop processors whether the user has access to it or not. Motherboards which support ECC memory may make the settings which control scrubbing available in the BIOS. Scrubbing applies to every level of cache which is ECC or parity protected and to main memory if ECC protected.
The reality is having error detection and/or correction on every cache, register, bus, lane, memory, storage, and everything between is hella expensive. So your desktop processor has relatively little and processors meant for servers or embedded systems have widely varying amounts.
With some exceptions, most Intel consumer and server processors use the exact same die so the ECC protection is there. The major difference is that with some exceptions, ECC for external memory is disabled on non-Xeon products.
One of the exceptions is for lower performance processors like the i3 series which do not compete with Xeon products. Fancy that.
If the cache is susceptible to random gamma rays, or, more likely, cosmic rays, and has no ECC, it is NEVER trustworthy, and should be permanently disabled.
While it is shut down, the cache is not being continuously scrubbed by ECC or parity allowing bit errors to accumulate and defeat the ECC or parity after it is powered up. Invalidating and reloading the contents of the cache makes perfect sense in this situation.
Hi, I'm a software engineer working on embedded computers flying on satellites. Single upset events are a common occurrence up in space, even on low earth orbit. And modern COTS chips are more vulnerable than chips of yore. RADHARD chips are old slow and expensive. They have fat thick lines that aren't as easily bumped by radiation. Satellites up on GEO might have it worse, but LEO still has problems.
The last time I checked, the reason radiation hardened processes used much larger minimum feature sizes was simply because it was not economical to produce a denser radiation hardened process. More modern fabrication processes require an economy of scale which is not available for such a small market.
With modern processors being built ont the 14 nanometres process this becones a serious problem.
Susceptibility is more complicated than just the minimum feature size. It was a serious problem generations ago.
Denser processes use gate insulators with a higher dielectric constant to store more charge and also provide more drive for a given area. These things make a process more resistant to radiation induce soft errors. The same things caused the susceptibility of DRAM processes to level off or even decrease slightly starting a couple generations ago.
DRAM soft error rates leveled off a couple generations ago. SRAM soft error rates are a couple orders of magnitude higher and have remained so for integrated SRAM caches. A discussion of the difference and why it exists would be interesting.
Other than some odd exceptions, integrated SRAM caches have been protected by ECC or parity almost since they were first used.
The problem is that you need a CPU and north bridge that can handle it, which adds to the initial costs. For Intel, for example, a Xeon CPU costs (artificially) a good deal more than a comparable speed i3/5/7/9, which is an upfront cost that consumers aren't willing to eat, and they tend to choose either a cheaper CPU or a faster CPU for the same kind of money.
In most cases Intel's Xeon and consumer CPUs are the same hardware so the only difference in production might be testing time. Intel's artificial market segmentation of ECC is more about price discrimination then costs which can be seen by their tying ECC to use of the proper south bridge which has nothing to do with it.
What's odd is that ECC is not routinely used in all hardware. Depending on the conditions it can be of great help, as the rare bit flip can cause strange problems that can take ages to track down.
Whether ECC is used or not depends on the likelyhood of an error and how serious the consequences will be. The number of errors depends on how much memory is used (not installed), how long it is used, and oddly enough some factor related to the access rate. Since servers tend to have much more memory and operate for longer times than desktops, ECC makes more sense for them.
Who cares about errors while playing a game or media or doing consumer type tasks which do not tax the computer? But if my workstation is running for days at a time on important work, or I do not want to waste my time programming tracking down even one soft error, or a computer has any effect on human safety, ECC is very economical.
I was unaware that they were in the habit of using materials that suffer from alpha decay when manufacturing electronics (hint, they don't).
They try to avoid radioactive materials in packaging for that very reason however sometimes contamination occurs anyway.
Back during about the 64kbit DRAM generation, this was a huge problem with ceramic packaged parts increasing the demand for plastic packaging despite doubts about its reliability.
S1 i supposed to keep the cache fully powered up. How's it going to make any difference if an alpha particle hits the cache memory cells while the core clock has stopped?
The cache is protected against data corruption by ECC or parity however if multiple bit errors accumulate within one word, this protection fails. During normal operation, the cache is continuously scrubbed of errors so this is not a problem.
Of course, there are many more bits in RAM which could be affected, so a problem is more likely to occur there, which this doesn't address.
High performance integrated SRAM is orders of magnitude more susceptible to radiation induced soft errors than DRAM which is why SRAM caches have included ECC or parity protection almost since they were first used.
Oddly enough, DRAM has actually become more resistant to radiation induced soft errors over the last couple of generations but this is more than cancelled by the increasing amount of DRAM used.
That's a little unfair. The reason that commercial crew has such strict requirements is because of the shitstorm that hit NASA from every direction after the shuttle failures.
NASA did this before the Shuttle failures.
NASA holds other parties to a higher standard than NASA and NASA's contractors. Things which are considered failures if others do them are maintenance issues for NASA.
When NASA found that the Space Shuttle's main engines returned with cracked turbine blades, they redefined this from a failure to a maintenance issue. But if the Merlin engines in SpaceX's Falcon 9 return with cracked turbine blades, it is a failure.
Heat prevents a 3D chip? Lay down a thick layer of heat conductive material, before the next layer of logic. Ok, you won't get 80.000 layers that way, perhaps only 800.
You will not get any layers that way; any thin heat conductive layers between chips just does not support the needed increase in thermal conductivity needed to help significantly.
High performance chips have been thermal limited for many process generations now. Anything which increases the junction to surface thermal resistance will just make them more thermal limited. About the only thing which would help for a single chip is a better heat spreader made of something with a better thermal conductivity than copper like diamond. The power density is so high that even a heat pipe cannot be used without a heat spreader.
That leaves convection cooling through microfluidics to remove heat through the volume of the chip if it is feasible.
The Commerce clause allows them to do stuff like this. Not everything needs to be written out specifically. The Commerce clause because its relative vagueness allows the Fed. government to do a lot of stuff that isn't explicitly stated.
We should terraform Antarctica just to piss Bill Nye off.
Who's up for that?
Ice court tennis, anyone?
It would be a great feasibility test with much less risk, at least up until the point were we dig up an alien spaceship which has been buried in the ice for millions of years and recover an occupant. Ok, maybe it is not such a good idea. Forget that I suggested it.
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Nobody is going back to nuclear. It costs too much to store the waste. They're just improving the storage options.
Nobody is going back to coal; it costs too much to store the wastes. Or blow them into the atmosphere for others to deal with.
Nobody is going back to oil; it costs too much to conduct war in the MIddle East. Shouldn't these wars be considered petroleum subsidies?
Considering that there is more than enough easily available nuclear fuel to power civilization for several time longer than we have had civilization so far, I give it a pass and in its case consider being truly renewable a distinction without a difference.
Magnetic media is not so prone to this. But this makes me wonder if the SSD drives, we are all using now, are having this problem??
Maybe SSDs have better data check and correction functions, but maybe we should keep a hard drive in our computers to reload the SSD, if necessary.
Both hard disk drives and solid state drives use block based error correction. Several bad bits can be corrected in each sector and sectors may even be considered good with several bad bits below a specified threshold.
Where SSDs compare poorly to HDDs is endurance and retention time but as long as they are not used for unpowered offline storage like a hard drive might be, retention time is not a problem and few users are going to reach endurance limits. There is a new standard for SSD retention time but I do not think any actually meet it.
Cosmic rays causing ram errors, is a thing. Scientists estimate it will happen to PCs, at ground level, about once a year. Surprisingly, which year does not matter much because as the tech gets smaller, the capacity gets larger, so the die size stays about the same.
Moore's law is about economics and includes cost reduction per transistor from increasing die size so I wonder if the total die area of memory has actually increased at the high end of consumer hardware.
Once a year might not sound like much, but that is not "at the end of the year", it can happen right away. Chance is strange that way. 8-)
MS should probably -not- have commented it out...
A couple of DRAM generations ago it was something like 1 bit per year per gigabyte but later DRAM generations actually improved slightly. My workstations went from 2GB to 8GB in my current one and my next will likely be 64GB but they all use 4 x dual sided DIMMs so the same number of chips but the silicon chips themselves have increased in area with better packaging.
Some of the idle processing on AS/400s would periodically re-write the microcode from disk. When I asked a core developer why, they cited gamma rays flipping a bit. I then asked if a lead umbrella wouldn't do the job better, and they said yes, but the umbrella would have to be about six feet thick.
Cache and memory scrubbing is a standard feature even on x86 consumer desktop processors whether the user has access to it or not. Motherboards which support ECC memory may make the settings which control scrubbing available in the BIOS. Scrubbing applies to every level of cache which is ECC or parity protected and to main memory if ECC protected.
The reality is having error detection and/or correction on every cache, register, bus, lane, memory, storage, and everything between is hella expensive. So your desktop processor has relatively little and processors meant for servers or embedded systems have widely varying amounts.
With some exceptions, most Intel consumer and server processors use the exact same die so the ECC protection is there. The major difference is that with some exceptions, ECC for external memory is disabled on non-Xeon products.
One of the exceptions is for lower performance processors like the i3 series which do not compete with Xeon products. Fancy that.
If the cache is susceptible to random gamma rays, or, more likely, cosmic rays, and has no ECC, it is NEVER trustworthy, and should be permanently disabled.
While it is shut down, the cache is not being continuously scrubbed by ECC or parity allowing bit errors to accumulate and defeat the ECC or parity after it is powered up. Invalidating and reloading the contents of the cache makes perfect sense in this situation.
Hi, I'm a software engineer working on embedded computers flying on satellites. Single upset events are a common occurrence up in space, even on low earth orbit. And modern COTS chips are more vulnerable than chips of yore. RADHARD chips are old slow and expensive. They have fat thick lines that aren't as easily bumped by radiation. Satellites up on GEO might have it worse, but LEO still has problems.
The last time I checked, the reason radiation hardened processes used much larger minimum feature sizes was simply because it was not economical to produce a denser radiation hardened process. More modern fabrication processes require an economy of scale which is not available for such a small market.
With modern processors being built ont the 14 nanometres process this becones a serious problem.
Susceptibility is more complicated than just the minimum feature size. It was a serious problem generations ago.
Denser processes use gate insulators with a higher dielectric constant to store more charge and also provide more drive for a given area. These things make a process more resistant to radiation induce soft errors. The same things caused the susceptibility of DRAM processes to level off or even decrease slightly starting a couple generations ago.
I think you are confusing SRAM and DRAM.
DRAM soft error rates leveled off a couple generations ago. SRAM soft error rates are a couple orders of magnitude higher and have remained so for integrated SRAM caches. A discussion of the difference and why it exists would be interesting.
Other than some odd exceptions, integrated SRAM caches have been protected by ECC or parity almost since they were first used.
The problem is that you need a CPU and north bridge that can handle it, which adds to the initial costs. For Intel, for example, a Xeon CPU costs (artificially) a good deal more than a comparable speed i3/5/7/9, which is an upfront cost that consumers aren't willing to eat, and they tend to choose either a cheaper CPU or a faster CPU for the same kind of money.
In most cases Intel's Xeon and consumer CPUs are the same hardware so the only difference in production might be testing time. Intel's artificial market segmentation of ECC is more about price discrimination then costs which can be seen by their tying ECC to use of the proper south bridge which has nothing to do with it.
What's odd is that ECC is not routinely used in all hardware. Depending on the conditions it can be of great help, as the rare bit flip can cause strange problems that can take ages to track down.
Whether ECC is used or not depends on the likelyhood of an error and how serious the consequences will be. The number of errors depends on how much memory is used (not installed), how long it is used, and oddly enough some factor related to the access rate. Since servers tend to have much more memory and operate for longer times than desktops, ECC makes more sense for them.
Who cares about errors while playing a game or media or doing consumer type tasks which do not tax the computer? But if my workstation is running for days at a time on important work, or I do not want to waste my time programming tracking down even one soft error, or a computer has any effect on human safety, ECC is very economical.
I was unaware that they were in the habit of using materials that suffer from alpha decay when manufacturing electronics (hint, they don't).
They try to avoid radioactive materials in packaging for that very reason however sometimes contamination occurs anyway.
Back during about the 64kbit DRAM generation, this was a huge problem with ceramic packaged parts increasing the demand for plastic packaging despite doubts about its reliability.
S1 i supposed to keep the cache fully powered up. How's it going to make any difference if an alpha particle hits the cache memory cells while the core clock has stopped?
The cache is protected against data corruption by ECC or parity however if multiple bit errors accumulate within one word, this protection fails. During normal operation, the cache is continuously scrubbed of errors so this is not a problem.
Of course, there are many more bits in RAM which could be affected, so a problem is more likely to occur there, which this doesn't address.
High performance integrated SRAM is orders of magnitude more susceptible to radiation induced soft errors than DRAM which is why SRAM caches have included ECC or parity protection almost since they were first used.
Oddly enough, DRAM has actually become more resistant to radiation induced soft errors over the last couple of generations but this is more than cancelled by the increasing amount of DRAM used.
What do you mean? It is only marginally more expensive.
With an AMD system that's the only extra expensive. For Intel, you also need a server class CPU (a 4 core Xeon will do).
For Intel, you also need a C series server class south bridge.
That's a little unfair. The reason that commercial crew has such strict requirements is because of the shitstorm that hit NASA from every direction after the shuttle failures.
NASA did this before the Shuttle failures.
NASA holds other parties to a higher standard than NASA and NASA's contractors. Things which are considered failures if others do them are maintenance issues for NASA.
When NASA found that the Space Shuttle's main engines returned with cracked turbine blades, they redefined this from a failure to a maintenance issue. But if the Merlin engines in SpaceX's Falcon 9 return with cracked turbine blades, it is a failure.
Heat prevents a 3D chip? Lay down a thick layer of heat conductive material, before the next layer of logic. Ok, you won't get 80.000 layers that way, perhaps only 800.
You will not get any layers that way; any thin heat conductive layers between chips just does not support the needed increase in thermal conductivity needed to help significantly.
High performance chips have been thermal limited for many process generations now. Anything which increases the junction to surface thermal resistance will just make them more thermal limited. About the only thing which would help for a single chip is a better heat spreader made of something with a better thermal conductivity than copper like diamond. The power density is so high that even a heat pipe cannot be used without a heat spreader.
That leaves convection cooling through microfluidics to remove heat through the volume of the chip if it is feasible.
The Commerce clause allows them to do stuff like this. Not everything needs to be written out specifically. The Commerce clause because its relative vagueness allows the Fed. government to do a lot of stuff that isn't explicitly stated.
"Interstate" and "commerce" sure are vague.
Instead of jamming, they would probably inject some errors, i.e. Selective Availability, so systems would still 'think' they have a good signal.
Spoofing is much more difficult than jamming military receivers. One reason for the military encryption is authentication to prevent spoofing.
> Sorry folks, but the Brailsford case caused me lose every scrap of respect I once had for the police.
Do you ever question blaming a whole class of people for the worst examples of the class?
I did not after the not worst examples of the class, politicians, judges, and prosecutors covered and supported the worst apples of the class.
... and held accountable.
The good faith exception and qualified immunity sure help with that.
So just because Shakespeare plays are still for sale his heirs should get a royalty for those sales?
Yes because otherwise what incentive will Shakespeare have to produce more content?
We should terraform Antarctica just to piss Bill Nye off.
Who's up for that?
Ice court tennis, anyone?
It would be a great feasibility test with much less risk, at least up until the point were we dig up an alien spaceship which has been buried in the ice for millions of years and recover an occupant. Ok, maybe it is not such a good idea. Forget that I suggested it.