The folks at mindvision made an installer/installer creation tool that allowed one to scan two different sets of files and directories to find differences between them (binary differences) and it would just package up those differences in the installer archive. In fact you could use it to diff and package delta between several versions at once. When the user ran the installer (really and updater) it would apply the binary patch to the file set as needed.
I was using this tool over 7 years ago now on Mac OS so I don't see what is so new about this concept... but I am glad is looks like it starting to be used more.
How did you get "abandoning manned space travel" out of questioning "the continuation of the shuttle program".
Or I guess you are just doing a preemptive post... anyway I agree that manned space travel is must for many many reasons (several emotional or spiritual if you will) but heavy use of robotic exploration and off loading of dangerous tasks to robots should be done in support of this manned mission.
IMHO we need to get off this planet and seed colonies as a responsible action for the continuance of the species here on earth (humans aren't the only species we will be taking of planet).
Actually the inverse square law holds for any thing with a initial fixed density that propagates from a point source.
So say you throw 100 rocks (each with a placard saying "Eat at Joes") out in an even distribution across the night sky then the density of those rocks in a shell centered on and growing out from the earth will reduce in accordance with the inverse square law. The farther you get from the earth the bigger this shell gets and the farther the distance between the rocks in the shell.
This increase in distance between the rocks means we have to get luckier and luckier that someone will actually see one or more of rocks and the little placard on it.
So your statement is non sensical since the inverse square can affect a bunch of rocks or photons.
Of course if we get lucky and someone happens to be inline with a rock they could get the message much better then a weak electromagnetic signal. Of course for every rock we send out we can send out trillions and trillions of photons in focused beams that can get their attention with enough signal strength to be useful. The beam can cover vastly larger areas then a rock ever could (now a rock with a say radio source could be interesting) and they travel just a wee bit faster;-) then a rock.
(I can see it now we launch a rock at a considerable fraction of light speed to get it out to a candidate world in a timely fashion only to get lucky and have a direct hit on their world... booom! Yeah they got the message alright.)
Second the inverse square law comes from the fact that the area of the shell of radiation coming off of a point source (star for example) increases to the square of the radius from the source (basic geometry). Yet the amount of energy (number of photons in the case of electromagnetic radiation) that is in that shell of radiation is constant so the density of those photons reduces by the inverse of the square of the distance (See this for a graphical explination.)
So if you look at a given photon traveling through space its "signal" will not weaken with the square of the distance, if it did this universe would be a dark dark place (also it would break the concept of quanta).
Also if you have photons traveling parallel to each other then the inverse square law doesn't apply because you have not radius to begin with.
Now it is hard to get fully parallel photons but you can get close (lasers, maser, etc.) and the closer you get the greater the radius of the theoretical point source for the signal. The greater the radius of the point source the father the signal can propagate before the exponential effects of the inverse square law begins to take hold.
So yes it is likely that the inverse square law applies to signals such as these but the point source radius to use in the calculation can be relatively huge if you take steps to focus the signal (attempt to have the photons travel in a parallel beam).
I don't really care for Kerry (the candidate not the man) nor do I like all that Bush has done... anyway well said about how personal/group desire often lead to extreme interpretations / mischaracterizations.
It makes addressing the real issues that much harder... such is politics these days it seems (or maybe always).
I am a Mac OS X user and Mac developer but what Finder has is not close to what WinFS could allow searching wise (yeah it is faster on average then searching on Windows currently via filename) and Spotlight should nearly match WinFS in search capabilities (but lag slightly in aspects of index update speed). WinFS however allows more then just searching, it is attempting to allow the sharing of data between applications, like a data soup (the Newton reborn on the desktop:-).
To do this however comes at a cost of having to reimplement aspects of current application to understand and package data in the way WinFS desires... this is the main road block for WinFS that I see.
Yes I did and thanks for the concern about my reading comprehension abilities.
Each core own indenpent L1's so there is common cahce as the original post talked about.
The original post made no mention of L1 you are assuming that. Yes the L1 is NOT shared (as I stated before). No multi-core CPU will likely ever share L1 since that is often rather integrated/intertwined with the core itself.
The L2 - there are 3 "three separate, autonomous cache controllers" again not a common single 1
The L2 is shared by the cores (note "The two processors share a unified second level cache, also onboard the chip") and this is what folks have been generally talking about in this topic. The fact that the L2 is implemented as "three separate, autonomous cache controllers" doesn't change this fact. Each core connects to a cross bar that interfaces it with the L2 (or out to L3, etc.) and each core can access any one of the three L2 cache banks. This is done to allow them to share the L2 cache more easily since while one it pulling a cache line from one L2 bank/controller another can be doing the same with a different controller... think of it as something like dual ported RAM. They can also directly share data in the cache this way.
The L3 - external controller - there is one of these but there are 2 banks
The same applies as above to the L3 and so on. Look at the picture if you are confused.
In fact if you go read the article you may see the context that folks are discussing better, to quote...
Similarly, each core of the dual-core Opteron will have separate caches, said Marius Evers, a researcher at AMD. Putting two cores on one chip increases computing performance while controlling power consumption, a major problem facing designers.
Splitting the cache differs from the approach taken by IBM, which came out with the first dual-core server chip with the Power 4, according to Kevin Krewell, editor in chief of the Microprocessor Report.
So if folks had been talking about L1 then the above would be incorrect but since they are talking about L2 things make sense.
So the kernel can use 16 GB of RAM but the applications can't?
Well yes and no (my wording wasn't the clearest). The virtual memory system can manage 64 bits worth of physical memory (in current G5s the system can support up to 16GB of physical RAM however Apple only support 8GB at the moment given DIMM densities). The kernel itself isn't able to use all of that memory directly itself since it is still using 32b address and will remain 32b for the known future.
Is there ever a situation where this is useful?
Yes.
For one each process, including the kernel itself, has its own virtual memory space that can grow up to 4GB in size (32 bit addressing). So say you have 4 processes each with a 2GB working set (they use 2GB of RAM at a time), 4 * 2 = 8 GB of RAM. Since the VM system (an aspect of the kernel) can manage that much RAM all of those processes will be able to get the physical RAM they need and avoid swapping.
Additionally on Mac OS X the VM system shares its page pool with the file caching aspect of IO sub-system, this is called the Universal Buffer Cache (UBC). The UBC intentionally will cache file data read in, as of yet unused, pages of physical memory. This has the effect (given enough time or file data loading) of using all free physical memory in the system to cache file data. Doing this can greatly reduce load times of application or files that have been cached in by the UBC (memory access is many many times fast then disk access).
Now if a process or the UBC needs a physical page and no more free pages are available then (in general) the least recently used cache page is reused (the cache file data is forgotten, no page out need because it is only caching data not changed data). This is as fast as using a free page.
Anyway between the ability to run more memory hungry applications before swapping (assuming you have larger amounts of physical RAM installed) at once and the ability of the UBC to leverage all available free RAM you can get a lot of gain out of the this capability of Mac OS X's VM system without the overhead of having to go all 64 bit.
In fact using mapping tricks and the behavior of the UBC one can simulate an application with an address space larger then 32 bits in size (using a sliding window of mapped in memory from a map file for example).
Did you bother to look at the link the parent provided?
Each core of the Power4 shares the L2 cache bank and L3 cache on a given die. This is exactly what folks are talking about when the say shared or independent caches (of course the L1 cache are not shared since they are really part of the core).
To quote...
The components of the POWER4 chip are shown in Figure 1. The chip has two processors on board. Included in what we are referring to as the processor are the various execution units and the split first level instruction and data caches. The two processors share a unified second level cache, also onboard the chip, through a Core Interface Unit (CIU) in Figure 1. The CIU is a crossbar switch between the L2, implemented as three separate, autonomous cache controllers, and the two processors. Each L2 cache controller can operate concurrently and feed 32 bytes of data per cycle. The CUI connects each of the three L2 controllers to either the data cache or the instruction cache in either of the two processors. Additionally, the CUI accepts stores from the processors across 8-byte wide buses and sequences them to the L2 controllers. Each processor has associated with it a Noncacheable (NC) Unit, the NC Unit in Figure 1, responsible for handling instruction serializing functions and performing any noncacheable operations in the storage hierarchy. Logically, this is part of the L2.
The directory for a third level cache, L3, and logically its controller are also located on the POWER4 chip. The actual L3 is on a separate chip. A separate functional unit, referred to as the Fabric Controller, is responsible for controlling data flow between the L2 and L3 controller for the chip and for POWER4 communication. The GX controller is responsible for controlling the flow of information in and out of the system. Typically, this would be the interface to an I/O drawer attached to the system. But, with the POWER4 architecture, this is also where we would natively attach an interface to a switch for clustering multiple POWER4 nodes together.
Also note not all POWER4 chips are packaged into 8 chip module.
Yeah my old Dual G4 wind-tunnel sits off in the corner silent with no power attached... I only power it up to do 2 machine debugging and only when I must.
Pulling in a post of mine from a completely different forum...
The G5 is a 64 bit processor and OSX Panther is a 64 bit OS.:)
Panther is not a true 64 bit OS in the traditional sense of the word. It does not support 64 bit addressing[1]. It does however support the use of 64 bit math operations and the saving of related registers on the CPU.
Tiger (Mac OS 10.4) will have the first steps towards a true 64 bit OS by allowing 64 bit addressing (virtual addressing) to be used for libSystem only based tools (command line applications, no GUIs, etc.). At least that is all that Apple has so far committed to doing in Tiger at this time (cannot say more because of NDA).
[1] Note the Panther kernel has support for 64 bit physical addressing so the system can utilize greater then 4 GBs of RAM (hardware wise supporting up to 16 GB of RAM) but it does not support 64 bit virtual addressing (what applications use) at this time.
The G5 (PPC970/970FX) has a two 32 bit wide buses one going in each direction from the CPU and they have a data rate at half that of the CPUs clock rate. At a clock rate of 2.5GHz the bus is capable of a max theoretical throughput of 5GB/s each direction or 10GB/s in total (that is per CPU). Real world throughput is around 8 GB/s per CPU at 2.5GHz because of address/command overhead. Apple/IBM terms this the elastic bus and it is not HT based.
Anyway the the post you are replying to is incorrect about each CPU having its own RAM. That is not true. Each CPU has it own independent bus to the memory controller (U3/U3H) and that controller has a dual channel connection memory capable of 6.4GB/s a second (DIMMS are required to be added in pairs to allow for a 128 bit wide path to memory). The U3 chip is basically cross bar like internally allowing for a few point-to-point connections to be taking place between its various interfaces (CPU to CPU, AGP to memory, etc.).
HT is used for as a secondary interconnect to relatively lower bandwidth devices in the IO chain.
By "Korea" I assume you mean South Korea. I doubt that many folks (on the scale of other nations) in North Korea have networking to the home let alone broadband.
Actually Hubble is just at the upper edge of the orbit that the shuttle can obtain. It is not clear, at least to me yet, that given the safety changes requested to be made to the shuttle (adding new systems, back up capabilities and plans) if the shuttle could still achieve such orbits any longer. For example some of the fall back plans require visiting the ISS which I doubt they could have the fuel for given the large difference between the Hubble and ISS orbits.
I would love to see humans go up an do it since we know that works. In reality all that has changed in the perceptions of the risks to those humans...
Anyways I am also all for the use of robots. Not only will such a mission (hopefully) extend the life the Hubble but it will help advance robot technology in the field of maintenance and construction. This is the exact type of technology that will be needed to achieve a moon installation and future installations and orbiting stations.
If the technology can be developed it could reduce the cost of the deployment and upkeep of orbit based science equipment. In the long run it is a lot cheaper to send up robots then humans and can greatly expand the orbits achievable and even could allow maintenance at Lagrange points.
You do realize the large difference between the US population in the late 18th and early 19th centuries and that of today (start of the 21st century). Also a huge difference exists between the economy of today and then.
Those all play into the a large increase of patents granted in the last 100 years or so.
Slashdot Mirror
The Genesis device and effect was fake?
Hey smart guy if it was fake how the hell did Spock get reborn., hummm?
Me thinks you are lying and trying to cover something up.
The folks at mindvision made an installer/installer creation tool that allowed one to scan two different sets of files and directories to find differences between them (binary differences) and it would just package up those differences in the installer archive. In fact you could use it to diff and package delta between several versions at once. When the user ran the installer (really and updater) it would apply the binary patch to the file set as needed.
I was using this tool over 7 years ago now on Mac OS so I don't see what is so new about this concept... but I am glad is looks like it starting to be used more.
How did you get "abandoning manned space travel" out of questioning "the continuation of the shuttle program".
Or I guess you are just doing a preemptive post... anyway I agree that manned space travel is must for many many reasons (several emotional or spiritual if you will) but heavy use of robotic exploration and off loading of dangerous tasks to robots should be done in support of this manned mission.
IMHO we need to get off this planet and seed colonies as a responsible action for the continuance of the species here on earth (humans aren't the only species we will be taking of planet).
Flamebait? what? I was pointing out he had a good point but I could not mod it up because I already had posted in this thread...
Very very good point. (I would mod you up if I could...)
Actually the inverse square law holds for any thing with a initial fixed density that propagates from a point source.
;-) then a rock.
So say you throw 100 rocks (each with a placard saying "Eat at Joes") out in an even distribution across the night sky then the density of those rocks in a shell centered on and growing out from the earth will reduce in accordance with the inverse square law. The farther you get from the earth the bigger this shell gets and the farther the distance between the rocks in the shell.
This increase in distance between the rocks means we have to get luckier and luckier that someone will actually see one or more of rocks and the little placard on it.
So your statement is non sensical since the inverse square can affect a bunch of rocks or photons.
Of course if we get lucky and someone happens to be inline with a rock they could get the message much better then a weak electromagnetic signal. Of course for every rock we send out we can send out trillions and trillions of photons in focused beams that can get their attention with enough signal strength to be useful. The beam can cover vastly larger areas then a rock ever could (now a rock with a say radio source could be interesting) and they travel just a wee bit faster
(I can see it now we launch a rock at a considerable fraction of light speed to get it out to a candidate world in a timely fashion only to get lucky and have a direct hit on their world... booom! Yeah they got the message alright.)
1/r^2 stands true for all electromagnetic waves. That means the intensity of the signal will decrease by the square of its distance.
This isn't a true statement depending on what exactly you mean...
For one the range of the electromagnetic force is infinite (see this for more information).
Second the inverse square law comes from the fact that the area of the shell of radiation coming off of a point source (star for example) increases to the square of the radius from the source (basic geometry). Yet the amount of energy (number of photons in the case of electromagnetic radiation) that is in that shell of radiation is constant so the density of those photons reduces by the inverse of the square of the distance (See this for a graphical explination.)
So if you look at a given photon traveling through space its "signal" will not weaken with the square of the distance, if it did this universe would be a dark dark place (also it would break the concept of quanta).
Also if you have photons traveling parallel to each other then the inverse square law doesn't apply because you have not radius to begin with.
Now it is hard to get fully parallel photons but you can get close (lasers, maser, etc.) and the closer you get the greater the radius of the theoretical point source for the signal. The greater the radius of the point source the father the signal can propagate before the exponential effects of the inverse square law begins to take hold.
So yes it is likely that the inverse square law applies to signals such as these but the point source radius to use in the calculation can be relatively huge if you take steps to focus the signal (attempt to have the photons travel in a parallel beam).
Yeah if you like having a 17"+ tablet on your laptop or under your arm. :-)
I don't really care for Kerry (the candidate not the man) nor do I like all that Bush has done... anyway well said about how personal/group desire often lead to extreme interpretations / mischaracterizations.
It makes addressing the real issues that much harder... such is politics these days it seems (or maybe always).
I am a Mac OS X user and Mac developer but what Finder has is not close to what WinFS could allow searching wise (yeah it is faster on average then searching on Windows currently via filename) and Spotlight should nearly match WinFS in search capabilities (but lag slightly in aspects of index update speed). WinFS however allows more then just searching, it is attempting to allow the sharing of data between applications, like a data soup (the Newton reborn on the desktop :-).
To do this however comes at a cost of having to reimplement aspects of current application to understand and package data in the way WinFS desires... this is the main road block for WinFS that I see.
I wonder if the page in / out counter only counts pages which weren't RAM cached?...
Yeah those only count pages faults to and from disk as I understand it and cache pages don't need to be faulted to disk.
On Mac OS X consider "free" + "inactive" to be your total available memory (cache pages are counted as part of inactive).
Oops... this post
Just so you know the G5s don't have separate banks of RAM as you imply... see my other post [slashdot.org].
Did you understand what you read?
Yes I did and thanks for the concern about my reading comprehension abilities.
Each core own indenpent L1's so there is common cahce as the original post talked about.
The original post made no mention of L1 you are assuming that. Yes the L1 is NOT shared (as I stated before). No multi-core CPU will likely ever share L1 since that is often rather integrated/intertwined with the core itself.
The L2 - there are 3 "three separate, autonomous cache controllers" again not a common single 1
The L2 is shared by the cores (note "The two processors share a unified second level cache, also onboard the chip") and this is what folks have been generally talking about in this topic. The fact that the L2 is implemented as "three separate, autonomous cache controllers" doesn't change this fact. Each core connects to a cross bar that interfaces it with the L2 (or out to L3, etc.) and each core can access any one of the three L2 cache banks. This is done to allow them to share the L2 cache more easily since while one it pulling a cache line from one L2 bank/controller another can be doing the same with a different controller... think of it as something like dual ported RAM. They can also directly share data in the cache this way.
The L3 - external controller - there is one of these but there are 2 banks
The same applies as above to the L3 and so on. Look at the picture if you are confused.
In fact if you go read the article you may see the context that folks are discussing better, to quote...
Similarly, each core of the dual-core Opteron will have separate caches, said Marius Evers, a researcher at AMD. Putting two cores on one chip increases computing performance while controlling power consumption, a major problem facing designers.
Splitting the cache differs from the approach taken by IBM, which came out with the first dual-core server chip with the Power 4, according to Kevin Krewell, editor in chief of the Microprocessor Report.
So if folks had been talking about L1 then the above would be incorrect but since they are talking about L2 things make sense.
So the kernel can use 16 GB of RAM but the applications can't?
Well yes and no (my wording wasn't the clearest). The virtual memory system can manage 64 bits worth of physical memory (in current G5s the system can support up to 16GB of physical RAM however Apple only support 8GB at the moment given DIMM densities). The kernel itself isn't able to use all of that memory directly itself since it is still using 32b address and will remain 32b for the known future.
Is there ever a situation where this is useful?
Yes.
For one each process, including the kernel itself, has its own virtual memory space that can grow up to 4GB in size (32 bit addressing). So say you have 4 processes each with a 2GB working set (they use 2GB of RAM at a time), 4 * 2 = 8 GB of RAM. Since the VM system (an aspect of the kernel) can manage that much RAM all of those processes will be able to get the physical RAM they need and avoid swapping.
Additionally on Mac OS X the VM system shares its page pool with the file caching aspect of IO sub-system, this is called the Universal Buffer Cache (UBC). The UBC intentionally will cache file data read in, as of yet unused, pages of physical memory. This has the effect (given enough time or file data loading) of using all free physical memory in the system to cache file data. Doing this can greatly reduce load times of application or files that have been cached in by the UBC (memory access is many many times fast then disk access).
Now if a process or the UBC needs a physical page and no more free pages are available then (in general) the least recently used cache page is reused (the cache file data is forgotten, no page out need because it is only caching data not changed data). This is as fast as using a free page.
Anyway between the ability to run more memory hungry applications before swapping (assuming you have larger amounts of physical RAM installed) at once and the ability of the UBC to leverage all available free RAM you can get a lot of gain out of the this capability of Mac OS X's VM system without the overhead of having to go all 64 bit.
In fact using mapping tricks and the behavior of the UBC one can simulate an application with an address space larger then 32 bits in size (using a sliding window of mapped in memory from a map file for example).
Each core of the Power4 shares the L2 cache bank and L3 cache on a given die. This is exactly what folks are talking about when the say shared or independent caches (of course the L1 cache are not shared since they are really part of the core).
To quote...
Also note not all POWER4 chips are packaged into 8 chip module.
Yeah my old Dual G4 wind-tunnel sits off in the corner silent with no power attached... I only power it up to do 2 machine debugging and only when I must.
Pulling in a post of mine from a completely different forum...
:)
The G5 is a 64 bit processor and OSX Panther is a 64 bit OS.
Panther is not a true 64 bit OS in the traditional sense of the word. It does not support 64 bit addressing[1]. It does however support the use of 64 bit math operations and the saving of related registers on the CPU.
Tiger (Mac OS 10.4) will have the first steps towards a true 64 bit OS by allowing 64 bit addressing (virtual addressing) to be used for libSystem only based tools (command line applications, no GUIs, etc.). At least that is all that Apple has so far committed to doing in Tiger at this time (cannot say more because of NDA).
[1] Note the Panther kernel has support for 64 bit physical addressing so the system can utilize greater then 4 GBs of RAM (hardware wise supporting up to 16 GB of RAM) but it does not support 64 bit virtual addressing (what applications use) at this time.
My dad just got his and it is quieter then a little 80GB hard drive he had sitting running on the corner of his desk, his words almost to the T.
My first generation G5 (dual 2GHz) is also almost as quiet.
This is incorrect, see my other post.
Actually they don't use the same bus technology.
The G5 (PPC970/970FX) has a two 32 bit wide buses one going in each direction from the CPU and they have a data rate at half that of the CPUs clock rate. At a clock rate of 2.5GHz the bus is capable of a max theoretical throughput of 5GB/s each direction or 10GB/s in total (that is per CPU). Real world throughput is around 8 GB/s per CPU at 2.5GHz because of address/command overhead. Apple/IBM terms this the elastic bus and it is not HT based.
For more information see this block diagram referenced from this hardware tech note.
Anyway the the post you are replying to is incorrect about each CPU having its own RAM. That is not true. Each CPU has it own independent bus to the memory controller (U3/U3H) and that controller has a dual channel connection memory capable of 6.4GB/s a second (DIMMS are required to be added in pairs to allow for a 128 bit wide path to memory). The U3 chip is basically cross bar like internally allowing for a few point-to-point connections to be taking place between its various interfaces (CPU to CPU, AGP to memory, etc.).
HT is used for as a secondary interconnect to relatively lower bandwidth devices in the IO chain.
By "Korea" I assume you mean South Korea. I doubt that many folks (on the scale of other nations) in North Korea have networking to the home let alone broadband.
Sorry you got +4 Insightful not +3 Informative, try again.
Actually Hubble is just at the upper edge of the orbit that the shuttle can obtain. It is not clear, at least to me yet, that given the safety changes requested to be made to the shuttle (adding new systems, back up capabilities and plans) if the shuttle could still achieve such orbits any longer. For example some of the fall back plans require visiting the ISS which I doubt they could have the fuel for given the large difference between the Hubble and ISS orbits.
I would love to see humans go up an do it since we know that works. In reality all that has changed in the perceptions of the risks to those humans...
Anyways I am also all for the use of robots. Not only will such a mission (hopefully) extend the life the Hubble but it will help advance robot technology in the field of maintenance and construction. This is the exact type of technology that will be needed to achieve a moon installation and future installations and orbiting stations.
If the technology can be developed it could reduce the cost of the deployment and upkeep of orbit based science equipment. In the long run it is a lot cheaper to send up robots then humans and can greatly expand the orbits achievable and even could allow maintenance at Lagrange points.
You do realize the large difference between the US population in the late 18th and early 19th centuries and that of today (start of the 21st century). Also a huge difference exists between the economy of today and then.
Those all play into the a large increase of patents granted in the last 100 years or so.