The most recent (March) compatibility update adds a feature to the properties page for shortcuts that allows you to run the program in a choice of compatibility layers (win95/win98/nt4sp5).
Has anyone ever used Kahn? That program rocked. It emulated an IPX network over the net. It used a form of compression. Kahn was usable in '96 and there was almost not lag with 28.8 modems.
I don't think developers have given any thought to developing some sort of compression algorithm for slow connections. They could really reach a large market with something like Q3.
2. The use of hardware 3D acceleration of any sort is forbidden. Software 3D engines are not forbidden, but the game must run at 20 frames per second or better in 640 x 480 16-bit SVGA mode or the nearest available equivalent.
2.5. This will include the eventual phasing out of all new technology and an eventual regression back to board games, such as checkers.
Yes a shorter trace helps increase clock. I was refering to this:
The problem is that it's a bit of a false gain. Most of the performance gained in clock speed is lost again to the serious hit you take at each branch misprediction. If you could keep your ultra-long pipe full, you'd be cruising, but you can't. Occasionally you will mispredict, and have to flush that pipe. One your pipe becomes as deep at the P4, that performance hit starts eating your lunch. Suddenly, most of your processor is sitting empty most of the time.
So, clock-for-clock P4's get slaughtered by Athlons or PIII's. But Intel doesn't care. They know that the majority of consumers buy based solely on that magical MHz/GHz number. Most consumers are not sophisticated enough to realize that there is more to performance to clock rate
I hope you realize that this is a fundimental CPU design. If AMD wants the Athlon to go beyond 2GHz they will have to make a deeoper pipeline. The Athlon has already incresed the pipe from ten stages to twelve. If any CPU maker decides to make a fast CPU it must have something to feed it data. Pipelining is the way bot AMD and Intel solve this problem.
This Moore's law has to hit a limit someplace, doesn't it? The next generation of even faster stuff is already on the map. Maybe 2 Gig by this time next year. Wow. How do they do it and keep it innexpensive?
Moore's law doesn't have anything to do with speed. It has to do with doubling the # of transistors that can be fit onto a chip.
When you increase the clock speed you also need to increase the rate it receives data. The P4 is optimized for higher clock speeds than 2 GHz. You can expect this chip to reach near 10 GHz. This is due to the 20-stage pipeline. Without a 20 stage pipeline it will be sitting there wasting cycles.
Cache misses - too big a pipeline
You have a 20-stage pipeline and you have a cache miss. The whole pipeline must be dumped when there is a miss. The bigger your pipeline the bigger your odds of a miss. The CPU must go to memory to get data since the pipeline is wrong. It may have to go to L1, L2, main memory, etc.
Slow clock - smaller pipeline - less performance hit
So, if you have a slower clocked CPU you make the pipeline smaller since its need for data isn't as bad as a CPU that is clocked at 5 GHz. This makes it easier to design, puts less emphasis on brach prediction, and makes it less costly.
Not Linear
The CPU's performance is not directly related to clock speed. It is definitely not linear. There is an elbow at the end of the graph. The beginning of the P4 graph will not be linear either, start out slow. Performance will not be in direct relation to GHz.
History Repeats Itself
Doesn't anyone remember when the Pentium classic came out? 486s were running circles around it. The Pentium 233 MMX is faster than a Pentium 2 233 with 16-bit code.
So you know: Pentium classic has a 5-stage pipeline, P2 & P3 has 10 stages, P4 has 20 stages. Athlons have 10 and new Athlons have 12.
OK, the alternative to this would be to limit and stop some the # of children born, totaly upend some industries like the auto and computer industry, and spend a boatload of money/rescources trying to repair what is already broke.
Face it people - human infestation is a cancer. -
I think you have quoted a line from the Matrix. I guess that says where your train of thought is coming from.
I read the an article a while back that said the same thing. It pretty much ruled out any possibility of colonizating Mars because its magnetic field. It is scattered, not polarized, and weak.
Multiple processor machines will not become commonplace. Maybe CPUs will have more parallelism built into them, but 2 separate CPUs is not a cost effective solution to be considered commonplace.
Slashdot Mirror
The most recent (March) compatibility update adds a feature to the properties page for shortcuts that allows you to run the program in a choice of compatibility layers (win95/win98/nt4sp5).
With Windows 2000?
I don't see that anywhere.
Has anyone ever used Kahn? That program rocked. It emulated an IPX network over the net. It used a form of compression. Kahn was usable in '96 and there was almost not lag with 28.8 modems.
I don't think developers have given any thought to developing some sort of compression algorithm for slow connections. They could really reach a large market with something like Q3.
2. The use of hardware 3D acceleration of any sort is forbidden. Software 3D engines are not forbidden, but the game must run at 20 frames per second or better in 640 x 480 16-bit SVGA mode or the nearest available equivalent.
2.5. This will include the eventual phasing out of all new technology and an eventual regression back to board games, such as checkers.
According to this article, there will be, basically, 2 versions of Office 10. A subscription based and nonsubscription.
I know mobile celerons using 100 Mhz bus started at 450 Mhz.
the first Celereon to use a 100 Mhz FSB
If anyone knew what they were doing, the Celeron 266 was the first Celeron to use 100 MHz FSB.
news anyone?
Ouch! Industrial strength. That must hurt.
I used to use my old Atari 400 to store progs on a modified cassette player.
It takes Torvalds 2.0 20 years to boot up.
www.tomshardware.com
It preforms slower than the Giga P3 for kernel compiles.
Yes a shorter trace helps increase clock. I was refering to this:
The problem is that it's a bit of a false gain. Most of the performance gained in clock speed is lost again to the serious hit you take at each branch misprediction. If you could keep your ultra-long pipe full, you'd be cruising, but you can't. Occasionally you will mispredict, and have to flush that pipe. One your pipe becomes as deep at the P4, that performance hit starts eating your lunch. Suddenly, most of your processor is sitting empty most of the time.
So, clock-for-clock P4's get slaughtered by Athlons or PIII's. But Intel doesn't care. They know that the majority of consumers buy based solely on that magical MHz/GHz number. Most consumers are not sophisticated enough to realize that there is more to performance to clock rate
This depends on the compiler. New versions from Microsoft or Borland should have this option.
I hope you realize that this is a fundimental CPU design. If AMD wants the Athlon to go beyond 2GHz they will have to make a deeoper pipeline. The Athlon has already incresed the pipe from ten stages to twelve. If any CPU maker decides to make a fast CPU it must have something to feed it data. Pipelining is the way bot AMD and Intel solve this problem.
This Moore's law has to hit a limit someplace, doesn't it? The next generation of even faster stuff is already on the map. Maybe 2 Gig by this time next year. Wow. How do they do it and keep it innexpensive?
Moore's law doesn't have anything to do with speed.
It has to do with doubling the # of transistors that can be fit onto a chip.
Performance is not linear.
Comp Org 101
Wasting cycles
When you increase the clock speed you also need to increase the rate it receives data. The P4 is optimized for higher clock speeds than 2 GHz. You can expect this chip to reach near 10 GHz. This is due to the 20-stage pipeline. Without a 20 stage pipeline it will be sitting there wasting cycles.
Cache misses - too big a pipeline
You have a 20-stage pipeline and you have a cache miss. The whole pipeline must be dumped when there is a miss. The bigger your pipeline the bigger your odds of a miss. The CPU must go to memory to get data since the pipeline is wrong. It may have to go to L1, L2, main memory, etc.
Slow clock - smaller pipeline - less performance hit
So, if you have a slower clocked CPU you make the pipeline smaller since its need for data isn't as bad as a CPU that is clocked at 5 GHz. This makes it easier to design, puts less emphasis on brach prediction, and makes it less costly.
Not Linear
The CPU's performance is not directly related to clock speed. It is definitely not linear. There is an elbow at the end of the graph. The beginning of the P4 graph will not be linear either, start out slow. Performance will not be in direct relation to GHz.
History Repeats Itself
Doesn't anyone remember when the Pentium classic came out? 486s were running circles around it. The Pentium 233 MMX is faster than a Pentium 2 233 with 16-bit code.
So you know: Pentium classic has a 5-stage pipeline, P2 & P3 has 10 stages, P4 has 20 stages. Athlons have 10 and new Athlons have 12.
I don't think the strength of the software has anything to do with it.
Its all about marketing.
Was Windows 3.1 better than OS2?
Is Linux less a server than Win NT?
MS has the marketing muscle to push through anything it wants. Indrema sound like a good system, but there will be no way to market it.
Indrema will have a short lived life.
This is government work at its best.
The government hires a federal convict to advise them on a subject that they have no understanding on.
I do know the magnetic field is not strong enough to provide the protection that we are used to having here on earth.
The rover that landed a few years back was tested for exposure to radiation that would be similiar to that of Mars.
The electronics involved were designed to reboot every so often. This was due to solar radiation effecting the way it preformed.
I would guess that would be too much for us as well.
Some people have talked about putting dust in the amosphere to help shield Mars.
Face it people - human infestation is a cancer. -
I think you have quoted a line from the Matrix. I guess that says where your train of thought is coming from.
I read the an article a while back that said the same thing. It pretty much ruled out any possibility of colonizating Mars because its magnetic field. It is scattered, not polarized, and weak.
Would the fact that it is faster the second time around have a positive effect on recursive programming, AI, lisp, etc...?
Yea, having a chipset that isn't made by VIA will be nice.
The VIA chipsets are very flaky.
Multiple processor machines will not become commonplace. Maybe CPUs will have more parallelism built into them, but 2 separate CPUs is not a cost effective solution to be considered commonplace.
It depends on which version of code morphing software you have.
.pdf files. There is no mention as to exactly what it morphs.
I know that as of now it doesn't support MMX, because it generated too much heat.
I've looked all over the crusoe web site and their
Does anyone have an idea how people plan to benchmark this processor?
One feature of the Crusoe processor's emulation is that it gets faster with repetition.
How is this going to work if a benchmark was to be run 3 times?