Actually, in recent times there have been papers published on how to create cpus which are tolerant in the face of cosmic radiation. Two examples could be Todd Austin's DIVA research http://www.eecs.umich.edu/~taustin/papers/micro32_ diva.pdf and reinhart's Transient Fault Detection Via Simultaneous Multithreading http://www.eecs.umich.edu/~stever/pubs/isca00-srt. pdf.
They take two separate approaches. DIVA puts a second, small cpu on the core which checks all work performed by the primary cpu. The multithreading paper executes two redundant copies of a program, checking that the results generated between the two agree (on the same processor, using simultaneous multithreading).
Itanium has a lot less complexity in instruction fetch / issue / execute etc. So, it seems to me like this is a contradiction of what you said. It is wider (6 instructions) as opposed to the 3 instructions of pentium 3 etc. Just look at the spec numbers though (hint, the p3 1ghz beats it and costs 1/50 as much (or some similar small fraction))...
Computers have taken advantage of parallelism for a long time. Most scientific applications (which I guess you're representing by a repeated floating addition) have trememndous amounts of parallelism...
Man, I don't want to be rude, but how could you fail to get the meaning out of the single sentence I wrote? I said, "life, death and resurrection" It is the resurrection of christ which is the ultimate testament to his being the son of god.
The last time I bothered to provide evidence at the request of others it ended up being a total waste of time, without them even bothering to read it. I'll be glad to provide evidence if you'll actually read it...
And note, I didn't say proof (that was another pointless argument that came out of it)...
No, because they idea is for people to either never have a chance of hitting 3 gigs (like my parents) or to be terrified of doing so because of the high charges for going over...
Heh, well I appreciate the benefit of the doubt... actually though, I don't think I deserve it... A lot of that just came out of my inability to handle stress in recent times... with the previous papers I've written, I've always had some amount of supervision, but with the one I'm working on now I'm largely on my own except for weekly meetings with my advisor, and around a month ago I was going fairly insane while trying to make progress;)... anyway, that's past now, so maybe I ought to just knock this stuff off... anyway...
As far as testing ideas, you are correct. While we'd love to build real processors to test ideas, obviously that's impossible. What you do is you spend a little while and write a program which simulates the performance of the processor you're modeling. Then, you run it on some program (we generally use the SPEC benchmarks (spec.org if you're unfamiliar with them) and get some performance number (say, average of 1.3 instructions executed per simulated clock cycle). Then, you make some change to your simulated processor and execute it again, and see what new performance you get... you do that about a billion times and boom... a paper;)... seriously, I have to wonder if computer architects are the only real market for faster processors, since we can ALWAYS use more cycles (in the lab at this school we have 4 667 mhz 21264, 4 500 mhz 21264 and 14 500mhz 21164 and we'd still love to have more machines;))...
Obviously because we're not executing on real hardware, the numbers we get aren't as accurate as real silicon, so you have to get really good performance gains to convince people of your ideas... usually 10-15% is considered the target to make your work publishable. The paper I did on Itanium got much higher speedups (76%) because the benchmarks represented sort of pathological cases for the architecture. Thus, the benefit of the work I did achieved a huge gain... Of course, if you have the time you can make a simulator that is highly accurate compared to real hardware, but the time investment is huge and it doesn't make your work that much more publishable... If you're interested, you can get a very commonly used simulator from simplescalar.org Most papers published use that simulator as a base.
It generally takes 5-8 years or more for architecture research at the academic level to work its way into commercial processors... if you work for intel maybe it takes only 3-5 years...
As far as your itanium question, I'm not sure if I really can answer that... I don't know much about the low level workings of itanium... what I was working on was as I described above--a high level software emulation of itanium. I was interning there actually, and they did have a highly accurate simulator, but my mentor indicated that it would take me a long time to learn the existing code base, so instead we interfaced their existing infrastructure to an processor simulator similar to simplescalar (but one I was more familiar with). So, things were at a high level... the lowest level I got to on it was like, how many load/store units does it have, how big of caches are we going to model etc.
What I mean to say is, when you compile code for the ppro or a later processor, the code that is being generated looks like a lot less like cisc code and a lot more like risc code...
Can you back up this claim that compiling for CISC is significantly easier?
First of all... p3 and p4 are basically risc processors anyway... while they support all the old instructions, most compilers only use the most risc like ones because those are the most efficiently implemented on the processor (it's slower to use the hardware string compares than to just do it manually etc).
Here is the abstract from two of my papers...
This one is being presented in about a month in sweden
This paper explores Speculative Precomputation, a technique that uses idle thread contexts in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. This technique is evaluated by simulating the performance of a research processor based on the Itanium(TM) ISA supporting Simultaneous Multithreading.
Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30\% are achieved when assuming ideal hardware. However, this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly
spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.
this one was presented about 18 months ago...
This paper describes the Miss Classification Table, a simple mechanism that enables the processor or memory controller
to identify each cache miss as either a conflict miss or a capacity (non-conflict) miss. The miss classification table works by storing part of the tag of the most recently evicted line of a cache set. If the next miss to that cache set has a matching tag, it is identified as a conflict miss. This technique correctly identifies 87\% of misses in the worst case.
Several applications of this information are demonstrated, including improvements to victim caching, next-line prefetching, cache exclusion, and a pseudo-associative cache. This paper also presents the Adaptive Miss Buffer (AMB), which combines several of these techniques, targeting each miss with the most appropriate
optimization, all within a single small miss buffer. The AMB's combination of techniques achieves 16% better
performance than any single technique alone.
regarding the insulting me etc crap... I mean, it's what I deserve right? I've been disrupting slashdot for my own selfish reasons, however lame they may be. I've actually started feeling guilty about not contributing anything to it and just wasting everyone's time... I stopped coming back as often because of this... so, anyway, I think it's amusing that you actually took the time to look at the past messages I posted etc:)...
haha... well, I make lots of pointless posts yes... slashdot is a total joke and when I'm bored... whatever... I realize it's pretty stupid... I mean, sometimes I'm bored, and this way, I don't have to think before I act... just post useless shit... Oh, and this account is automatically modded down to -1... that's why I post useless shit... because you only see it if you want to... if you set your threshhold at 0 or higher you would be spared of it...
as far as my publications go, I'll be more than happy to point you at them... the question is, why would you believe they were written by me in the first place? you'll probably just accuse me of making it up anyway... anyway, I'll be glad to send you them through email from an address that clearly corresponds to the primary author on them if that'll be proof enough, but I'd ask that you not spread them around (I know my behavior is childish, but I wouldn't want that to reflect on the other authors of the papers...)
think you can swing that?
Worst was when I TAed for a class recently. My university has changed the 'official' language from C to Java (BLAH). In a class full of seniors who were months away from graduation, I had to teach them how to do file IO in C. And these people expect to be hired in a few months? Give me a fucking break...
Back in AP Spanish in high school, my friend and I were amongst the best speakers in the class. We'd speak spanish to each other a lot outside of class etc to get better. The teacher took the approach of allowing the strong students to help the weak ones, so we were never seated next to each other.
The result of this was that I would speak in english to all the people sitting nearby me because they were bad enough at spanish that it was easier to speak to them in english than in spanish. So, in that case, it didn't really benefit anyone...
In classes at my school (UC San Diego) the rule commonly mentioned in classes is the Gilligan's Island rule. What this states is that if you need help from another student it's ok to talk about the program with them, but you have to watch an episode of Gilligan's Island or some other equally brainless activity for half an hour before you touch a keyboard.
Right... maybe the attitude expressed in my earlier post wasn't exactly correct. I think it's great to pursue things even if you have little chance of achieving them... There are two key differences between the example I gave and what this guy is doing
1) No one was arguing 'give this kid a chance, maybe he'll somehow be able to do the work of 20 trained professionals'
2) There was little threat of you causing harm to yourself or others in trying to write your own copy of SF2
I'm on something@home and I get pretty good upload (32k/s max). Since I moved in (4 months) I've uploaded 88,841,174,004 bytes from my ftp server on port 21...
so you can do well sometimes...
Slashdot Mirror
They take two separate approaches. DIVA puts a second, small cpu on the core which checks all work performed by the primary cpu. The multithreading paper executes two redundant copies of a program, checking that the results generated between the two agree (on the same processor, using simultaneous multithreading).
Itanium has a lot less complexity in instruction fetch / issue / execute etc. So, it seems to me like this is a contradiction of what you said. It is wider (6 instructions) as opposed to the 3 instructions of pentium 3 etc. Just look at the spec numbers though (hint, the p3 1ghz beats it and costs 1/50 as much (or some similar small fraction))...
For the kind of program this guy described, it's all about clock frequency since there is no parallelism...
Computers have taken advantage of parallelism for a long time. Most scientific applications (which I guess you're representing by a repeated floating addition) have trememndous amounts of parallelism...
Man, I don't want to be rude, but how could you fail to get the meaning out of the single sentence I wrote? I said, "life, death and resurrection" It is the resurrection of christ which is the ultimate testament to his being the son of god.
And note, I didn't say proof (that was another pointless argument that came out of it)...
There is actually quite a bit of evidence that the bible's account of jesus' life, death and resurrection is accurate, as recorded in the NT...
Posting people's phone numbers is crossing the line asshole
fairtunes.com
Good point
No, because they idea is for people to either never have a chance of hitting 3 gigs (like my parents) or to be terrified of doing so because of the high charges for going over...
As far as testing ideas, you are correct. While we'd love to build real processors to test ideas, obviously that's impossible. What you do is you spend a little while and write a program which simulates the performance of the processor you're modeling. Then, you run it on some program (we generally use the SPEC benchmarks (spec.org if you're unfamiliar with them) and get some performance number (say, average of 1.3 instructions executed per simulated clock cycle). Then, you make some change to your simulated processor and execute it again, and see what new performance you get... you do that about a billion times and boom... a paper ;)... seriously, I have to wonder if computer architects are the only real market for faster processors, since we can ALWAYS use more cycles (in the lab at this school we have 4 667 mhz 21264, 4 500 mhz 21264 and 14 500mhz 21164 and we'd still love to have more machines ;))...
Obviously because we're not executing on real hardware, the numbers we get aren't as accurate as real silicon, so you have to get really good performance gains to convince people of your ideas... usually 10-15% is considered the target to make your work publishable. The paper I did on Itanium got much higher speedups (76%) because the benchmarks represented sort of pathological cases for the architecture. Thus, the benefit of the work I did achieved a huge gain... Of course, if you have the time you can make a simulator that is highly accurate compared to real hardware, but the time investment is huge and it doesn't make your work that much more publishable... If you're interested, you can get a very commonly used simulator from simplescalar.org Most papers published use that simulator as a base.
It generally takes 5-8 years or more for architecture research at the academic level to work its way into commercial processors... if you work for intel maybe it takes only 3-5 years...
As far as your itanium question, I'm not sure if I really can answer that... I don't know much about the low level workings of itanium... what I was working on was as I described above--a high level software emulation of itanium. I was interning there actually, and they did have a highly accurate simulator, but my mentor indicated that it would take me a long time to learn the existing code base, so instead we interfaced their existing infrastructure to an processor simulator similar to simplescalar (but one I was more familiar with). So, things were at a high level... the lowest level I got to on it was like, how many load/store units does it have, how big of caches are we going to model etc.
What I mean to say is, when you compile code for the ppro or a later processor, the code that is being generated looks like a lot less like cisc code and a lot more like risc code...
Can you back up this claim that compiling for CISC is significantly easier?
First of all... p3 and p4 are basically risc processors anyway... while they support all the old instructions, most compilers only use the most risc like ones because those are the most efficiently implemented on the processor (it's slower to use the hardware string compares than to just do it manually etc).
Even benchmarks which are heavily floating point intensive (ie, matrix multiplication) are 70% integer instructions...
This one is being presented in about a month in sweden
This paper explores Speculative Precomputation, a technique that uses idle thread contexts in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. This technique is evaluated by simulating the performance of a research processor based on the Itanium(TM) ISA supporting Simultaneous Multithreading. Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30\% are achieved when assuming ideal hardware. However, this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.
this one was presented about 18 months ago...
This paper describes the Miss Classification Table, a simple mechanism that enables the processor or memory controller to identify each cache miss as either a conflict miss or a capacity (non-conflict) miss. The miss classification table works by storing part of the tag of the most recently evicted line of a cache set. If the next miss to that cache set has a matching tag, it is identified as a conflict miss. This technique correctly identifies 87\% of misses in the worst case. Several applications of this information are demonstrated, including improvements to victim caching, next-line prefetching, cache exclusion, and a pseudo-associative cache. This paper also presents the Adaptive Miss Buffer (AMB), which combines several of these techniques, targeting each miss with the most appropriate optimization, all within a single small miss buffer. The AMB's combination of techniques achieves 16% better performance than any single technique alone.
regarding the insulting me etc crap... I mean, it's what I deserve right? I've been disrupting slashdot for my own selfish reasons, however lame they may be. I've actually started feeling guilty about not contributing anything to it and just wasting everyone's time... I stopped coming back as often because of this... so, anyway, I think it's amusing that you actually took the time to look at the past messages I posted etc :)...
woops... this is really disgorged_fetus... accidentally submitted it under my other login :/...
haha... well, I make lots of pointless posts yes... slashdot is a total joke and when I'm bored... whatever... I realize it's pretty stupid... I mean, sometimes I'm bored, and this way, I don't have to think before I act... just post useless shit... Oh, and this account is automatically modded down to -1... that's why I post useless shit... because you only see it if you want to... if you set your threshhold at 0 or higher you would be spared of it...
as far as my publications go, I'll be more than happy to point you at them... the question is, why would you believe they were written by me in the first place? you'll probably just accuse me of making it up anyway... anyway, I'll be glad to send you them through email from an address that clearly corresponds to the primary author on them if that'll be proof enough, but I'd ask that you not spread them around (I know my behavior is childish, but I wouldn't want that to reflect on the other authors of the papers...)
think you can swing that?
Worst was when I TAed for a class recently. My university has changed the 'official' language from C to Java (BLAH). In a class full of seniors who were months away from graduation, I had to teach them how to do file IO in C. And these people expect to be hired in a few months? Give me a fucking break...
The result of this was that I would speak in english to all the people sitting nearby me because they were bad enough at spanish that it was easier to speak to them in english than in spanish. So, in that case, it didn't really benefit anyone...
In classes at my school (UC San Diego) the rule commonly mentioned in classes is the Gilligan's Island rule. What this states is that if you need help from another student it's ok to talk about the program with them, but you have to watch an episode of Gilligan's Island or some other equally brainless activity for half an hour before you touch a keyboard.
1) No one was arguing 'give this kid a chance, maybe he'll somehow be able to do the work of 20 trained professionals'
2) There was little threat of you causing harm to yourself or others in trying to write your own copy of SF2
Yes it's good to try things that are difficult, but some things just aren't meant to be...
I'm on something@home and I get pretty good upload (32k/s max). Since I moved in (4 months) I've uploaded 88,841,174,004 bytes from my ftp server on port 21... so you can do well sometimes...
Going back over the exachange covered on the webpage, I'm more inclined to agree with you now.