The x86 pain in the ASS is more than just a die area for translation circuitry! A) Legacy instructions, legacy exceptions legacy... Pain in the ass, self modifying code detection. B) Strong memory model. Reduces freedom in reordering stuff, or simply increases amount of time. C) Amount of programmer visible registers, and lack of triadic operations. D1) In P4 the trace cache holds quite little number of instructions, because they are MUCH bigger than RISC instructions, and there is more of them for equivalent code. D2) Athlon line has extra predecode bits in its Icache and 3 large decoders. That consume POWER! E) Amount of parallerism available trough the ISA, is limited. F) Cost of adding parallerism is a LOT bigger in X86 because of
Decoders or tracecache parallerism costs more. POWER, and latency/clockspeed.
All the myriadic exception models have to be compatible.
More memory renaming required and all pain in there.
FLAGS! Renaming, and all trickery making that work so that it won't hurt parellerism,
and accessed by most execution units! G) Clock speed is hurt because of the issue. Remember than IBM and SUN ran 1/3 of clock speed of alpha all the time, because of their design methology, until alpha lost their fab. The clock speed is more function of design methology, but ISA adds more complexity on some structures, complexity increase the distance travelled so that hurts clock speed, but intel has superiour fabbing and design methology for doing full custom designs. Now A, and D brings to a nice little point. LEAKAGE POWER which is growing component. Logic transistors leak 30 times the cache transistors. Besides even for inorder RISC:s CPU:s decode and fetch consume most of power so, that is where the X86 complexity hurts, most.
Now the scale of economics, is the reason why X86 is as fast as it is. When you do full custom circuit design there is no way a semiasic design methology will catch you in performance or performance/watt, if goals are same. If you wan't to compare RISC vs X86 go for similar design methology use VIA for X86 candidate, and G4+ for risc. Intel and AMD and Alpha are compareble, up until 0.35u EV6. Yes thats a 600mhz OO 4 inst/cycle risc design made in similar process as under 300mhz PII:s , and that trounced everything. Too bad it came late for Digital. After that there is no highperformance targetting RISC with full custom designmethology available. Power is highly limited by its design methology in terms of clockspeed and instruction latencies, and having different design methology would simply increase the fixed costs for IBM so much that the scale of economics is not there. And for embedded market they prefere ability to customize the processor for customers so design methology choise is obvious for them.
One small point, in power comsumption execution units are CHEAP, its fetch, reorder, and decode that costs power. Cache too is cheap in power comsumption based. So lots of cache and execution units is cheap in powercomsumption and the rest is where the power comsumption lies mostly. Exceptions, decode, fetch, and reorder. Now in ALL things in the list X86 ISA makes things more complex than equivalent RISC, and spends more transistors in there.
Blah what about HER NEEDS! Won't you consider about that you sovinist bastard!
Never underestimate the power of the Force!
on
Star Wars on DVD
·
· Score: 1
"Despite the force behind Star Wars, its price probably will prevent it from taking the year's top-selling spot." Never underestimate the power of the Force!
Right now that holds for multiple reasons.
A) both AMD and intel is going for dual core in a year or so. Desktop maybe later.
B) They are moving to 0.65u manufacturing by then. Thats 4 times transistor density for AMD and twice for intel. Which result more stuff on processor die. So its 2 processors and lots of cache and other stuff or 4 processors...
C) Probably a new architecture is introduced by then K9 for AMD. For intel It might be desktop Itanium. [Yes thats fast, unlike the common misconseption. Intel server line is currently one process generation behind the x86 line, probably because longer verification cycles for server CPU:s, and server systems, and extra reliability requirements. And die area is huge and so is power because its designed as high end server CPU not because of architecture. x86 is quite fast as software emulation on itanium, actually so much faster that itanium could get nice speed up from ditching hardware x86 compability that consumes power and slows down the clock speed slightly.] But intel should get something in 2 years either itanium, or Pentium M based multicore desktops. Or something.
Half true. Amount of memory is important, relative memory speed, negligle after certain point...
Well there is little problem. There is two kind of memory performance one is latency and one is bandwith. Lower timings don't give much in either way. A64 is faster because it gives 50% reduction in latency not some singledigit% fast modules gives over slower. The memory performance is improving PROCESSING performance, and processor matters more if you have REASONABLE memory speed=dual channel Remember Ahmdalls law, Time= Timenotaffected+Timeaffected/percentageofimproveme nt.
Now if you hit cache most of the time. On the other hand some applications are limited by memory bandwith so that only way to improve them is adding improving memory, while processor means nothing, on the other hand MOST applications benefit from processing power.But remember to consider about % of improvement. 300Mhz in processor at 3Ghz is 10% improvement and means about nothing in responsiveness.
Adding other processor, while getting slower model probably means that while a badly coded application locks your one processor the other processor can continue working for your tasks.
Wan't fastest memory system. Go for dual opteron. ~200$ a peace, get ~200$ MB that has 2 channels per processor available [Some dual opterons boards use only memory controller on ONE of the processors see the layout to determine if they use both processors memory controllers]. You get more benefit from dual processing and get more than twice the memory bandwith than the getting 2 channel P4 system with fastest available memory. Id say amount of memory and dual processing means more than the few % of improvement the SPEED of memory gives.
"I used illegal fireworks here (Minnesota) and all I got was the few I hadn't shot off confiscated by the local cops. Good job, poindexter." It depends where you are and all kinds things.
Then there was a friend of mine who got a "Ultimate Mega Final Jeopardy Triple Stumper," where he correctly guessed the response before the clue was even given, knowing only the category, and all three contestants got it wrong. As I recall, his head exploded. That was quite a day.
Don't use illegal fireworks, its a felony! [learnin trivia of stuff that matters.]
Well lets make SIMPLIFIED calculations... Assume a cubic with 100meter edge. That has volume of million m^3 the air density at target altitude is 1/5kg-0.1 per m^3 [It wasn't clearest graph where I looked the value] Then that sized of ballon can handle 100-200Tons now. Then there is need to stabilize the location of said balloon, in order to test teather. And for that it needs some sort of engine to stay still and the jet engine is not correct choise [ARGH I should of slept more.] But still I think the engine and balloon and fuel will weight a LOT less than the 150Tons assumed lift at the height. Perhaps leaving couple of tons for the weight of teather and 250kg for weight of the climber.
Besides balloon made of nanotubes would weight a LOT less than that and the engine and propellers don't weight too much either, nor does the fuel to keep it steady. The height where air is too thin for ANY kind of balloon is over 20 and probably over 30km . And with some nanomaterials there maybe possibility to build even HIGHER climbing balloons.
English is not my native language and there is ALWAYS a counter weight at end of teather in space in full scale. Uhh balloon creating the upperward force for keeping the teather up. I wasn't joking, only my expression wans't best possible.
There is one point... There is difference between PHYSICAL slots and available lanes. 4x16 slots with 4x4 links could be realized at pretty quickly. That's between AGPx2 and AGPx4 for each card Assuming my calculations as 8*4*66=2.5GB for AGPx4 is correct. The MB would be SMALLER than with current PCI slots. For gaining quad CPU well put CMP dual core with two processor packages, and end up with with about standard sized MB. Hmmm. This makes the coming of dual core processors even MORE exciting. Put a single package dual core processor on a system and gain SMT benefits with minimal costs increase in such system... 2-4CPU's for 8-14 desktops is just great for business users, assume everything except GFX integrated so no need for other slots. Minimal system administration, perhaps a backup system available on site if any such system goes down, think only 4 systems for administrate for over 50 people to use. Intel didn't realize the power they released when they brought PCI-express.
There is one prediction, there is expected to have more than few PCIe-16 slots available EVEN if they cannot put enough lanes to fill it. And last but not least, expect some low end cards come in pcie-4 formfactor. That should be in physical connector available.
Yes... Remember that with new 20" LCD:s from apple YOU SAVE 40$ in electicity in normal business use in a year compared to comparable CRT. The Display costs only $1,299.00.;)
Uhh I personally think its good to save electricity not because $$$ because thats not the biggest costs I know. But because its better for enviroment to reduce the amount of fossil fuel we burn.
The biggest benefit of multiuser/multi head in home enviroment is reduced management afterwards, initial costs, and Basicly I'd rather have ONE water cooled fanless PC running than two with fans (Fanless water cooling costs and take area outside the box). Anyway I'm still single so its not YET an issue.
Baloon? http://vpizza.org/~jmeehan/balloon/
If amateur home made ballon gets 79 809 (feet / kilometer) = 24.3257832 km then multimillion funded carbon nanotube project could make or buy a ballon that could work as counter weight. The problems from winds maybe dealt with small jets attached to it. And problem with fuel... Hmm use another balloon for refuelling. And make balloon REALLY big, as the weight of balloon and the surface area for wind grows R while lift grows R so you could get better fuel ratio for bigger balloons.
Well I agree with the car tax that should be reduced. But the result of public transportation being cheaper in Capital area, is reduced pollution which is the goal of having those taxes in first place. Partially the size of car is trade of between fuel efficiency and amount you can transport with it.
We don't need to have a van or small truck for going work. Its not too common to have situation where you really need to move lots of stuff. So you only need to know some one with such a car, or ren't it when you move things. But get reasonably sized car for daily use.
Besides there is half the price of western car a modern LADA (uhh a long version of it [I know ther exist English word that describes it but I don't remember it])can carry as much and has reasonable fuel economy.
I had coded a graphical calculator, and it had over 5000 LOC, all variables where 3 letter except some local where shorter. No comments nor any documentation. After 6 month brake I spend week trying to fix that. I had windows, my HD mysticly broke and wiped out everything, including games and ALL the things I've programmed that far.[I didn't have CD-drive at that machine, nor made backups]. I was happy because the need for updating the calculator was gone, and I didn't need to see those sources anymore.
Needless to say I've learned to put something in readability and documentation after that.
In Finland we have SUBSTANTIAL Gas tax. That means MPG has real result in my pocket. BAD MPG is from 70's soviet union made vehicles which is about 30 MPG and modern cars get around 60-70MPG. We pay 1.2 Eur/litre =~ 5.67$/gallon. Most of it taxes. If US would get anyway near similar TAX on gasoline [Passed with reduction of other taxes] Your thinkin 30MPG is good fuel economy would change. Also that would bring small shops closer to places where people live in order to reduce driving.
>I don't see the sonic boom is that much of a problem... But, aerodynamically, I don't know why >2.5khm/hr muzzle velocity is sufficient. >Here is my reasoning: >(from the PDF document) >conventional gun system: muzzle velocity 1.5 km/hr, range 50 miles >first generation of railgun: muzzle velcocity 2.5 km/hr, range 250 miles, Mach 5.0 (1.6 km/hr) at >impact.
I have a question. Me as a Finnish person who measures his walking speed in metric system is 5-6 km/hr so I'm walking over twice the muszle velocity you estimated, so How bad impact I would create a frigate If I walked straight at it?
Well smart guys are good even for creatig terror. Only reason that US population is not halved is that really smart guys don't really ACT on those things. Heck, wiping out over half the population of US would take 100 sacrificial lambs, under 50M$ and ~20 smartguys that are NOT sacrificed. Luckily smart people are not handling those operations. Its brains that matters, for any big operation. And really smart guys,dislike the activists operations since activists make smartguys look dumb.
Now that we know top spammers / email marketing firms....
How long would it take for geek population to find the PHYSICAL sites where they are located. And no we wouldn't be interested proofing that they send THE spam we recieved, only fact that they send spam lots of it. Now get AK47 in large quantities, and some explosives and timing based detonators.
If 50 or more email marketing sites are attacked at same time all-around the world. With those offices destroyed, and top spammers sleeping with the fishes, how many would think that the email marketing is easy and safe money making business. The punishment maybe on a hard side compared to the crime, but it would simply eliminate Spammers.
MMX was designed a minimal instruction extension to allow certain decoders work in realtime.
I cannot remember which, but it was graphics. Now the marketers got a hint of the MMX and marketed it to give you moon from the sky. And while marketing worked for a while, the MMX was later dismissed completely since although it did EXACLY what it was designed to do, it didn't give you the things the marketers said it would. Also it become unnecessary additional complexity burden to carry with now that we have enough integer power to deal with the said decoding routines WITHOUT any MMX code. It was designed for special purpose tasks that worked, and marketed as general purpose all for all solution.
Heck PPRO architects gave us wonders by supporting ancient architecture and made it surpass best RISC of the time in integer performance for a short period of time. AMD gives us best bang for buck because its underdog and intel has such marketing muscle that gives it leverage on pricing. If we want something big from intel its itanium2 and further stuff. Pentium4 was slight step in wrong direction, but intel has huge number of engineers working on further products so its only temporary...
Slashdot Mirror
The x86 pain in the ASS is more than just a die area for translation circuitry!
A) Legacy instructions, legacy exceptions legacy... Pain in the ass, self modifying code detection.
B) Strong memory model. Reduces freedom in reordering stuff, or simply increases amount of time.
C) Amount of programmer visible registers, and lack of triadic operations.
D1)
In P4 the trace cache holds quite little number of instructions, because they are MUCH bigger than RISC instructions, and there is more of them for equivalent code.
D2)
Athlon line has extra predecode bits in its Icache and 3 large decoders. That consume POWER!
E) Amount of parallerism available trough the ISA, is limited.
F) Cost of adding parallerism is a LOT bigger in X86 because of
Decoders or tracecache parallerism costs more. POWER, and latency/clockspeed.
All the myriadic exception models have to be compatible.
More memory renaming required and all pain in there.
FLAGS! Renaming, and all trickery making that work so that it won't hurt parellerism,
and accessed by most execution units!
G) Clock speed is hurt because of the issue. Remember than IBM and SUN ran 1/3 of clock speed of alpha all the time, because of their design methology, until alpha lost their fab. The clock speed is more function of design methology, but ISA adds more complexity on some structures, complexity increase the distance travelled so that hurts clock speed, but intel has superiour fabbing and design methology for doing full custom designs.
Now A, and D brings to a nice little point. LEAKAGE POWER which is growing component. Logic transistors leak 30 times the cache transistors. Besides even for inorder RISC:s CPU:s decode and fetch consume most of power so, that is where the X86 complexity hurts, most.
Now the scale of economics, is the reason why X86 is as fast as it is. When you do full custom circuit design there is no way a semiasic design methology will catch you in performance or performance/watt, if goals are same. If you wan't to compare RISC vs X86 go for similar design methology use VIA for X86 candidate, and G4+ for risc. Intel and AMD and Alpha are compareble, up until 0.35u EV6. Yes thats a 600mhz OO 4 inst/cycle risc design made in similar process as under 300mhz PII:s , and that trounced everything. Too bad it came late for Digital. After that there is no highperformance targetting RISC with full custom designmethology available. Power is highly limited by its design methology in terms of clockspeed and instruction latencies, and having different design methology would simply increase the fixed costs for IBM so much that the scale of economics is not there. And for embedded market they prefere ability to customize the processor for customers so design methology choise is obvious for them.
One small point, in power comsumption execution units are CHEAP, its fetch, reorder, and decode that costs power. Cache too is cheap in power comsumption based. So lots of cache and execution units is cheap in powercomsumption and the rest is where the power comsumption lies mostly. Exceptions, decode, fetch, and reorder. Now in ALL things in the list X86 ISA makes things more complex than equivalent RISC, and spends more transistors in there.
Blah what about HER NEEDS! Won't you consider about that you sovinist bastard!
"Despite the force behind Star Wars, its price probably will prevent it from taking the year's top-selling spot."
Never underestimate the power of the Force!
And old news from thursday!i d=04/08/05/ 1442252&tid=147&tid=218
http://linux.slashdot.org/article.pl?s
WHAT! Have they really.
AARRGGGHHH.
Just before I was about to file a patent!
Right now that holds for multiple reasons. A) both AMD and intel is going for dual core in a year or so. Desktop maybe later. B) They are moving to 0.65u manufacturing by then. Thats 4 times transistor density for AMD and twice for intel. Which result more stuff on processor die. So its 2 processors and lots of cache and other stuff or 4 processors... C) Probably a new architecture is introduced by then K9 for AMD. For intel It might be desktop Itanium. [Yes thats fast, unlike the common misconseption. Intel server line is currently one process generation behind the x86 line, probably because longer verification cycles for server CPU:s, and server systems, and extra reliability requirements. And die area is huge and so is power because its designed as high end server CPU not because of architecture. x86 is quite fast as software emulation on itanium, actually so much faster that itanium could get nice speed up from ditching hardware x86 compability that consumes power and slows down the clock speed slightly.] But intel should get something in 2 years either itanium, or Pentium M based multicore desktops. Or something.
Blah. OGLE would of been optimal symbol.
Half true. Amount of memory is important, relative memory speed, negligle after certain point... Well there is little problem. There is two kind of memory performance one is latency and one is bandwith. Lower timings don't give much in either way. A64 is faster because it gives 50% reduction in latency not some singledigit% fast modules gives over slower. The memory performance is improving PROCESSING performance, and processor matters more if you have REASONABLE memory speed=dual channel Remember Ahmdalls law, Time= Timenotaffected+Timeaffected/percentageofimproveme nt.
Now if you hit cache most of the time. On the other hand some applications are limited by memory bandwith so that only way to improve them is adding improving memory, while processor means nothing, on the other hand MOST applications benefit from processing power.But remember to consider about % of improvement. 300Mhz in processor at 3Ghz is 10% improvement and means about nothing in responsiveness.
Adding other processor, while getting slower model probably means that while a badly coded application locks your one processor the other processor can continue working for your tasks.
Wan't fastest memory system. Go for dual opteron. ~200$ a peace, get ~200$ MB that has 2 channels per processor available [Some dual opterons boards use only memory controller on ONE of the processors see the layout to determine if they use both processors memory controllers]. You get more benefit from dual processing and get more than twice the memory bandwith than the getting 2 channel P4 system with fastest available memory. Id say amount of memory and dual processing means more than the few % of improvement the SPEED of memory gives.
"I used illegal fireworks here (Minnesota) and all I got was the few I hadn't shot off confiscated by the local cops. Good job, poindexter."
It depends where you are and all kinds things.
Then there was a friend of mine who got a "Ultimate Mega Final Jeopardy Triple Stumper," where he correctly guessed the response before the clue was even given, knowing only the category, and all three contestants got it wrong. As I recall, his head exploded. That was quite a day. .]
Don't use illegal fireworks, its a felony! [learnin trivia of stuff that matters
Well lets make SIMPLIFIED calculations... Assume a cubic with 100meter edge. That has volume of million m^3 the air density at target altitude is 1/5kg-0.1 per m^3 [It wasn't clearest graph where I looked the value] Then that sized of ballon can handle 100-200Tons now. Then there is need to stabilize the location of said balloon, in order to test teather. And for that it needs some sort of engine to stay still and the jet engine is not correct choise [ARGH I should of slept more.] But still I think the engine and balloon and fuel will weight a LOT less than the 150Tons assumed lift at the height. Perhaps leaving couple of tons for the weight of teather and 250kg for weight of the climber. Besides balloon made of nanotubes would weight a LOT less than that and the engine and propellers don't weight too much either, nor does the fuel to keep it steady. The height where air is too thin for ANY kind of balloon is over 20 and probably over 30km . And with some nanomaterials there maybe possibility to build even HIGHER climbing balloons.
English is not my native language and there is ALWAYS a counter weight at end of teather in space in full scale. Uhh balloon creating the upperward force for keeping the teather up. I wasn't joking, only my expression wans't best possible.
There is one point... There is difference between PHYSICAL slots and available lanes. 4x16 slots with 4x4 links could be realized at pretty quickly. That's between AGPx2 and AGPx4 for each card Assuming my calculations as 8*4*66=2.5GB for AGPx4 is correct. The MB would be SMALLER than with current PCI slots. For gaining quad CPU well put CMP dual core with two processor packages, and end up with with about standard sized MB. Hmmm. This makes the coming of dual core processors even MORE exciting. Put a single package dual core processor on a system and gain SMT benefits with minimal costs increase in such system... 2-4CPU's for 8-14 desktops is just great for business users, assume everything except GFX integrated so no need for other slots. Minimal system administration, perhaps a backup system available on site if any such system goes down, think only 4 systems for administrate for over 50 people to use. Intel didn't realize the power they released when they brought PCI-express. There is one prediction, there is expected to have more than few PCIe-16 slots available EVEN if they cannot put enough lanes to fill it. And last but not least, expect some low end cards come in pcie-4 formfactor. That should be in physical connector available.
Uhh I personally think its good to save electricity not because $$$ because thats not the biggest costs I know. But because its better for enviroment to reduce the amount of fossil fuel we burn. The biggest benefit of multiuser/multi head in home enviroment is reduced management afterwards, initial costs, and Basicly I'd rather have ONE water cooled fanless PC running than two with fans (Fanless water cooling costs and take area outside the box). Anyway I'm still single so its not YET an issue.
Baloon? http://vpizza.org/~jmeehan/balloon/
If amateur home made ballon gets 79 809 (feet / kilometer) = 24.3257832 km then multimillion funded carbon nanotube project could make or buy a ballon that could work as counter weight. The problems from winds maybe dealt with small jets attached to it. And problem with fuel... Hmm use another balloon for refuelling. And make balloon REALLY big, as the weight of balloon and the surface area for wind grows R while lift grows R so you could get better fuel ratio for bigger balloons.
Well I agree with the car tax that should be reduced. But the result of public transportation being cheaper in Capital area, is reduced pollution which is the goal of having those taxes in first place. Partially the size of car is trade of between fuel efficiency and amount you can transport with it. We don't need to have a van or small truck for going work. Its not too common to have situation where you really need to move lots of stuff. So you only need to know some one with such a car, or ren't it when you move things. But get reasonably sized car for daily use. Besides there is half the price of western car a modern LADA (uhh a long version of it [I know ther exist English word that describes it but I don't remember it])can carry as much and has reasonable fuel economy.
I had coded a graphical calculator, and it had over 5000 LOC, all variables where 3 letter except some local where shorter. No comments nor any documentation. After 6 month brake I spend week trying to fix that. I had windows, my HD mysticly broke and wiped out everything, including games and ALL the things I've programmed that far.[I didn't have CD-drive at that machine, nor made backups]. I was happy because the need for updating the calculator was gone, and I didn't need to see those sources anymore. Needless to say I've learned to put something in readability and documentation after that.
In Finland we have SUBSTANTIAL Gas tax. That means MPG has real result in my pocket. /gallon. Most of it taxes.
BAD MPG is from 70's soviet union made vehicles which is about 30 MPG and modern cars get around 60-70MPG. We pay 1.2 Eur/litre =~ 5.67$
If US would get anyway near similar TAX on gasoline [Passed with reduction of other taxes] Your thinkin 30MPG is good fuel economy would change. Also that would bring small shops closer to places where people live in order to reduce driving.
>I don't see the sonic boom is that much of a problem... But, aerodynamically, I don't know why >2.5khm/hr muzzle velocity is sufficient.
>Here is my reasoning:
>(from the PDF document)
>conventional gun system: muzzle velocity 1.5 km/hr, range 50 miles
>first generation of railgun: muzzle velcocity 2.5 km/hr, range 250 miles, Mach 5.0 (1.6 km/hr) at >impact.
I have a question. Me as a Finnish person who measures his walking speed in metric system is 5-6 km/hr so I'm walking over twice the muszle velocity you estimated, so How bad impact I would create a frigate If I walked straight at it?
Well smart guys are good even for creatig terror. Only reason that US population is not halved is that really smart guys don't really ACT on those things. Heck, wiping out over half the population of US would take 100 sacrificial lambs, under 50M$ and ~20 smartguys that are NOT sacrificed. Luckily smart people are not handling those operations. Its brains that matters, for any big operation. And really smart guys ,dislike the activists operations since activists make smartguys look dumb.
Quote from article, "John Carmack, co-founder and chief technical engineer of id Software. He admits to being a long-time rocketry enthusiast".
Now that we know top spammers / email marketing firms....
How long would it take for geek population to find the PHYSICAL sites where they are located. And no we wouldn't be interested proofing that they send THE spam we recieved, only fact that they send spam lots of it. Now get AK47 in large quantities, and some explosives and timing based detonators. If 50 or more email marketing sites are attacked at same time all-around the world. With those offices destroyed, and top spammers sleeping with the fishes, how many would think that the email marketing is easy and safe money making business. The punishment maybe on a hard side compared to the crime, but it would simply eliminate Spammers.
So Male sex dolls that, blows during an intercouse fills on all 3 account.
I don't know but use your karma Whorenium.
MMX was designed a minimal instruction extension to allow certain decoders work in realtime. I cannot remember which, but it was graphics. Now the marketers got a hint of the MMX and marketed it to give you moon from the sky. And while marketing worked for a while, the MMX was later dismissed completely since although it did EXACLY what it was designed to do, it didn't give you the things the marketers said it would. Also it become unnecessary additional complexity burden to carry with now that we have enough integer power to deal with the said decoding routines WITHOUT any MMX code. It was designed for special purpose tasks that worked, and marketed as general purpose all for all solution. Heck PPRO architects gave us wonders by supporting ancient architecture and made it surpass best RISC of the time in integer performance for a short period of time. AMD gives us best bang for buck because its underdog and intel has such marketing muscle that gives it leverage on pricing. If we want something big from intel its itanium2 and further stuff. Pentium4 was slight step in wrong direction, but intel has huge number of engineers working on further products so its only temporary...