Some customers have specs requiring intel processors. Not just Intel compatible, but intel. And thats a problem. Ofcourse some bosses wan't intel, and some IT managers want intel and don't wan't to hear about alternatives. And thats a no other choise. Its artificial line. Only reason to go intel is if you need 16+ proc x86 system, or SMT , or want highest per processor FP power. [ITANIUM2.] Or wan't high performance embedded ARM compatible processor. And the there is a case why pentium M could be the choise, wan't high performance in low power package and with x86 compability.
installing any program is as easy as going [b]apt-get install programname[/b], and applying security patches is: [b]apt-get update && apt-get upgrade[/b].
Is that realy that difficult or 1337?
Let me try it: apt-get install civilization
nope doesn't work.
Ok other try: apt-get install flashplayer
doesn't work
Next try: apt-get install excell
doesn't work but perhaps thats windows only stuff
This should work: apt-get install spreadsheet
nope, huh. LINUX is only for nerd kids, I give up.
Disclaimer: I've been using debian since y2k, and hardest part of software installation is to figure WHAT software to get, I can do it but still it takes lots of efford, For end users well designed default installing and some way GIVING THEM PROPER INFORMATION with graphical installation, is a key to solve that problem.Not everything but something that they can interpret on how usefull certain software package is for their problems.
I was 16 when I first saw any starwars movie and that was mid 90's. And neither I knew who those people where. You can assume he's young computer freak or just troll. Either way there are plenty of situations where you most certainly don't know a Starwars, and still read slashdot sometimes....
Uhh the load/store reordering is not a great solution and triadic operations are also usefull. And implementation issues are bigger impact, than what ever code issue people find or what ever architectural feature that impacts reordering is. The X86 makes implementors choose, between.
Large instruction cache and wide execution, trace cache reduces the decoders while increases the code size, but wide execution without tracecache would be pain in the ass. And don't keep telling us lack of IPC, There is plenty of IPC available for out of order execution when you have plenty registers. And now I'm not saying 32 is best for today.... And don't say register renaming handles it, that problem it won't, it will alleviate its worst, the load/store reordering will alleviate the worst, now all this is handled by increasing control logic which already take over 90% of powerbudget, for inorder processor. Clean RISC architecture like alpha can get far more parallerism than an X86 can.
Why?
TWO dependencies to follow not 3! [flags], which helps with increasing OO execution, while flags renaming and all that crap, triadic operations are not 3rd dependency, two operands are after register rename 3 operands
More registers=allows keep more variables inside core, so that your memory ordering buffer with limited capacity for exeuction is free to handle the jobs not mangling temporary variables around.
X86:s complex memory rules, not ONLY the addressing modes, DO increase the costs for taking advantage of parallerising cache memory accesses. Keeping things clean make things easier, and doing great things possible.
Legacy modes[increase complexicty in Memory exeucion units and control logic] , partial register access=> more control logic, more trouble, in register handling, which leads less space for putting more parallerism in there.
With all these think that power comsumption is mostly from control logic EVEN with architecture that doesn't have the x86 hindrances.
Its no coincidence that alpha was 600Mhz with by FAR better clock for clock performance in 0.35 when it was last developed with full company focus on it. When x86 was at 300mhz. Yes it consumed as much power as 0.25 x86 when it reached at 600mhz but that happened long after that, and needed more advanced process and couple of revision to get there
[Alpha died because lack of marketing and making sales harder than necesary, and because bad management, and because its competitors where first in the market where compability rules.]
Well RISC allows low power comsumption by simplifyin decode. The simplicity, well the simplicity all depends on what you consider. Majority of chip power comsumption is in control-logic and decode, so having simpler that is the key advantage of RISC not a having simple execution units. Todays RISC, well spend transistors on certain paths, BUT still OoO execution is simpler with RISC, Branch predictors where in the EARLY RISC, and it can be complex but doesn't have to be. Remember they got the die area to spend and they had to use it or others would get better performance simply by actually using the die area. To put it simply the high performance chips expand to area they are economically best for their target market, putting more transistors etc... Simplicity, could give us 8 inst/cycle instead of 3. Those simplicity favors regularity things help us more than a little. On the other hand the most simple high performance risc is dead, because of bad management. Moore law gives us space, simplicity makes complex speed optimizations easier. [To put it so programmers understand, its easier to create optimizing compiler for C than C++, especially if you put artificial maximum memory limit for compiler binary.]
In fact, it's likely to just make things more confusing. There's a reason that mathematicians don't do geometric proofs so much anymore - symbolic manipulation is more clear, more general, and more compact. It's the same reason that hardware designers use things like VHDL now.
Not true...
HW designers use VHDL because their graphical tools are too low level, and highlevel graphical tools just generate VHDL, and its mostly a standard way of moving things around, and being compatible and having ability to reuse blocks. Also they could reuse other VHDL created blocks that they have spend hundreds of millions of dollars to create, and are known to work.
The low level tools that HW designers use it takes ages to build even a simplest block.
Consider for low level graphical tools...
They put transistors and powerlines and datalines. And they could copy blocks around but thats it for reuse, so you could end up spending weeks for a creating something that can be done in single line of VHDL. So thats the reason, they switched to VHDL and some have made a switch to graphical tools that generate vhdl that is higlevel stuff. Now the VHDL is the level how to interact between components, and test things and simulate things. And intead of spending 1M$ per test cycle to debug we use simulators instead. Its much easier to do logic simulator for VHDL than transistor level laidout stuff...
Phone(NOW)==Watch(NOW)
Hey I know that lots of younger people don't wear any watches anymore in Finland. Mobilephone shows time always when on. While its not as convenient to take one from you pocket that check you wrist. Some just don't wan't to carry one more thing in their wrist, and there fore they use the thing they carry anyway. After I run out of batteries in my current whatch I might do same thing. Only reason I keep whatch that is convenient in sauna and when I'm in hurry.
People may learn apt-get install to get applications but there is ONE BIG CATCH! They need to know that gtkpod is the application for that purpose. I have used linux from y2k and thats news to me. I could google and find out if I needed. But will average joe do it? NO. Heck there is probably some really good applications on tasks I wan't to do. But there is 10 crappy choises from which to choose. And I only wan't one that works. And know the name. Unless you get something along the way.
ap-get install "connecting mobilephone to PC" And that "" could be parsed as any task user wan'ts or something to identify anything, apt-get is not for average Joe.
How to make it a lot easier task. First put a list of commonly used apps for different task in a GUI installer with detailed descriptions what the applications is all about and top choises for different tasks. Now people could actually select what they need, and easy gui interface. Not needing guessing what application works for what. Now besidest that there should be something for "Windows power user" friendly thing like ability to search descriptions for key words. Like handset, or something. And common assumption for many tasks is that "if I cannot do it in gui its hard and there for impossible for me to do.".
You know, I did try that, but the girl still wasn't impressed with the size of my X. Am I doing something wrong?
I't all depends size of the girl. But one thing girls have common that they don't wan't to know your X. Past is past, and now is now.
This is a lists of criminals, wanted by slashdotters. should be considered extremely dangerous and should be ping to death on sight.
Imagine a beowolf of slashdotters pinging of these down.
http://www.spamhaus.org/rokso/index.lasso
Query replace ping shoot.
disclaimer: I do NOT advocate people for actually finishing 200 individuals responsible for 90% of spam, this was supposed to be joke.
If I understand you correctly, you are saying that a good RISC design would totally beat the x86 if equal resources were applied to the design of the chip. All I know is that, in the real world, x86 chips such as the Opteron perform extremely well, and even the latest PowerPC chips are not dramatically better. (The benchmarks I have seen show G5 and Opteron in the same ballpark on performance, each better in some areas.)
You got comparison totally wrong, if we take RISCvsCISC lets take something with closer relative in memory subsystem take fastest athlonXP and compare THAT to IBM solution.[They have same amount of cache and similar REALWORLD memory subsystems! (They have same amount of memory bandwith from memory to processor.). Opteron has ondie memory controller and larger cache which both make it killer, CPU not because its inherently better core.
If x86 is so horrible, why doesn't PowerPC totally crush the x86?
It depends on which incarnation of powerPC you look. We have power4, and PPC970. One beats in absolute performance while the other is mass produced at beats in relative to power comsumption, die area and transistor counts. And other point is that IBM uses high level design tools while intel, has more optimized design. Most anti risc comments put in programmer understandable context sound to me like, "this guys VBSCipt is slightly slower compared the other guys C implementation of same problem his algorithms must be bad.".
Or its closer that intel writes everything in C and optimizes every place that take atleast 0.1% of time with ASM while IBM writes in VB and optimizes few key points in C.
P.S. The Alpha sure sounds wonderful. Why doesn't someone make an Alpha-like RISC chip and crush the x86? If all you say is true, this should be a no-brainer.
It was as much as ISA it was design methology that mattered. And the Alpha team is currently making next generation itanium processors these days... And alpha IP is owned by HP and for their intended market compability and reliability matters more, so as much as I would like to see alpha survive it was killed by company politics and performance is not the king anymore, so there is no point. See SUN = slower than x86 because of few VERY bad design decision, made in 80's that made sence then. And Weakprocess tech, VS alpha who had quite extreme performance. People did buy sun because they had sun workstations before, and Sun had good software, support for its architecture, while alpha was strugling. Besides no one affords to put 2B$ fab for processor that is not guaranteed to sell in tens of millions/year.
But -- who cares? Modern CPU chips translate instructions into RISC-like micro-ops, and feed the micro-ops into multiple execution units.
Translation logic... Size of microops in reordering queus=more area for reordering queus more power comsumption, and smaller reordering windows.
The pain of a wacky instruction set is isolated in the translation part of the chip, and doesn't significantly hold back the chip in other ways.
Yeh right like power comsumption was not an issue these days? And strick memory ordering rules complicate memory ordering doesn't hurt?
The fact remains that intel and AMD get their chips so fast in INTEGER because a) They are made with more advanced process than any RISC. b) They trow lot of engineers to deep optimization tasks. c) Alphacide happened, =Managers killed a company and got personal profit out of it, and killed the fastest RISC processor family that was practicly only family as much hand optimized for speed as X86 is these days. [They had their 0.35u processors running faster than any 0.18u intel processor!] [2 process generations difference.]
RISC fans predicted years ago that CISC would die, because RISC is so much better.
They under estimated need for compability. Nothing more. nothing less.
But CISC chips contain RISC cores these days,
RISC was coined with many PROGRAMMER VISIBLE registers architecture optimized for COMPILER target, load/store architecture, and REDUCED complexity. You should read the acronym properly (Reduced Instruction) Set Computer.
And the old idea that RISC instructions would win because they are easier to decode didn't pan out.
Risc superiority cannot beat the amount of hand optimization that goes in intel/amd chips its because of volumes. Besides decoding was only a PART of advantage.
CISC instructions get decoded to RISC-like micro-ops, as I said, and it turns out not to be a huge deal.
It is, only thing is that you have to be Electrical Engineer who designs micro chips to fully realize WTF the big deal is. Besides being better compiler target by having large and regular register sets and staying without non register dependencies between instructions. [Flags, complicate reordering.]
Meanwhile, those CISC instructions are denser than RISC instructions, so you fit more of them into your limited cache space, which helps speed.
This is blatantly FALSE statement. P4 takes 72bits per instruction in Icache and AMD takes 11Bits per byte Icache inorder to have acceptable parallerism. So instruction cache sence RISC beats both hands down, on dencity.
In short, modern chips do all kinds of clever stuff, and the instruction set architecture is not really holding them back.
In short with a clean 64bit risc with EQUAL developement resources/hand optimizations compared to INTEL/AMD and equal volumes, we would get more parallerism than opteron and about same clock speed as P4 at similar costs. But unfortunately RISC high end is not high volume, and that dooms it from practically getting big chunks.
If you want me to feel sad, you need to back this up with some facts. Show me why you feel the Athlon64 would be faster if it were not backward-compatible with x86.
A) FPU, FPU, FPU !!!! The FPU has been crap. Always on X86. PPro was 1/2 as fast as equally clocked INORDER alpha with 1 integer and 1 FPU pipeline in floating point.... Remeber that intel required one process generation advantage and extreme packaging to get there. Today it has't really changed.
B) FLAGS!!!!! Screw the flags they complicate REORDERING LOGIC.
C) Simplicity gives a huge advantage, from implementation point of view. Less rules to adhere to. Less tricky logic trying to work over the braindamaged ISA and some really complex and large units can be simplified a lot. Like Reordering side, and control logic. And all the partial register dependencies yak
Yeah. Right it took me 20seconds to find a notification from the links in the article where Intel says that they are compatible with AMDs 64bit extensions, its in the FAQ. They just add there that they support some other techologies which AMD is not compatible, which may make the software non compatible. But from what they said in the faq they basicly say that the 64 bit extensions are compatible with AMD's.
Nope. x87 isa was developed by certain university/intel co-operation, which was supposed to become IEEE standard and FIRST ieee standard compatible chip was 8087 by intel Israel. You can read it all about in Hennessey/Patterson, HW/SW interface.
You brain damaged puppets!
Heh I will crab a bunch of chicks with a space ship, and put an asteroid on course to hit earth!
My name will survive, my legacy will be in the genes of all the remaining mankind.
Buahhhahahahhahaahahahaahhaaaaa...
Besides if I don't be the sole leader of mankind NO ONE ELSE WILL!!
This won't be ready until they get atleast one die shrink which means that CPU size is halved, quartered. [Besides your die area estimation is too large.]
I think the better analogy would be. 200->300mm wafers =2.25 times the area. 1.1-1.2 times the cost. Which should give people better realize of the reduction in CPU costs....
Besides actual SILICON cost is not largest part of cost equation. Marketing is. But if we take production costs then testing and packaging is more important. But larger wafers allow AMD to produce MORE processors, and have LARGER die area too.
And found out that it was THE best source for learning assembler for me. Almost every other asm tutorial I found on net was for windows. And everything else I found for linux wasn't beginner friendly, I tried to learn it from those sources but simply it was bits and pieces everywhere and nowhere anything comprehensive. So basicly if you use linux as your only OS, and wan't to learn assembler. Then get the book as pdf from savanna.nongnu.org , its practicly your ONLY reasonable source for doing it from material from net.
Slashdot Mirror
Some customers have specs requiring intel processors. Not just Intel compatible, but intel. And thats a problem. Ofcourse some bosses wan't intel, and some IT managers want intel and don't wan't to hear about alternatives. And thats a no other choise. Its artificial line. Only reason to go intel is if you need 16+ proc x86 system, or SMT , or want highest per processor FP power. [ITANIUM2.] Or wan't high performance embedded ARM compatible processor. And the there is a case why pentium M could be the choise, wan't high performance in low power package and with x86 compability.
Here is the rerun.
goat.cx
Let me try it: apt-get install civilization
nope doesn't work.
Ok other try: apt-get install flashplayer
doesn't work
Next try: apt-get install excell
doesn't work but perhaps thats windows only stuff
This should work: apt-get install spreadsheet
nope, huh. LINUX is only for nerd kids, I give up.
Disclaimer: I've been using debian since y2k, and hardest part of software installation is to figure WHAT software to get, I can do it but still it takes lots of efford, For end users well designed default installing and some way GIVING THEM PROPER INFORMATION with graphical installation, is a key to solve that problem.Not everything but something that they can interpret on how usefull certain software package is for their problems.
I was 16 when I first saw any starwars movie and that was mid 90's. And neither I knew who those people where. You can assume he's young computer freak or just troll. Either way there are plenty of situations where you most certainly don't know a Starwars, and still read slashdot sometimes....
Uhh the load/store reordering is not a great solution and triadic operations are also usefull. And implementation issues are bigger impact, than what ever code issue people find or what ever architectural feature that impacts reordering is. The X86 makes implementors choose, between. Large instruction cache and wide execution, trace cache reduces the decoders while increases the code size, but wide execution without tracecache would be pain in the ass. And don't keep telling us lack of IPC, There is plenty of IPC available for out of order execution when you have plenty registers. And now I'm not saying 32 is best for today.... And don't say register renaming handles it, that problem it won't, it will alleviate its worst, the load/store reordering will alleviate the worst, now all this is handled by increasing control logic which already take over 90% of powerbudget, for inorder processor. Clean RISC architecture like alpha can get far more parallerism than an X86 can.
Why?
TWO dependencies to follow not 3! [flags], which helps with increasing OO execution, while flags renaming and all that crap, triadic operations are not 3rd dependency, two operands are after register rename 3 operands
More registers=allows keep more variables inside core, so that your memory ordering buffer with limited capacity for exeuction is free to handle the jobs not mangling temporary variables around.
X86:s complex memory rules, not ONLY the addressing modes, DO increase the costs for taking advantage of parallerising cache memory accesses. Keeping things clean make things easier, and doing great things possible.
Legacy modes[increase complexicty in Memory exeucion units and control logic] , partial register access=> more control logic, more trouble, in register handling, which leads less space for putting more parallerism in there.
With all these think that power comsumption is mostly from control logic EVEN with architecture that doesn't have the x86 hindrances.
Its no coincidence that alpha was 600Mhz with by FAR better clock for clock performance in 0.35 when it was last developed with full company focus on it. When x86 was at 300mhz. Yes it consumed as much power as 0.25 x86 when it reached at 600mhz but that happened long after that, and needed more advanced process and couple of revision to get there
[Alpha died because lack of marketing and making sales harder than necesary, and because bad management, and because its competitors where first in the market where compability rules.]
Well RISC allows low power comsumption by simplifyin decode. The simplicity, well the simplicity all depends on what you consider. Majority of chip power comsumption is in control-logic and decode, so having simpler that is the key advantage of RISC not a having simple execution units. Todays RISC, well spend transistors on certain paths, BUT still OoO execution is simpler with RISC, Branch predictors where in the EARLY RISC, and it can be complex but doesn't have to be. Remember they got the die area to spend and they had to use it or others would get better performance simply by actually using the die area. To put it simply the high performance chips expand to area they are economically best for their target market, putting more transistors etc... Simplicity, could give us 8 inst/cycle instead of 3. Those simplicity favors regularity things help us more than a little. On the other hand the most simple high performance risc is dead, because of bad management. Moore law gives us space, simplicity makes complex speed optimizations easier. [To put it so programmers understand, its easier to create optimizing compiler for C than C++, especially if you put artificial maximum memory limit for compiler binary.]
a) They get banned.
b) More screening process on who to give licence.
c) Same thing happens few times more and goto a.
In fact, it's likely to just make things more confusing. There's a reason that mathematicians don't do geometric proofs so much anymore - symbolic manipulation is more clear, more general, and more compact. It's the same reason that hardware designers use things like VHDL now. Not true... HW designers use VHDL because their graphical tools are too low level, and highlevel graphical tools just generate VHDL, and its mostly a standard way of moving things around, and being compatible and having ability to reuse blocks. Also they could reuse other VHDL created blocks that they have spend hundreds of millions of dollars to create, and are known to work. The low level tools that HW designers use it takes ages to build even a simplest block. Consider for low level graphical tools... They put transistors and powerlines and datalines. And they could copy blocks around but thats it for reuse, so you could end up spending weeks for a creating something that can be done in single line of VHDL. So thats the reason, they switched to VHDL and some have made a switch to graphical tools that generate vhdl that is higlevel stuff. Now the VHDL is the level how to interact between components, and test things and simulate things. And intead of spending 1M$ per test cycle to debug we use simulators instead. Its much easier to do logic simulator for VHDL than transistor level laidout stuff...
Phone(NOW)==Watch(NOW) Hey I know that lots of younger people don't wear any watches anymore in Finland. Mobilephone shows time always when on. While its not as convenient to take one from you pocket that check you wrist. Some just don't wan't to carry one more thing in their wrist, and there fore they use the thing they carry anyway. After I run out of batteries in my current whatch I might do same thing. Only reason I keep whatch that is convenient in sauna and when I'm in hurry.
In soviet russia C says Miguel is dead.
In soviet russia children teach robots.
People may learn apt-get install to get applications but there is ONE BIG CATCH! They need to know that gtkpod is the application for that purpose. I have used linux from y2k and thats news to me. I could google and find out if I needed. But will average joe do it? NO. Heck there is probably some really good applications on tasks I wan't to do. But there is 10 crappy choises from which to choose. And I only wan't one that works. And know the name. Unless you get something along the way. ap-get install "connecting mobilephone to PC" And that "" could be parsed as any task user wan'ts or something to identify anything, apt-get is not for average Joe. How to make it a lot easier task. First put a list of commonly used apps for different task in a GUI installer with detailed descriptions what the applications is all about and top choises for different tasks. Now people could actually select what they need, and easy gui interface. Not needing guessing what application works for what. Now besidest that there should be something for "Windows power user" friendly thing like ability to search descriptions for key words. Like handset, or something. And common assumption for many tasks is that "if I cannot do it in gui its hard and there for impossible for me to do.".
You know, I did try that, but the girl still wasn't impressed with the size of my X. Am I doing something wrong? I't all depends size of the girl. But one thing girls have common that they don't wan't to know your X. Past is past, and now is now.
Imagine a beowolf of slashdotters pinging of these down.
http://www.spamhaus.org/rokso/index.lasso
Query replace ping shoot.
disclaimer: I do NOT advocate people for actually finishing 200 individuals responsible for 90% of spam, this was supposed to be joke.
You got comparison totally wrong, if we take RISCvsCISC lets take something with closer relative in memory subsystem take fastest athlonXP and compare THAT to IBM solution.[They have same amount of cache and similar REALWORLD memory subsystems! (They have same amount of memory bandwith from memory to processor.). Opteron has ondie memory controller and larger cache which both make it killer, CPU not because its inherently better core.
If x86 is so horrible, why doesn't PowerPC totally crush the x86?
It depends on which incarnation of powerPC you look. We have power4, and PPC970. One beats in absolute performance while the other is mass produced at beats in relative to power comsumption, die area and transistor counts. And other point is that IBM uses high level design tools while intel, has more optimized design. Most anti risc comments put in programmer understandable context sound to me like, "this guys VBSCipt is slightly slower compared the other guys C implementation of same problem his algorithms must be bad.". Or its closer that intel writes everything in C and optimizes every place that take atleast 0.1% of time with ASM while IBM writes in VB and optimizes few key points in C.
P.S. The Alpha sure sounds wonderful. Why doesn't someone make an Alpha-like RISC chip and crush the x86? If all you say is true, this should be a no-brainer.
It was as much as ISA it was design methology that mattered. And the Alpha team is currently making next generation itanium processors these days... And alpha IP is owned by HP and for their intended market compability and reliability matters more, so as much as I would like to see alpha survive it was killed by company politics and performance is not the king anymore, so there is no point. See SUN = slower than x86 because of few VERY bad design decision, made in 80's that made sence then. And Weakprocess tech, VS alpha who had quite extreme performance. People did buy sun because they had sun workstations before, and Sun had good software, support for its architecture, while alpha was strugling. Besides no one affords to put 2B$ fab for processor that is not guaranteed to sell in tens of millions/year.
Translation logic... Size of microops in reordering queus=more area for reordering queus more power comsumption, and smaller reordering windows.
The pain of a wacky instruction set is isolated in the translation part of the chip, and doesn't significantly hold back the chip in other ways.
Yeh right like power comsumption was not an issue these days? And strick memory ordering rules complicate memory ordering doesn't hurt? The fact remains that intel and AMD get their chips so fast in INTEGER because a) They are made with more advanced process than any RISC. b) They trow lot of engineers to deep optimization tasks. c) Alphacide happened, =Managers killed a company and got personal profit out of it, and killed the fastest RISC processor family that was practicly only family as much hand optimized for speed as X86 is these days. [They had their 0.35u processors running faster than any 0.18u intel processor!] [2 process generations difference.]
RISC fans predicted years ago that CISC would die, because RISC is so much better.
They under estimated need for compability. Nothing more. nothing less.
But CISC chips contain RISC cores these days,
RISC was coined with many PROGRAMMER VISIBLE registers architecture optimized for COMPILER target, load/store architecture, and REDUCED complexity. You should read the acronym properly (Reduced Instruction) Set Computer.
And the old idea that RISC instructions would win because they are easier to decode didn't pan out.
Risc superiority cannot beat the amount of hand optimization that goes in intel/amd chips its because of volumes. Besides decoding was only a PART of advantage.
CISC instructions get decoded to RISC-like micro-ops, as I said, and it turns out not to be a huge deal.
It is, only thing is that you have to be Electrical Engineer who designs micro chips to fully realize WTF the big deal is. Besides being better compiler target by having large and regular register sets and staying without non register dependencies between instructions. [Flags, complicate reordering.]
Meanwhile, those CISC instructions are denser than RISC instructions, so you fit more of them into your limited cache space, which helps speed.
This is blatantly FALSE statement. P4 takes 72bits per instruction in Icache and AMD takes 11Bits per byte Icache inorder to have acceptable parallerism. So instruction cache sence RISC beats both hands down, on dencity.
In short, modern chips do all kinds of clever stuff, and the instruction set architecture is not really holding them back.
In short with a clean 64bit risc with EQUAL developement resources /hand optimizations compared to INTEL/AMD and equal volumes, we would get more parallerism than opteron and about same clock speed as P4 at similar costs. But unfortunately RISC high end is not high volume, and that dooms it from practically getting big chunks.
If you want me to feel sad, you need to back this up with some facts. Show me why you feel the Athlon64 would be faster if it were not backward-compatible with x86.
A) FPU, FPU, FPU !!!! The FPU has been crap. Always on X86. PPro was 1/2 as fast as equally clocked INORDER alpha with 1 integer and 1 FPU pipeline in floating point.... Remeber that intel required one process generation advantage and extreme packaging to get there. Today it has't really changed.
B) FLAGS!!!!! Screw the flags they complicate REORDERING LOGIC.
C) Simplicity gives a huge advantage, from implementation point of view. Less rules to adhere to. Less tricky logic trying to work over the braindamaged ISA and some really complex and large units can be simplified a lot. Like Reordering side, and control logic. And all the partial register dependencies yak
For me as EE st
Yeah. Right it took me 20seconds to find a notification from the links in the article where Intel says that they are compatible with AMDs 64bit extensions, its in the FAQ. They just add there that they support some other techologies which AMD is not compatible, which may make the software non compatible. But from what they said in the faq they basicly say that the 64 bit extensions are compatible with AMD's.
Nope.
x87 isa was developed by certain university/intel co-operation, which was supposed to become IEEE standard and FIRST ieee standard compatible chip was 8087 by intel Israel. You can read it all about in Hennessey/Patterson, HW/SW interface.
Buahhhahahahhahaahahahaahhaaaaa...
Besides if I don't be the sole leader of mankind NO ONE ELSE WILL!!
In soviet russia Java creates Liv shits.
No not really just one anomaly.
This won't be ready until they get atleast one die shrink which means that CPU size is halved, quartered. [Besides your die area estimation is too large.] I think the better analogy would be. 200->300mm wafers =2.25 times the area. 1.1-1.2 times the cost. Which should give people better realize of the reduction in CPU costs.... Besides actual SILICON cost is not largest part of cost equation. Marketing is. But if we take production costs then testing and packaging is more important. But larger wafers allow AMD to produce MORE processors, and have LARGER die area too.
And found out that it was THE best source for learning assembler for me. Almost every other asm tutorial I found on net was for windows. And everything else I found for linux wasn't beginner friendly, I tried to learn it from those sources but simply it was bits and pieces everywhere and nowhere anything comprehensive. So basicly if you use linux as your only OS, and wan't to learn assembler. Then get the book as pdf from savanna.nongnu.org , its practicly your ONLY reasonable source for doing it from material from net.