Mass layoffs are bad, not by virtue of having chance of loosing the good staff but by virtue of loosing SIGNIFICANTLY MORE of the good staff than incompetent as in % vice of their existence in company.
How much they save? 700M$ a year estimated. How much it costs for the action to happen? Do they loose the good ones instead of bad ones? There has been more or less common to loose the people you don't want to get rid off because there are layoffs. Next question is that DO they loose some of their business because of layoffs, by loosing more talented persons willing to jump ship? Are competitors getting insights by hiring people IBM just lost?
They are risking 9B$ profits by cutting 0.7B$ thats the effect. They cut costs but same time they cut their sales. Now there is risk of loosing more in sales than getting by cutting employees.
Have you ever known Athlon 64 that was sold and the advertised clockspeed was 1Ghz? My chip is 2Ghz chip which runs at 1ghz when I surf the net. But when I look at AVI it goes to its nominal speed of 2Ghz.
Well when you go for 0.9u or deeper technology the lifetime begins to matter... You got 50% clock speed increase at time when the memory interface wasn't such a bottleneck as it is today. The older processes tolerate overclocking better. What I'm saying that what you get today isn't worth the risks. When I used 366 celeron I would of overclocked at the END OF ITS USABLE LIFETIME. Not before, before that its unnecessary risk which I took and once changed my GFX card and HD because of experimentation, got replacement by guarantee though. At near the end I wouldn't care anymore as long as my data was backed up. Still remember the percentages. Similar performance increate that we get today it would of been overclock to 350mhz from your 300mhz. Also there is BIG difference of overclocking a something near the bottom grade to match clock speed of higher grade chips, than going beyond designed clockspeed, and going from middle grade to way beyond the designed limits, since the odds are that you are getting actual middle grade chip instead of top grade chip. But getting from bottom grade to midgrade is more probably non harmfull, since odds are that you might have a midgrade chip just marked lower, but NOT GUARANTEED THAT.
WOOHOO 20% higher clockspeed ! It gives 10% more realworld performance. And 10000% higher failure/error rate! Well having 100x higher error rate might go undetected most of time since errors in cpu are not that common without overclocking. Anyway. I'm thinking that what the overclocking gives is minimal increase not worth the potential problems. Not everyone get problems, and not everyone who got problems realize them. How you tell if the X server crashed by change of a bit at some place or by software failure if the error happens rarely enough? Or some other bit crashing. It simply goes that they burn em and test them to fit at certain point. Few people get lucky because they need to mark some chips at lower speed than they are truly capable and they keep certain margins on the chip timings to ensure it works. But getting rid of those margins just gives a potential like. If certain datapath gets used commonly enough, it gets hot, and it slows it down. The different bit patterns may show what kind of changes makes it hottest. Now those problems can be at ANY circuit location. It can be parts of alu, FPU, instruction decoder, cache. ANYTHING that just cannot keep with certain changing bit patterns when it becomes hot. And don't say that your cooling helps this a lot. Well the problem is INDIVIDUAL TRANSISTORS temperature not average chip temperature. And those transistors are becoming so small for dissipation.Plus it might be that the cycle time is not enough even at normal temperatures to keep up with worstcase changing bit patterns. Billions of different things CAN go wrong, with overclocked chip, and we don't know what it takes to burn certain paths. Then there is electromigration which worsens with voltage increases and so on. Basicly you are trading the lifetime and reliability of results for getting 10% more results. I've though thats not worth it for me, I'm more happy with my A64 chip, staying at 1Ghz when I don't need its performance and powering up to 2Ghz when load goes up. And having PC thats more quiet than other sound sources around here, like flow of water trough the pipes for heater, is more important me than the bragging rights of 10% higher performance;)
I'm using A64 with integrated everything, just plugged processor & ram & drives and put inside case. Cheap indeed. But there was a performance price for doing so. Integrated GFX sux in X even outside 3D games, id rather utilize the memory bus for something else. And accelerate it faster. Another that I can feel the difference is integrated sound. That correct, the onboard audio becomes choppy when system does something else. I might be inclined to believe that the problem is with COMBINATION of integrated GFX and sound trying to do their stuff at the same time. On K7 I had similar problems when I did have similar combination but it went away with installing a SBLIVE value from year 99. (which went with the K7 machine to buy a new A64) With integrated everything there is problem if those integrated chips drivers assume they can USE the main cpu whenever they want and then there are collisions there. Anyway those heavily integrated MB:s are really cheap so there is no harm done if getting one. Just remember that you need either discreet soundcard OR GFX card anyway.
The article seems to think that they saw a empty slot in ecology and filled it...
"Perhaps certain dinosaurs were pushed along the evolutionary route to vegetarianism because they lived in an area where there was no other plant-eating competitor, he suggests."
I think that if this where the case there was not just evolutionary pull but a push also. If they lived in area without plant eating competitor it makes me wonder what does a carnivore eat...
ANY x86 is a crap when talking about floating point. Especially when talking about that era. It was about the time when fastest x86 got 1/4 floating point performance of fastest risc. But on integer side the difference was smaller. So both floating point and integer performance scale have many different points where chips reside. From what I recall Cyrix 6x86 price was equal to a pentium with equal floating point performance while delivering much better integer performance by having superiour architecture. But the thing that gave them bad reputation was that people without realizing overclocked their chips 25% by setting the MB run at frequency of the rating instead of frequency it was supposed to run, and then wondering what gave them strange errors, and being without some extensions intel added with their latests chip just like nowadays AMD was without SS3 for a while except that at the day some people used those extensions and users that used ANYTHING BUT INTEL PENTIUM got hurt at the time.
This thing is really bad and crappy. You know its WINDOWS! There is nothing as bad as windows, although eye candy makes you see the blue screen WITH TRANSPARENCY! You know its BLASHPHEMY to put a link for a microsoft promoting article in slashdot.
Well. Cyrix 5x86 and 6x86 chips where good. It had two problems. First they couldn't predict at design phase the features intel was going to add and they lacked some PENTIUM compability while they where compatible with older x86 chips. 2ndly Their floating point performance was lackluster. Although their integer performance was great. Quake was one of rare cases where it bite really. Since normally even with floating point applications the integer performance is the key, and floating point performance is only secondary as those are rare instructions in the instructions mix anyway. Too bad for cyrix quake became THE benchmark to evaluate the performance.
I must tell that after I've learned something about the C compilation today. I doubt that C compiler can optimize enough, you have to. Either write in assembler or know what the compiler will output in different situations and code accordingly. There is one order of magnitude performance difference between optimized assembler and c-code that doesn't take account on what is assembler output of the code with same basic algorithm, depending on situations as C code can be efficient too. And no, the compiler cannot help as it lacks the information that could varrant those optimizations.
No I'll keep learning. I just dissassembled and tested this to work on 3 different platforms with multiple optization levels just to make sure that compiler does always stop before testing condition2. on if(condition1||condition2)
Anyway as long as there is employed persons who do.
if(condition1) goto label2 DOTHINGS; label2:
I think I'm not first one to go.
If you ask what I DO then I'll have to ask have your mobile phones had any crashes?
Okay here is something. If you have TWO conditions to one specific code sequence where 2nd test *CAN* cause pagefaults if first test do not pass. The said code sequence is such that creating a separate function for it is out of question and replicating the sequence inside elseif would be just another place to fix problems. So I go for short goto sequences. Like contion1 is something like if pointer=null or arrayindex=-1 or something similar. Yes the arrayIndex=-1 while accessing array CAN cause pagefaults. Getting array mallocated to a new page so that the arraystarts at pageboundary and later when previous page gets freed using arrayindex -1 in tests gets pagefault. And depending on malloc implementation for large mallocations they hit ALWAYS pageboundary.
IF(condition1) goto label1; IF(condition2) {
label1:
DOTHINGS; } I doubt people have such problems that such form becomes mysticly unreadable because use of goto.
2ndly I use GOTO as a replacement for return statement in functions where I need properly release the locks and do free() and other issues that are complex enough to varant the GOTO and for some reason would be stupid to put in its own function . But I use descriptive label, FUNCTION_END: GOTO FUNCTION_END; is a line that you could read quite well.
Of course there is obvious nongoto way for first issue.
if(condition1){
DOTHINGS; } else if (condition2) {
DOTHINGS; }
Difference here is that there are TWO locations where you DOTHINGS. If we make a BUG in DOTHINGS there is risk that the guy that fixes it fixes it in only ONE location while leaving the other untouched, and goes happily since his testing shows that the bug got fixed. Or we add a feature and introduce some difference between those two paths and thats a BUG. And what about 3 tests wich each if succeed lead to DOTHINGS but if fails the later test(s) COULD cause a pagefault.
But for the 2nd thing I don't know what else to do in C. If I copy the code in the end to all locations where I should return I risk creating really bad syncronization bugs that are VERY hard to track down. I only need to make mistake ONCE in many locations to create deep problems that seem to pop up in completely unrelated location of code. Or trying to do 100+ lines of code in DEEP nesting inside functions might be solution but when I look at the code it becomes REALLY unreadable by trying to track in which depth each thing should be instead being sequential.
Yes I'd prefer not doing same code sequences in multiple places since fixing a bug requires changing em all. I've just learned to DOCUMENT the use of goto and reasons for it so that others don't try to "fix" it. TWO METHODS of using goto separated by labelname, ONLY forward gotos. For first condition no unrelated code between goto and label,and for 2nd the targets are always at the end of function and in numbered sequence if need more than one different location in sequence of freeing specific resources used inside function.
The 64bit is for anyone with more than 2Gb of RAM + x86-64 gives you more registers besides being 64bit so it speeds up the recompiled code.
Dual core means simply you have TWO processors running. Rember old reviews on SMP dual celeron A and other such reviews. It gives little for games, lots for certain multithreaded applications. As you have two processors running and doing things. And multitasking applications, like being able to run interactive application (doom 3), while system is doing some multihour compilation on background. Anyway, it mainly keeps system more responsive when you have some thread or application takes CPU. Also with lesser degree helps in some other similar situation, where CPU is tied up with something EXACLY same moment you would wan't it to deal with UI stuff.
Is in its configurability. What about standard size planet filled with great AI and slow research, no huts giving random military units. I just loved it. 2 settlers you start with, find a place to start then, its war for expansion immediately. Basicly freeciv lets me hack with options that can change the gameplay of old game a LOT, and make it even more interesting. You can alter the population growth rate so that you get different variations on what will happen.
I can change the game options to play WAY different way compared to original civ. And there are lots of minor differences that make it different from CIV & CIV2 atleast in way of the strategies goes.
Is not the single thread performance or how fast can you finish task X. Its responsiveness of the system. I'm using A64 3000 and I get annoying stalls on system level. The CPU spends time with the backside thread, while I would love it working on UI, there is annoying stall. Multiple CPU:s according to reviews remove those issues. And don't say having 20% higher processor clock speed is going to help, its by simple fact that CPU was just doing something else at a time I would of loved it to handle UI events. Having 2 cores means, that responsiveness of a system is greatly improved, atleast until people write most of their applications to tie up more than one core;)
Celerons where mostly different chips. Why? Firstly L2 cache is redundancy protected. It means that instead of 256KB of cache there is 260KB or something similar amount of cache there are defective lines are replaced with a one that works. Another point is that L2 cache wasn't half the die area at the time not even close. So the defects because of the L2 is quite minimal, as many can be masked away. Another point is that MFG with less cache makes die area smaller so it would be cheaper for MASS producing it. Initially having same die size is effect of using SINGLE mask on both, and ADAPTING INVENTORY DEPENDING ON DEMAND. And avoid of spending ~Million dollars for having some savings in spend die area. [Having multiple sets of masks, and multiple chip designs isn't cheap.] Now with redundancy protection and having half the die area as cache on highend its even less of a good idea to reduce highend to low end, product by disabling cache. [Except on itanium volumes].
Consider a 120mm chip with a 60mm cache. If we have low end product with 1/4 of cache thats die area of 75mm Now if cache redundancy will handle 80%+ of defects that hit in cache area (estimated low) and there is overall yield of 80% it means that 4% of chips have defect in cache. And probably under 3% of more chips could be used again. And for low end product you could produce 1.6 as many chips for given die area just by making the cache proportionally smaller. Now if we consider the cache taking 25% of die area for highend(old chip) it means that after redundancy FIX the number of chips that could be rescued because of cache defect is 1% or less.
So having single die for two products and disabling parts of cache has NOTHING to do with reusing defective chips from purely economic reasons. Since making and running the system for reusing the things costs more than it saves.
Think 400mm(mostly cache that is redundancy protected to 90%) chip 80% overall yield 3000$ for a 300mm wafer. The costs is 3000$*400/(PI*150*0.95*0.8) [some slack in edges=0.95 term] The result is ~22$ and real number is lower since Intel has MUCH cheaper wafers since that is what some foundries charge for their customers and intel is low costs leader in manufacturing besides that number has the gross margins for foundry partner included in it.]
The chip I talked about was ITANIUM2 with rounded numbers. P4 in reality costs probably >5$ for the silicon in reality currently. Now saving 1% on some large costs HUH. I think the work of making the recycling system outweights any gains for intel that could get from recycling bad cache parts as low end product. No they have ALL good parts in their high end product line, and they blow the fuse only because the want to make some low end products out of it. BTW testing isn't cheap compared to silicon, in manycases its more expensive part of the process, and should be kept as simple as possible.
Slashdot Mirror
This beats the normal standard of dupes.
TFA points to a slashdot article for the issue.
Mass layoffs are bad, not by virtue of having chance of loosing the good staff but by virtue of loosing SIGNIFICANTLY MORE of the good staff than incompetent as in % vice of their existence in company.
How much they save?
700M$ a year estimated.
How much it costs for the action to happen?
Do they loose the good ones instead of bad ones?
There has been more or less common to loose the people you don't want to get rid off because there are layoffs.
Next question is that DO they loose some of their business because of layoffs, by loosing more talented persons willing to jump ship?
Are competitors getting insights by hiring people IBM just lost?
They are risking 9B$ profits by cutting 0.7B$ thats the effect. They cut costs but same time they cut their sales. Now there is risk of loosing more in sales than getting by cutting employees.
Have you ever known Athlon 64 that was sold and the advertised clockspeed was 1Ghz? My chip is 2Ghz chip which runs at 1ghz when I surf the net. But when I look at AVI it goes to its nominal speed of 2Ghz.
Well when you go for 0.9u or deeper technology the lifetime begins to matter...
You got 50% clock speed increase at time when the memory interface wasn't such a bottleneck as it is today. The older processes tolerate overclocking better. What I'm saying that what you get today isn't worth the risks. When I used 366 celeron I would of overclocked at the END OF ITS USABLE LIFETIME. Not before, before that its unnecessary risk which I took and once changed my GFX card and HD because of experimentation, got replacement by guarantee though. At near the end I wouldn't care anymore as long as my data was backed up. Still remember the percentages. Similar performance increate that we get today it would of been overclock to 350mhz from your 300mhz. Also there is BIG difference of overclocking a something near the bottom grade to match clock speed of higher grade chips, than going beyond designed clockspeed, and going from middle grade to way beyond the designed limits, since the odds are that you are getting actual middle grade chip instead of top grade chip. But getting from bottom grade to midgrade is more probably non harmfull, since odds are that you might have a midgrade chip just marked lower, but NOT GUARANTEED THAT.
EMU10K2 beats the CPU in processing power. So if you can offload it to that it would be good idea.
WOOHOO 20% higher clockspeed ! ;)
It gives 10% more realworld performance.
And 10000% higher failure/error rate!
Well having 100x higher error rate might go undetected most of time since errors in cpu are not that common without overclocking.
Anyway. I'm thinking that what the overclocking gives is minimal increase not worth the potential problems. Not everyone get problems, and not everyone who got problems realize them.
How you tell if the X server crashed by change of a bit at some place or by software failure if the error happens rarely enough? Or some other bit crashing.
It simply goes that they burn em and test them to fit at certain point. Few people get lucky because they need to mark some chips at lower speed than they are truly capable and they keep certain margins on the chip timings to ensure it works. But getting rid of those margins just gives a potential like.
If certain datapath gets used commonly enough, it gets hot, and it slows it down. The different bit patterns may show what kind of changes makes it hottest. Now those problems can be at ANY circuit location. It can be parts of alu, FPU, instruction decoder, cache. ANYTHING that just cannot keep with certain changing bit patterns when it becomes hot. And don't say that your cooling helps this a lot. Well the problem is INDIVIDUAL TRANSISTORS temperature not average chip temperature. And those transistors are becoming so small for dissipation.Plus it might be that the cycle time is not enough even at normal temperatures to keep up with worstcase changing bit patterns. Billions of different things CAN go wrong, with overclocked chip, and we don't know what it takes to burn certain paths. Then there is electromigration which worsens with voltage increases and so on. Basicly you are trading the lifetime and reliability of results for getting 10% more results.
I've though thats not worth it for me, I'm more happy with my A64 chip, staying at 1Ghz when I don't need its performance and powering up to 2Ghz when load goes up. And having PC thats more quiet than other sound sources around here, like flow of water trough the pipes for heater, is more important me than the bragging rights of 10% higher performance
No you got it wrong.
Its fucking Hillaryous.
I'm using A64 with integrated everything, just plugged processor & ram & drives and put inside case. Cheap indeed. But there was a performance price for doing so.
Integrated GFX sux in X even outside 3D games, id rather utilize the memory bus for something else. And accelerate it faster. Another that I can feel the difference is integrated sound. That correct, the onboard audio becomes choppy when system does something else. I might be inclined to believe that the problem is with COMBINATION of integrated GFX and sound trying to do their stuff at the same time.
On K7 I had similar problems when I did have similar combination but it went away with installing a SBLIVE value from year 99. (which went with the K7 machine to buy a new A64)
With integrated everything there is problem if those integrated chips drivers assume they can USE the main cpu whenever they want and then there are collisions there. Anyway those heavily integrated MB:s are really cheap so there is no harm done if getting one. Just remember that you need either discreet soundcard OR GFX card anyway.
Yes the onboard Vi sucks emacs is better!
The article seems to think that they saw a empty slot in ecology and filled it...
"Perhaps certain dinosaurs were pushed along the evolutionary route to vegetarianism because they lived in an area where there was no other plant-eating competitor, he suggests."
I think that if this where the case there was not just evolutionary pull but a push also. If they lived in area without plant eating competitor it makes me wonder what does a carnivore eat...
Oh boy, thats the brains of a PHD put in great use, helping the future of mankind.
Oh well the research doesn't pay that well does it?
ANY x86 is a crap when talking about floating point. Especially when talking about that era. It was about the time when fastest x86 got 1/4 floating point performance of fastest risc. But on integer side the difference was smaller. So both floating point and integer performance scale have many different points where chips reside. From what I recall Cyrix 6x86 price was equal to a pentium with equal floating point performance while delivering much better integer performance by having superiour architecture. But the thing that gave them bad reputation was that people without realizing overclocked their chips 25% by setting the MB run at frequency of the rating instead of frequency it was supposed to run, and then wondering what gave them strange errors, and being without some extensions intel added with their latests chip just like nowadays AMD was without SS3 for a while except that at the day some people used those extensions and users that used ANYTHING BUT INTEL PENTIUM got hurt at the time.
This thing is really bad and crappy. You know its WINDOWS!
There is nothing as bad as windows, although eye candy makes you see the blue screen WITH TRANSPARENCY!
You know its BLASHPHEMY to put a link for a microsoft promoting article in slashdot.
Well. Cyrix 5x86 and 6x86 chips where good.
It had two problems. First they couldn't predict at design phase the features intel was going to add and they lacked some PENTIUM compability while they where compatible with older x86 chips.
2ndly Their floating point performance was lackluster. Although their integer performance was great.
Quake was one of rare cases where it bite really. Since normally even with floating point applications the integer performance is the key, and floating point performance is only secondary as those are rare instructions in the instructions mix anyway. Too bad for cyrix quake became THE benchmark to evaluate the performance.
I must tell that after I've learned something about the C compilation today.
I doubt that C compiler can optimize enough, you have to. Either write in assembler or know what the compiler will output in different situations and code accordingly. There is one order of magnitude performance difference between optimized assembler and c-code that doesn't take account on what is assembler output of the code with same basic algorithm, depending on situations as C code can be efficient too. And no, the compiler cannot help as it lacks the information that could varrant those optimizations.
No I'll keep learning. I just dissassembled and tested this to work on 3 different platforms with multiple optization levels just to make sure that compiler does always stop before testing condition2.
on if(condition1||condition2)
Anyway as long as there is employed persons who do.
if(condition1) goto label2
DOTHINGS;
label2:
I think I'm not first one to go.
If you ask what I DO then I'll have to ask have your mobile phones had any crashes?
Okay here is something.
,and for 2nd the targets are always at the end of function and in numbered sequence if need more than one different location in sequence of freeing specific resources used inside function.
If you have TWO conditions to one specific code sequence where 2nd test *CAN* cause pagefaults if first test do not pass. The said code sequence is such that creating a separate function for it is out of question and replicating the sequence inside elseif would be just another place to fix problems. So I go for short goto sequences.
Like contion1 is something like if pointer=null or arrayindex=-1 or something similar.
Yes the arrayIndex=-1 while accessing array CAN cause pagefaults. Getting array mallocated to a new page so that the arraystarts at pageboundary and later when previous page gets freed using arrayindex -1 in tests gets pagefault. And depending on malloc implementation for large mallocations they hit ALWAYS pageboundary.
IF(condition1) goto label1;
IF(condition2) {
label1:
DOTHINGS;
}
I doubt people have such problems that such form becomes mysticly unreadable because use of goto.
2ndly I use GOTO as a replacement for return statement in functions where I need properly release the locks and do free() and other issues that are complex enough to varant the GOTO and for some reason would be stupid to put in its own function . But I use descriptive label, FUNCTION_END:
GOTO FUNCTION_END; is a line that you could read quite well.
Of course there is obvious nongoto way for first issue.
if(condition1){
DOTHINGS;
} else if (condition2) {
DOTHINGS;
}
Difference here is that there are TWO locations where you DOTHINGS. If we make a BUG in DOTHINGS there is risk that the guy that fixes it fixes it in only ONE location while leaving the other untouched, and goes happily since his testing shows that the bug got fixed. Or we add a feature and introduce some difference between those two paths and thats a BUG. And what about 3 tests wich each if succeed lead to DOTHINGS but if fails the later test(s) COULD cause a pagefault.
But for the 2nd thing I don't know what else to do in C. If I copy the code in the end to all locations where I should return I risk creating really bad syncronization bugs that are VERY hard to track down. I only need to make mistake ONCE in many locations to create deep problems that seem to pop up in completely unrelated location of code.
Or trying to do 100+ lines of code in DEEP nesting inside functions might be solution but when I look at the code it becomes REALLY unreadable by trying to track in which depth each thing should be instead being sequential.
Yes I'd prefer not doing same code sequences in multiple places since fixing a bug requires changing em all. I've just learned to DOCUMENT the use of goto and reasons for it so that others don't try to "fix" it. TWO METHODS of using goto separated by labelname, ONLY forward gotos. For first condition no unrelated code between goto and label
The 64bit is for anyone with more than 2Gb of RAM + x86-64 gives you more registers besides being 64bit so it speeds up the recompiled code.
Dual core means simply you have TWO processors running. Rember old reviews on SMP dual celeron A and other such reviews. It gives little for games, lots for certain multithreaded applications. As you have two processors running and doing things. And multitasking applications, like being able to run interactive application (doom 3), while system is doing some multihour compilation on background.
Anyway, it mainly keeps system more responsive when you have some thread or application takes CPU.
Also with lesser degree helps in some other similar situation, where CPU is tied up with something EXACLY same moment you would wan't it to deal with UI stuff.
Nah. AI just simulates american mind set.
Is in its configurability.
What about standard size planet filled with great AI and slow research, no huts giving random military units. I just loved it. 2 settlers you start with, find a place to start then, its war for expansion immediately.
Basicly freeciv lets me hack with options that can change the gameplay of old game a LOT, and make it even more interesting. You can alter the population growth rate so that you get different variations on what will happen.
I can change the game options to play WAY different way compared to original civ. And there are lots of minor differences that make it different from CIV & CIV2 atleast in way of the strategies goes.
Is not the single thread performance or how fast can you finish task X. ;)
Its responsiveness of the system. I'm using A64 3000 and I get annoying stalls on system level.
The CPU spends time with the backside thread, while I would love it working on UI, there is annoying stall. Multiple CPU:s according to reviews remove those issues. And don't say having 20% higher processor clock speed is going to help, its by simple fact that CPU was just doing something else at a time I would of loved it to handle UI events. Having 2 cores means, that responsiveness of a system is greatly improved, atleast until people write most of their applications to tie up more than one core
In soviet russia hard-drives upgrades the size of YOU!
Celerons where mostly different chips.
Why?
Firstly L2 cache is redundancy protected. It means that instead of 256KB of cache there is 260KB or something similar amount of cache there are defective lines are replaced with a one that works. Another point is that L2 cache wasn't half the die area at the time not even close. So the defects because of the L2 is quite minimal, as many can be masked away. Another point is that MFG with less cache makes die area smaller so it would be cheaper for MASS producing it. Initially having same die size is effect of using SINGLE mask on both, and ADAPTING INVENTORY DEPENDING ON DEMAND. And avoid of spending ~Million dollars for having some savings in spend die area.
[Having multiple sets of masks, and multiple chip designs isn't cheap.]
Now with redundancy protection and having half the die area as cache on highend its even less of a good idea to reduce highend to low end, product by disabling cache. [Except on itanium volumes].
Consider a 120mm chip with a 60mm cache. If we have low end product with 1/4 of cache thats die area of 75mm Now if cache redundancy will handle 80%+ of defects that hit in cache area (estimated low) and there is overall yield of 80% it means that 4% of chips have defect in cache. And probably under 3% of more chips could be used again. And for low end product you could produce 1.6 as many chips for given die area just by making the cache proportionally smaller. Now if we consider the cache taking 25% of die area for highend(old chip) it means that after redundancy FIX the number of chips that could be rescued because of cache defect is 1% or less.
So having single die for two products and disabling parts of cache has NOTHING to do with reusing defective chips from purely economic reasons. Since making and running the system for reusing the things costs more than it saves.
Think 400mm(mostly cache that is redundancy protected to 90%) chip 80% overall yield 3000$ for a 300mm wafer.
The costs is 3000$*400/(PI*150*0.95*0.8) [some slack in edges=0.95 term] The result is ~22$ and real number is lower since Intel has MUCH cheaper wafers since that is what some foundries charge for their customers and intel is low costs leader in manufacturing besides that number has the gross margins for foundry partner included in it.]
The chip I talked about was ITANIUM2 with rounded numbers. P4 in reality costs probably >5$ for the silicon in reality currently. Now saving 1% on some large costs HUH. I think the work of making the recycling system outweights any gains for intel that could get from recycling bad cache parts as low end product. No they have ALL good parts in their high end product line, and they blow the fuse only because the want to make some low end products out of it.
BTW testing isn't cheap compared to silicon, in manycases its more expensive part of the process, and should be kept as simple as possible.
Hey why not the developers would do with the only incubator they are going to use, get a 9 month release cycle for their favourite (and only child;)