It's not at all obvious to me what they actually want.
They obviously know about the ISO MPEG-4 source since they provide it, and this is freely licenced. You still need to licence the MPEG-4 patents though, as you still would if you reimplemented the CODEC yourself.
It's also rather bizarre that they have provided the Microsoft (was that publically released?!) MPEG-4 source in addition, since anyone getting anythign from it will probably be infringing on Microsoft's copyrights and patents.
So what's the goal here? If you want an MPEG-4 implementation and are willing to say "screw the patents" then just use the ISO source. Reimplementing it won't help. Given that MPEG-2 has similar patent issues yet MPEG-2 open source CODECs are available without (yet) any heat from the patent owners, I'd say just use it!
Find out who's the maintainer for that piece of code and send the patch to them. Alan Cox is generally only going to be interested in fixes for stuff he's personally responsible for, or collating other approved patches.
Does anyone know if the G450 supports hardware YUV-to-RGB conversion and scaling on BOTH the primary and secondary outputs, and if this is supported by the Xv extension under XFree86 4.0?
Also, does the dual head support appear as two X screens (as reported by xdpyinfo) under XFree?
AMD list on their web site what power supplies are approved for Athlon. If you're building your own system then go with one of these and you can't go wrong. If you want to cheap out with a 250W supply, then good luck to you!
By the end of the year AMD will have moved to their new Mustang "corvette" core which massively cuts power requirements and enables mobile athlons. This is what I'm waiting for to upgrade (Mustang/DDR) - not Intel's space heater P4!
Remember that Tom's was the first one to speak out against Rambus memory when everyone else was claiming how great it is. Now even Intel have vindicated Tom's Hardware, and are moving from RDRAM to DDR.
Looks like Tom's may have been the first to point out the PIII 1.13 GHz problems too. I think Tom's anti-Intel reputation is just because everyone else has an unrealistic (i.e. out of date) idea about how good Intel are, while Tom's isn't afraid to call it how they see it.
Burnt barcodes sounds like inadequately cooled CPU's to me. It'd be interesting to know if those were using boxed processor "thermal solutions", and whether they were being oc'd or not.
If T-Birds in general had a 10% failure rate, then I think we'd have heard about it from Compaq, Gateway, HP et al.
The issue is that heatsinks for PIII/Celeron and Thunderbird/Duron arn't interchangeable due to different physical dimensions of the chips. If you use an AMD approved heatsink or one specifically designed for T-Bird/Duron (e.g. there is a special Golden Orb version for them) then it'll be fine, but if you use one made for an Intel CPU then you may well damage the CPU.
If the compiler and/or CPU is unable to reorder instructions effectively (or if a particular piece of code is not amenable to reordering), then an instruction in the pipeline may not have it's operands ready when it needs them and will stall the pipeline waiting for them. With a longer pipeline it will take more clock ticks for the necessarty operands to work their way thru the pipeline to clear the stall. Intel have added a double clock speed arithmetic unit (ALU) to the P4 to try to mitigate operand latency.
2) Branch mispredict penalty:
When a modern CPU such as the P4 encounters a branch instruction, it predicts whether the branch will be taken or not (by using the execution history) in order to be able to continue processing instructions through the pipeline. When the branch is finally evaluated near the end of the pipeline it may turn out that the prediction was wrong, and that all the instructions following the branch (now in the pipeline) should not ne executed. In this case the processor has to flush the pipeline and instead take the correct branch. This "pipeline flush" branch mispredict penalty is obviously higher the longer the pipeline is - a 20 stage pipeline means you are throwing away 20 instructions when a branch is mispredicted.
P4 was designed with a long pipeline so that each pipeline step could be very simple/quick and therefore the processor could have a very high clock rate. The downside of doing this is the above two problems, which mean that the average number of instructions executed per clock cycle (IPC - aka processor efficiency) gets reduced.
P4 at 1.4GHz may be faster than P3 at 1GHz, but because P4 will have a lower IPC than P3, it won't be as fast as a 1.4GHz P3 (if we ever see one) or 1.4GHz Athlon (which we will see).
The one area where P4 should excel is in SSE2 optimized floating point math intensive applications, which is why Intel are now trying to reposition the P4 as an Internet/multimedia CPU rather than a general purpose one. The fallacy of this is that once you can decode your DivX in real-time, you don't need to go any faster!
I believe Qt designer spits out C code, not some high level XML representation of the interface, so you're SOL there!:-(
Perhaps the best way to implement what you're after would be to implement a "libqtglade" that instantiates glade interfaces in Qt rather than GTK+ as libglade does.
Pinker's "How the mind works" was well reviewed, but I think he's better suited sticking to pure linguistics than veering off into cognitive science...
If you want an (IMO more plausible) alternative to Pinker's Chomskian explanation of language, I'd recommend Derek Bickerton's "Language and Species".
People viewing habits change with Tivo. Tivo is really a time shifter that lets you watch TV on your schedule rather than the networks - it's a different concept from a VCR. Many people with Tivo's NEVER watch live TV, because it's much more convenient to use Tivo to start watching a show, say 30 min, later than the network time, then you can fast forward thru all the commercials.
Tivo's threat to the TV industry is simply about advertizing because of the ability to skip advertisements (or for Tivo to insert their own, which they havn't done - yet). Tivo's competitor Replay has a "30 sec skip" button used for skipping commercials, but Tivo doesn't have one due to pressure from it's network partners...
Remember he was the first one to point out that Rambus performed worse than SDRAM, when everyone else was claiming it was great but just too expensive.
Intel are now part of an industry law cuit fighting Rambus patents, and have announced a complete U turn and will support SDRAM and DDR for P4.
I'll give Tom the benefit of the doubt on this one - lets wait a while, and I'm sure the truth will come out about the microcode update.
The benchmark results were AWFUL (although interstingly both agreed - one set run on an Intel demo at WinHEC 2000, and one set on am enginerring sample that got into the wrong hands). 800MHz P4 performed like a 600MHz PIII!!!
I don't doubt that P4 will excell at some particular tasks. If used with dual-channel PC800 RDRAM and an SSE2 optimized application, I believe it will be able to turn in some impressive FP numbers. However that doesn't mean it's going to offer good general purpose performance, or perform well on legacy code.
P4 won't beat AMD on clock speed. 1.3/4GHz P4 will be up against 1.3/4GHz Mustang this year, and both will be at 1.5GHz in Q1 of next year. Maybe technically Intel will launch the 1.5GHz P4 this year (just like, technically, they launched the 1GHz PIII back in march), and Dell will sell 3 of them.
PIII is first being shrunk 5% while still at 0.18 micron. This will be the 1.15GHz part, and is slated for low-volume "release" on July 31st.
PIII will also be shrunk by a move to 0.13 micron. This is the "Tualatin" PIII core that is slated for introduction mid next year, after P4.
P4 is being introduced at 0.18 micron in a 432 pin package, will then switch to a mysterious 0.18 micron 479 pin package early next year, and is then slated for a shrink to 0.13 micron also around the middle of next year.
Given that Intel are only just starting on th move to 0.13 micron (and the fact that historically they've always been well behind state of the art inn process technology), I'd take those mid-2001 0.13 micron shrinks with a grain of salt! Mid 2001 is about the timeframe for process verification/samples; I'd be VERY surprised if Intel are ready for 0.13 PRODUCTION before the end of next year.
I'm not sure where you get that Intel say P4 will be a high end part. They intend P4 to replace PIII, and PIII to replace Celeron. It's not apparent that P4 adoption will be fast though because:
1) It will intially be Rambus only until Via produce a DDR chipset and fight Intel in court for the right to market it (thay have stated this is what they intend to do. Intel themselves have a legal agreement with Rambus that prevents them from making DDR chipsets for P4 .
2) None of the Taiwanese motherbaord makers have expressed interest in making P4 motherboards, because of the short life of the initial 432 pin package. They will at least wait until the 479 pin package, and maybe until Via's DDR chipset is available.
By all accounts P4's x87 performance may be BELOW PIII's, so when you're talking about good P4 FP performance you're presumably talking about SSE2, not x87...
Note that P4 has SSE2, not SSE. Photoshop is only going to faster if/when it gets P4-specific support, which isn't likely to occur before it becomes a volume part. Intel themselves have stated that P4 will take ("3-8 quarters") to replace PIII (up to 2 years!!!), and certainly it's hard to see the initial 432 pin P4 being volume since Intel are planning to replace it with tht 479 pin part in about 6 months (gee, wonder why..). I expect P4 with it's huge 170 sq. mm (vs 120 for Athlon) die, huge power consumption and heat output, will not be a viable mass volume part until a 0.13 die shrink sometime late next year.
Unless you think I'm unduly pessimistic about P4, look at Itanium. Now many YEARS late, and currently scheduled to launch at 733MHz (struggling in the lab at 600MHz), vs an original 1GHz+ goal... Intel arn't exactly the CPU geniuses many seem to think they are! With Intel's huge R&D budget, they still produce fewer CPU patents per year than tiny AMD!!!!
I have seen two sets of leaked P4 benchmarks, and both were dismal, other than predictably impressive memory bandwidth (with dual channel Rambus memory). Never mind the benchmarks, there is at least one MAJOR reason to question P4's performance - the pipeline length. P4 has a pipeline around 20 steps to allow it to reach very high clock speeds, but this brings with it two major penalties:
- branch mispredict pipe flush (lose 20 instructions!!!) - instruction latency; waiting for instruction arguments takes a lot of clock cycles
Comparing P4's double pumped ALU to Athlon, you should remember that Athlon has 3 Integer units, and 3 Floating point units (PIII has 2 of each). On certain benchmarks, Athlon just beats PIII silly because of this:
When Athlon is paired with DDR memory and is able to keep it's multiple instruction decoders (it can issue 3 instructions per clock cycle) fed, then it is going to scream, never mind the advantages that Mustang will bring such as it's 400MHz FSB.
A final point for you to ponder: if P4 is clock-for-clock faster than PIII (I don't believe it), then why doesn't Intel launch it at 1.2 or 1.3GHz (vs fastest PIII 1.1GHz). A process doesn't yield such a narrow (1.4-5 or 1.3-5) speed band, so Intel must be throwing away the lower binsplits! Why?.....
Every indication that I can see points to P4 having been designed for very high clock speeds at the expense of instructions-per-clock performance. AMD Mustang will launch at 1.3GHz and will be in volume before P4. Mustang achieves it's speed more through better process technology (AMD licenced Motorola's HiP6L copper interconnect process, and is well on their way to dual damascene and 0.13 micron), than through Intel pipeline-achieved GHZ marketing stunts.
AMD's Athlon has a 200/266MHz FSB and can use DDR bandwidth. PIII has a 100/133MHz FSB and will get very little (maybe zero) gain from DDR.
With CPU speeds around 1GHz and memory around 133MHz, memory is THE bottleneck for many applications. Increasing processor speed from 900MHz to 1GHz may be nothing to be excited about, particularly since the performance increase is much less than the clock speed increase. DOUBLING memory bandwidth IS something to be excited about, since it should have a HUGE impact on performance!
AMD's Mustang processor will be out in a few months and will match P4's 400MHz FSB (except it will use affordable DDR memory). It is rumoured to possibly also have Sledgehammer's "Technical floating point" unit which will blow P4 out of the water.
FWIW Sledgehammer will sample in Q1 2001, to ship late in the year, and therefore will not be far behind Mustang.
From the P4 benchmarks that have leaked, it appears that Intel may well be the ones in serious trouble. Certainly Intel's plans for PIII don't exactly jive with it being obsoleted by P4...
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Total effort to do what???
It's not at all obvious to me what they actually want.
They obviously know about the ISO MPEG-4 source since they provide it, and this is freely licenced. You still need to licence the MPEG-4 patents though, as you still would if you reimplemented the CODEC yourself.
It's also rather bizarre that they have provided the Microsoft (was that publically released?!) MPEG-4 source in addition, since anyone getting anythign from it will probably be infringing on Microsoft's copyrights and patents.
So what's the goal here? If you want an MPEG-4 implementation and are willing to say "screw the patents" then just use the ISO source. Reimplementing it won't help. Given that MPEG-2 has similar patent issues yet MPEG-2 open source CODECs are available without (yet) any heat from the patent owners, I'd say just use it!
IANAL.
mpeglib will also let you play divX's on Linux - it wraps the Windows CODEC.
http://mpeglib.sourceforge.net/
Find out who's the maintainer for that piece of code and send the patch to them. Alan Cox is generally only going to be interested in fixes for stuff he's personally responsible for, or collating other approved patches.
Does anyone know if the G450 supports hardware YUV-to-RGB conversion and scaling on BOTH the primary and secondary outputs, and if this is supported by the Xv extension under XFree86 4.0?
Also, does the dual head support appear as two X screens (as reported by xdpyinfo) under XFree?
AMD list on their web site what power supplies are approved for Athlon. If you're building your own system then go with one of these and you can't go wrong. If you want to cheap out with a 250W supply, then good luck to you!
By the end of the year AMD will have moved to their new Mustang "corvette" core which massively cuts power requirements and enables mobile athlons. This is what I'm waiting for to upgrade (Mustang/DDR) - not Intel's space heater P4!
If a link to a page that has DeCSS is illegal, then what about a link to a page that has a link to it?
Maybe the whole web is illegal since it's all interlinked.
I hope some judge has the common sense to rule that pointing to a crime isn't illegal.
I'm not sure what you're looking at.
Try this link (same as I posted above).
Select Dimension XPS B Processor
If you can find a place on Dell's site that lets you select a 1.13GHz processor, then please post the link!
Dimension XPS B used to support 1.13GHz...
i men_desktops.htm
_ dim_b.htm
http://www.dell.com/us/en/dhs/products/series_d
But 1.13GHz choice has now been pulled:
http://www.dell.com/html/us/segments/dhs/choose
Remember that Tom's was the first one to speak out against Rambus memory when everyone else was claiming how great it is. Now even Intel have vindicated Tom's Hardware, and are moving from RDRAM to DDR.
Looks like Tom's may have been the first to point out the PIII 1.13 GHz problems too. I think Tom's anti-Intel reputation is just because everyone else has an unrealistic (i.e. out of date) idea about how good Intel are, while Tom's isn't afraid to call it how they see it.
AMD's 760 and Via's KX266 chipsets will both support Athlon and Duron SMP, and with both be out around the end of the year (Christmas?).
Burnt barcodes sounds like inadequately cooled CPU's to me. It'd be interesting to know if those were using boxed processor "thermal solutions", and whether they were being oc'd or not.
If T-Birds in general had a 10% failure rate, then I think we'd have heard about it from Compaq, Gateway, HP et al.
Maybe Sharky's has a bone to grind...
The issue is that heatsinks for PIII/Celeron and Thunderbird/Duron arn't interchangeable due to different physical dimensions of the chips. If you use an AMD approved heatsink or one specifically designed for T-Bird/Duron (e.g. there is a special Golden Orb version for them) then it'll be fine, but if you use one made for an Intel CPU then you may well damage the CPU.
If peer to peer software uses existing protocols like HTTP, FTP, SMTP, then there's nothing anyone can do to block it.
BTW, doesn't that Sony ranting rather sound like Mike Tyson's "I wanna rip his heart out, I wanna eat his children..."?
I was about to add a big cheap IDE drive to my PC, but a few smaller SCSI drives off e-bay are a much better idea!
Heh, my antique PII 266MHz only has a 4GB UW SCSI drive right now...
1) Pipeline stalls / operand latency:
If the compiler and/or CPU is unable to reorder instructions effectively (or if a particular piece of code is not amenable to reordering), then an instruction in the pipeline may not have it's operands ready when it needs them and will stall the pipeline waiting for them. With a longer pipeline it will take more clock ticks for the necessarty operands to work their way thru the pipeline to clear the stall. Intel have added a double clock speed arithmetic unit (ALU) to the P4 to try to mitigate operand latency.
2) Branch mispredict penalty:
When a modern CPU such as the P4 encounters a branch instruction, it predicts whether the branch will be taken or not (by using the execution history) in order to be able to continue processing instructions through the pipeline. When the branch is finally evaluated near the end of the pipeline it may turn out that the prediction was wrong, and that all the instructions following the branch (now in the pipeline) should not ne executed. In this case the processor has to flush the pipeline and instead take the correct branch. This "pipeline flush" branch mispredict penalty is obviously higher the longer the pipeline is - a 20 stage pipeline means you are throwing away 20 instructions when a branch is mispredicted.
P4 was designed with a long pipeline so that each pipeline step could be very simple/quick and therefore the processor could have a very high clock rate. The downside of doing this is the above two problems, which mean that the average number of instructions executed per clock cycle (IPC - aka processor efficiency) gets reduced.
P4 at 1.4GHz may be faster than P3 at 1GHz, but because P4 will have a lower IPC than P3, it won't be as fast as a 1.4GHz P3 (if we ever see one) or 1.4GHz Athlon (which we will see).
The one area where P4 should excel is in SSE2 optimized floating point math intensive applications, which is why Intel are now trying to reposition the P4 as an Internet/multimedia CPU rather than a general purpose one. The fallacy of this is that once you can decode your DivX in real-time, you don't need to go any faster!
I believe Qt designer spits out C code, not some high level XML representation of the interface, so you're SOL there! :-(
Perhaps the best way to implement what you're after would be to implement a "libqtglade" that instantiates glade interfaces in Qt rather than GTK+ as libglade does.
Pinker's "How the mind works" was well reviewed, but I think he's better suited sticking to pure linguistics than veering off into cognitive science...
If you want an (IMO more plausible) alternative to Pinker's Chomskian explanation of language, I'd recommend Derek Bickerton's "Language and Species".
People viewing habits change with Tivo. Tivo is really a time shifter that lets you watch TV on your schedule rather than the networks - it's a different concept from a VCR. Many people with Tivo's NEVER watch live TV, because it's much more convenient to use Tivo to start watching a show, say 30 min, later than the network time, then you can fast forward thru all the commercials.
Tivo's threat to the TV industry is simply about advertizing because of the ability to skip advertisements (or for Tivo to insert their own, which they havn't done - yet). Tivo's competitor Replay has a "30 sec skip" button used for skipping commercials, but Tivo doesn't have one due to pressure from it's network partners...
I love hi-tech toys as much bas the next guy, but I think this is going a bit far!
"What time is it?"
"I dunno, I'm just re-booting my watch!"
Remember he was the first one to point out that Rambus performed worse than SDRAM, when everyone else was claiming it was great but just too expensive.
Intel are now part of an industry law cuit fighting Rambus patents, and have announced a complete U turn and will support SDRAM and DDR for P4.
I'll give Tom the benefit of the doubt on this one - lets wait a while, and I'm sure the truth will come out about the microcode update.
The benchmark results were AWFUL (although interstingly both agreed - one set run on an Intel demo at WinHEC 2000, and one set on am enginerring sample that got into the wrong hands). 800MHz P4 performed like a 600MHz PIII!!!
I don't doubt that P4 will excell at some particular tasks. If used with dual-channel PC800 RDRAM and an SSE2 optimized application, I believe it will be able to turn in some impressive FP numbers. However that doesn't mean it's going to offer good general purpose performance, or perform well on legacy code.
P4 won't beat AMD on clock speed. 1.3/4GHz P4 will be up against 1.3/4GHz Mustang this year, and both will be at 1.5GHz in Q1 of next year. Maybe technically Intel will launch the 1.5GHz P4 this year (just like, technically, they launched the 1GHz PIII back in march), and Dell will sell 3 of them.
You're confusing the PIII and P4 shrinks.
PIII is first being shrunk 5% while still at 0.18 micron. This will be the 1.15GHz part, and is slated for low-volume "release" on July 31st.
PIII will also be shrunk by a move to 0.13 micron. This is the "Tualatin" PIII core that is slated for introduction mid next year, after P4.
P4 is being introduced at 0.18 micron in a 432 pin package, will then switch to a mysterious 0.18 micron 479 pin package early next year, and is then slated for a shrink to 0.13 micron also around the middle of next year.
Given that Intel are only just starting on th move to 0.13 micron (and the fact that historically they've always been well behind state of the art inn process technology), I'd take those mid-2001 0.13 micron shrinks with a grain of salt! Mid 2001 is about the timeframe for process verification/samples; I'd be VERY surprised if Intel are ready for 0.13 PRODUCTION before the end of next year.
I'm not sure where you get that Intel say P4 will be a high end part. They intend P4 to replace PIII, and PIII to replace Celeron. It's not apparent that P4 adoption will be fast though because:
1) It will intially be Rambus only until Via produce a DDR chipset and fight Intel in court for the right to market it (thay have stated this is what they intend to do. Intel themselves have a legal agreement with Rambus that prevents them from making DDR chipsets for P4 .
2) None of the Taiwanese motherbaord makers have expressed interest in making P4 motherboards, because of the short life of the initial 432 pin package. They will at least wait until the 479 pin package, and maybe until Via's DDR chipset is available.
By all accounts P4's x87 performance may be BELOW PIII's, so when you're talking about good P4 FP performance you're presumably talking about SSE2, not x87...
Note that P4 has SSE2, not SSE. Photoshop is only going to faster if/when it gets P4-specific support, which isn't likely to occur before it becomes a volume part. Intel themselves have stated that P4 will take ("3-8 quarters") to replace PIII (up to 2 years!!!), and certainly it's hard to see the initial 432 pin P4 being volume since Intel are planning to replace it with tht 479 pin part in about 6 months (gee, wonder why..). I expect P4 with it's huge 170 sq. mm (vs 120 for Athlon) die, huge power consumption and heat output, will not be a viable mass volume part until a 0.13 die shrink sometime late next year.
Unless you think I'm unduly pessimistic about P4, look at Itanium. Now many YEARS late, and currently scheduled to launch at 733MHz (struggling in the lab at 600MHz), vs an original 1GHz+ goal... Intel arn't exactly the CPU geniuses many seem to think they are! With Intel's huge R&D budget, they still produce fewer CPU patents per year than tiny AMD!!!!
I have seen two sets of leaked P4 benchmarks, and both were dismal, other than predictably impressive memory bandwidth (with dual channel Rambus memory). Never mind the benchmarks, there is at least one MAJOR reason to question P4's performance - the pipeline length. P4 has a pipeline around 20 steps to allow it to reach very high clock speeds, but this brings with it two major penalties:
k s/23966.html
- branch mispredict pipe flush (lose 20 instructions!!!)
- instruction latency; waiting for instruction arguments takes a lot of clock cycles
Comparing P4's double pumped ALU to Athlon, you should remember that Athlon has 3 Integer units, and 3 Floating point units (PIII has 2 of each). On certain benchmarks, Athlon just beats PIII silly because of this:
http://www.amd.com/products/cpg/athlon/benchmar
When Athlon is paired with DDR memory and is able to keep it's multiple instruction decoders (it can issue 3 instructions per clock cycle) fed, then it is going to scream, never mind the advantages that Mustang will bring such as it's 400MHz FSB.
A final point for you to ponder: if P4 is clock-for-clock faster than PIII (I don't believe it), then why doesn't Intel launch it at 1.2 or 1.3GHz (vs fastest PIII 1.1GHz). A process doesn't yield such a narrow (1.4-5 or 1.3-5) speed band, so Intel must be throwing away the lower binsplits! Why?.....
Every indication that I can see points to P4 having been designed for very high clock speeds at the expense of instructions-per-clock performance. AMD Mustang will launch at 1.3GHz and will be in volume before P4. Mustang achieves it's speed more through better process technology (AMD licenced Motorola's HiP6L copper interconnect process, and is well on their way to dual damascene and 0.13 micron), than through Intel pipeline-achieved GHZ marketing stunts.
DDR doubles potential memory bandwidth.
AMD's Athlon has a 200/266MHz FSB and can use DDR bandwidth. PIII has a 100/133MHz FSB and will get very little (maybe zero) gain from DDR.
With CPU speeds around 1GHz and memory around 133MHz, memory is THE bottleneck for many applications. Increasing processor speed from 900MHz to 1GHz may be nothing to be excited about, particularly since the performance increase is much less than the clock speed increase. DOUBLING memory bandwidth IS something to be excited about, since it should have a HUGE impact on performance!
AMD's Mustang processor will be out in a few months and will match P4's 400MHz FSB (except it will use affordable DDR memory). It is rumoured to possibly also have Sledgehammer's "Technical floating point" unit which will blow P4 out of the water.
FWIW Sledgehammer will sample in Q1 2001, to ship late in the year, and therefore will not be far behind Mustang.
From the P4 benchmarks that have leaked, it appears that Intel may well be the ones in serious trouble. Certainly Intel's plans for PIII don't exactly jive with it being obsoleted by P4...