"However, note that the x86 does all floating point operations with 80-bit precision. So you don't get any performance advantage from using only single precision variables (other than lower memory bandwidth usage)."
Actually, division and square root are faster in single precision mode. FDIV is 18 cycles for single precision vs. 38 for extended precision on a PIII.
This is not going to be a CD burner that you plug into your PC.
This is just for mastering discs for mass production.
It says the readers will just use a blue laser:
"Pioneer's EBR can manufacture master discs for high-density optical discs including Blu-ray discs, as well as Discrete Track Media and Patterned Media - higher-density hard disks regarded as highly promising future technologies."
The microscope appears to have a resolution of about 800 dpi (the grinder is supposed to have a 45mm diameter, I'm basing my guess at the resolution off the photos of the grinding holes). An Intel Play QX3 microscope can take an 8000 dpi picture. Is NASA so poor that they can't afford a $40 microscope for their rover?
AMD64 pages have an execute permission bit. That just means that you can make your buffers non-executable (this can be achieved with segment level protection on normal x86 cpus). You can still have a buffer overflow exploit that doesn't execute any code. For example, consider someone writing a 104 character name to the following structure:
struct user {
char name[100];
int can_write_other_peoples_files; };
Non executable buffers don't help here. True buffer overflow protection would be some kind of hardware assisted bounds checking.
"Yes, but the IA-64 EPIC is not a modern architecture - it is a design by committee, with microarchitects who believed religious dogma instead of thinking.
At least some modern microarchitectures have made optimization easier than in their predecessors. Apart from some egregious glass jaws (mea culpa), P6 was often less sensitive to optimization than the P5. The compiler folks complained that their unoptimized code often ran as fast as their optimized code. AMD's K7 and K8 continue in this vein.
This is one of the reasons I jumped from Intel to AMD: the Intel P6 is philosophically a lot closer to the AMD K7 and K8 than it is to the Intel Pentium 4 (Willamette, Prescott), or Itanium. Pentium 4 is fragile, just like Itanium."
That is the only advantage of using a Transmeta CPU. Wouldn't it be more efficient to just use a regular VLIW CPU without all the x86 code morphing stuff?
Ted Hooton, editor of Jane's Naval Weapon Systems in London, agreed with the assessment, saying problems with payload weight would put the Harpoon out of balance, limiting its range and accuracy.
"It seems to me that a nuclear weapon, which is extremely dense, would make the Harpoon nose heavy and significantly reduce its range -- in any event well below the (150 kilometres) it is designed for," Hooton said.
"In the same way that Slashdot should not be held responsible for what you or I may post in the comments section, there is no staff of Indymedia editors sitting in a room somewhere determining what's going to go up on the news wire. Indymedia only presents an uncensored place on the web for individuals to post their own journalistic efforts."
I don't think we disagree. You say an Indymedia article is like a slashdot comment. That doesn't suggest a high level of credibility.
"Indymedia did have summitted coverage of Israel's acquisition of submarines that fire nuclear-armed Harpoon cruise missiles."
They have the right to free speech and that should not be taken away
from them. But please, don't give them credibility they don't
deserve. Some examples of their work:
I just called Geico and saved a bundle on my auto insurance!
Re:Performance doesn't come directly from 64 bits
on
Is Prescott 64-bit?
·
· Score: 1
X86 certainly is ugly as hell. But IMHO, it looks very clean next to
Itanium/IA64.
The problem with Itanium/IA64 is that it has just about every feature
that has ever been proposed for an ISA bundled together in one giant
mess, with the big feature being that it is EPIC - explicitly
parallel. This means that if you have an instruction that depends on
the result of a previous instruction, it must be separated from that
instruction with a 'stop'. As a result, the instruction groups
between the stops can be executed in parallel without any messy
dependency checking that a normal architecture requires to run
instructions out of order.
It sounds reasonable, but the catch is that to get good performance,
you need more parallelism than is encoded in the explicitly parallel
instruction groups. Newer IA64 implementations will run instruction
groups out of order and have to do dependency checking between them,
just like a regular x86. So now you are stuck with a complicated
explicitly parallel instruction encoding and a processor that still
needs to check dependencies at run time. The goofy encoding gets you
nothing.
All this, yet they couldn't find room for a reg+offset addressing
mode.
On the other hand, AMD has just taken the x86 and removed all the
major problems. An x86 with more registers and a non stack based FPU
is actually a pretty nice ISA.
AMD is shooting itself in the foot with this, but I can sympathize after reading
the following paragraph from
this article.
"Intel now leads rival Advanced Micro Devices Inc. in the so-called
gigahertz race. AMD, whose Athlon chip now tops out at 1.4 GHz, says
its slower chips still perform better than Intel's faster ones."
I just bought a LCD monitor a month ago (a 15 inch Samsung 570v for $450). When I first turned it on, it had one dead pixel at the bottom left side of the screen. After I used it for a few hours the dead pixel came back and has been fine for a whole month now!
I'm really glad I went for an LCD. You can look at it for hours without feeling eye strain. At $450 it cost about $200 more than an equivalent CRT. If you spent a lot of time in front of your monitor it is easily worth it.
Slashdot Mirror
"However, note that the x86 does all floating point operations with 80-bit precision. So you don't get any performance advantage from using only single precision variables (other than lower memory bandwidth usage)."
Actually, division and square root are faster in single precision mode. FDIV is 18 cycles for single precision vs. 38 for extended precision on a PIII.
"Pioneer's EBR can manufacture master discs for high-density optical discs including Blu-ray discs, as well as Discrete Track Media and Patterned Media - higher-density hard disks regarded as highly promising future technologies."
The microscope appears to have a resolution of about 800 dpi (the grinder is supposed to have a 45mm diameter, I'm basing my guess at the resolution off the photos of the grinding holes). An Intel Play QX3 microscope can take an 8000 dpi picture. Is NASA so poor that they can't afford a $40 microscope for their rover?
AMD64 pages have an execute permission bit. That just means that you can make your buffers non-executable (this can be achieved with segment level protection on normal x86 cpus). You can still have a buffer overflow exploit that doesn't execute any code. For example, consider someone writing a 104 character name to the following structure:
struct user {
char name[100];
int can_write_other_peoples_files;
};
Non executable buffers don't help here. True buffer overflow protection would be some kind of hardware assisted bounds checking.
Andy Glew (the designer of the Pentium Pro) on EPIC vs. normal architectures:
"Yes, but the IA-64 EPIC is not a modern architecture -
it is a design by committee, with microarchitects who believed
religious dogma instead of thinking.
At least some modern microarchitectures have made optimization
easier than in their predecessors. Apart from some egregious
glass jaws (mea culpa), P6 was often less sensitive to optimization
than the P5. The compiler folks complained that their unoptimized
code often ran as fast as their optimized code.
AMD's K7 and K8 continue in this vein.
This is one of the reasons I jumped from Intel to AMD:
the Intel P6 is philosophically a lot closer to the AMD K7 and K8
than it is to the Intel Pentium 4 (Willamette, Prescott), or Itanium.
Pentium 4 is fragile, just like Itanium."
That is the only advantage of using a Transmeta CPU. Wouldn't it be more efficient to just use a regular VLIW CPU without all the x86 code morphing stuff?
Here's what someone apparently from trident said about Linux support on the DRI list.
So this nuclear Harpoon has moved the stabilizers, warhead, fuel supply, and has a new engine. Sounds a lot like a complete redesign of the missile.
I think I'll trust the experts who have declared the story BS.
"It seems to me that a nuclear weapon, which is extremely dense, would make the Harpoon nose heavy and significantly reduce its range -- in any event well below the (150 kilometres) it is designed for," Hooton said.
I don't think we disagree. You say an Indymedia article is like a slashdot comment. That doesn't suggest a high level of credibility.
"Indymedia did have summitted coverage of Israel's acquisition of submarines that fire nuclear-armed Harpoon cruise missiles."
You might find this AP article interesting: Sub claim `impossible'
ZIONAZIS BLOW UP U.S. DIPLOMATIC CONVOY TO REGAIN AMERICAN SYMPATHY - Apparently it was THE JEW who killed the three Americans in Gaza this week.
roy horn of sigfried and roy gets what he deserves - The tiger realised he was a capitalist.
Zionism and Nazism: We Can't Tell The Difference, Can You? - THE JEWS are NAZIS!
Moscow demands Jewish tycoon's extradition - First Russian tycoon was A JEW? whatelse new!
Some cartoons: Israeli bus , Iraqi resistance comics , Iraqi rat trap , Iraqi quagmire , Tel Aviv bust stop
Thank Allah for these links! Allahu Akbar!
I think this might be the first ever attempt to create a forum with less credibility than USENET!
I just called Geico and saved a bundle on my auto insurance!
The problem with Itanium/IA64 is that it has just about every feature that has ever been proposed for an ISA bundled together in one giant mess, with the big feature being that it is EPIC - explicitly parallel. This means that if you have an instruction that depends on the result of a previous instruction, it must be separated from that instruction with a 'stop'. As a result, the instruction groups between the stops can be executed in parallel without any messy dependency checking that a normal architecture requires to run instructions out of order.
It sounds reasonable, but the catch is that to get good performance, you need more parallelism than is encoded in the explicitly parallel instruction groups. Newer IA64 implementations will run instruction groups out of order and have to do dependency checking between them, just like a regular x86. So now you are stuck with a complicated explicitly parallel instruction encoding and a processor that still needs to check dependencies at run time. The goofy encoding gets you nothing.
All this, yet they couldn't find room for a reg+offset addressing mode.
On the other hand, AMD has just taken the x86 and removed all the major problems. An x86 with more registers and a non stack based FPU is actually a pretty nice ISA.
This was written by an "AP Technology Writer".
I'm really glad I went for an LCD. You can look at it for hours without feeling eye strain. At $450 it cost about $200 more than an equivalent CRT. If you spent a lot of time in front of your monitor it is easily worth it.