I was on the architecture team for Cray & SGI mpp &Cc-NUMA machines in the 90s. afaik the first cray mpp (T3D) had the lowest barrier sync latency of any machine ever built, before or since. we could sync 512 nodes in less than a microsecond. turned out to be extremely expensive overkill from the pov of app algorithms. may not be so these days since the compute phases are so much quicker w.r.t the comms than they were back then.
The Cray 2 had a three stage cooling system; the flourinert was pumped through a heat exchanger and dumped it's heat into chilled water, which was either provided by the site's existing HVAC infrastructure or (more likely, since the dissipation was in the Megawatt range) by a dedicated freon-based water chiller. The 5th generation Cray Inc (as opposed to CCC) also used immersion cooling in a similar vein. Many other Cray machines (YMP, C90 and so on used the same 3-stage cooling system, but the modules weren't immersed in the flourinert, rather the coolant flowed through channels in a thermally conductive plate sandwiched between the two boards of each processor or memory module.
This wasn't a means of cooling the boards more cheaply; this was ECL logic... in those days it was the only way you could deliver the required power and have the thing not literally melt.
AKA F--, The simplest explicit programming model on the planet.
Brainchild of Bob Numrich, unsung hero of Cray Research in the early 90's ( & probably much before... but that was when I was lucky enough to work with him)
F-- was Numrich's second great contribution to parallel programming models... the first being the shmem model for the Cray T3D, Four assembly routines which made the raw capabilities of the T3D available to massively parallel applications when every other programming model (e.g. MPI) had about 50x the communication overhead. This was a big factor in Cray's takeover of the short-lived MPP market in the mid 90's.
On the topic of the thread.... Explicit programming models scale to thousands of processors, implicit ones peter out at 4-8. The reason is Data Locality. Explicit models ensure that the processor is operating on data which is local and unshared. Implicit models end up fighting for operands with competing processors. This requires either heroic hardware ( e.g. 70% of the Cray C-90s processor logic was concerned with memory contention resolution) or a dramatic performance dropoff.
Seymour was fond of transparent gizmos too. He also used to say that disks were for people that couldn't afford enough memory - maybe this would have changed his mind....
I have always (possibly mis)understood that most of Lloyds business is in underwriting, which is to say spreading the risk associated with high-value policies issued by an individual insurer.
In the above context, the proposed scheme with OSRM looks eminently sensible - OSRM provides "indemnity services" which shield their customers from Open Source-related liability. OSRM's services are in turn made credible by virtue of the fact that their potential liability is underwritten by Lloyds. The overall effect is hopefully that:
- Any attempted son-of-SCO is denied the opportunity to put the squeeze on thousands of individual companies, but instead has to defeat a well-funded organization whose only purpose is to thwart such attacks.
- The likelihood that any such attack will be mounted is massively decreased because an attacker knows that OSRM and the underwriters will spend any amount of money to defeat the attack.
The upshot it that the underwiters make a ton of money over time out of insuring against a contingency which is itself obviated by the very fact that they are insuring against it. Sweet.
Just because they aren't making low-end chipsets doesn't mean they won't be getting chipset revenue from the low end.
As even the cheaper processors move to multi-core, shared L3, multi-CPU capable, etc, the complexities of producing an unlicensed chipset will become more and more prohibitive.
Assuming AMD can be squeezed out (Intel seems to be making good progress there), then if you want to make a chipset for any kind of low-end PC, then you'll need an FSB license from Intel. They'll likely make more money out of the licensing than they would from the tedious business of designing/making/marketing/selling/supporting the chips themselves.
Slashdot Mirror
I was on the architecture team for Cray & SGI mpp &Cc-NUMA machines in the 90s. afaik the first cray mpp (T3D) had the lowest barrier sync latency of any machine ever built, before or since. we could sync 512 nodes in less than a microsecond. turned out to be extremely expensive overkill from the pov of app algorithms. may not be so these days since the compute phases are so much quicker w.r.t the comms than they were back then.
The Cray 2 had a three stage cooling system; the flourinert was pumped through a heat exchanger and dumped it's heat into chilled water, which was either provided by the site's existing HVAC infrastructure or (more likely, since the dissipation was in the Megawatt range) by a dedicated freon-based water chiller. The 5th generation Cray Inc (as opposed to CCC) also used immersion cooling in a similar vein. Many other Cray machines (YMP, C90 and so on used the same 3-stage cooling system, but the modules weren't immersed in the flourinert, rather the coolant flowed through channels in a thermally conductive plate sandwiched between the two boards of each processor or memory module. This wasn't a means of cooling the boards more cheaply; this was ECL logic... in those days it was the only way you could deliver the required power and have the thing not literally melt.
...which looks out anywhere you want. In the absence of net neutrality, of course, we'd need to revise that definition to "...anywhere _they_ want."
AKA F--, The simplest explicit programming model on the planet. Brainchild of Bob Numrich, unsung hero of Cray Research in the early 90's ( & probably much before... but that was when I was lucky enough to work with him) F-- was Numrich's second great contribution to parallel programming models... the first being the shmem model for the Cray T3D, Four assembly routines which made the raw capabilities of the T3D available to massively parallel applications when every other programming model (e.g. MPI) had about 50x the communication overhead. This was a big factor in Cray's takeover of the short-lived MPP market in the mid 90's. On the topic of the thread.... Explicit programming models scale to thousands of processors, implicit ones peter out at 4-8. The reason is Data Locality. Explicit models ensure that the processor is operating on data which is local and unshared. Implicit models end up fighting for operands with competing processors. This requires either heroic hardware ( e.g. 70% of the Cray C-90s processor logic was concerned with memory contention resolution) or a dramatic performance dropoff.
Seymour was fond of transparent gizmos too. He also used to say that disks were for people that couldn't afford enough memory - maybe this would have changed his mind....
And there's me thinking that the point was to make money out of selling all those books.
I have always (possibly mis)understood that most of Lloyds business is in underwriting, which is to say spreading the risk associated with high-value policies issued by an individual insurer. In the above context, the proposed scheme with OSRM looks eminently sensible - OSRM provides "indemnity services" which shield their customers from Open Source-related liability. OSRM's services are in turn made credible by virtue of the fact that their potential liability is underwritten by Lloyds. The overall effect is hopefully that: - Any attempted son-of-SCO is denied the opportunity to put the squeeze on thousands of individual companies, but instead has to defeat a well-funded organization whose only purpose is to thwart such attacks. - The likelihood that any such attack will be mounted is massively decreased because an attacker knows that OSRM and the underwriters will spend any amount of money to defeat the attack. The upshot it that the underwiters make a ton of money over time out of insuring against a contingency which is itself obviated by the very fact that they are insuring against it. Sweet.
Just because they aren't making low-end chipsets doesn't mean they won't be getting chipset revenue from the low end. As even the cheaper processors move to multi-core, shared L3, multi-CPU capable, etc, the complexities of producing an unlicensed chipset will become more and more prohibitive. Assuming AMD can be squeezed out (Intel seems to be making good progress there), then if you want to make a chipset for any kind of low-end PC, then you'll need an FSB license from Intel. They'll likely make more money out of the licensing than they would from the tedious business of designing/making/marketing/selling/supporting the chips themselves.