You don't have to. AltiVec allows fp and int operations to be performed on vec registers. You are allowed to take a value in an int register and replicate it to fill all the spots on a vec register, tho.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Any fool with a wad of money can buy Soviet nuclear weapons. Only an extremely advanced defense budget will build nanotech weapons.
As technology becomes more advanced, there will be more possibilities of ways to kill lots of people, but the only significant fact is that at least one weapon of mass destruction exists.
The idea of robots taking over the world is stupid. I doubt this guy has ever programmed, much less taken a course in psychology or how the mind works.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
My motherboard (an Apple G4) has a software-controlled L2, so once I wrote a mini-program to determine just what the cache does. It read 512k of memory over and over again (the cache is 1M, but it's no different). It turned out that setting the cache to 150MHz doubled or tripled speed, but increasing it all the way to 300MHz (overclocked) only made a 10% or so performance gain.
So, the main advantage of cache RAM is latency, not transfer rate.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Wow... I never guessed these processors were so $$$$-y. The G4, as I remember (I can't find pricing info any more... odd...) is about half as expensive or less, at half the clock rate.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
The idea of releasing generations of little-improved processors with higher clock rates to give the impression of progress is decadent. What can we do with a 1GHz PIII processor that heats like a furnace and looks like a brick that we couldn't do w/ a 500MHz PIII? Nothin'. But lower the power requirements and heat generated (really the same thing...), and mebbe overall reliability, and you could add uses.
I say, go Transmeta or IBM/Motorola. My PowerBook G3 gets quite a few hours to the charge, without reducing the clock speed as a non-copper "Coppermine" would. I can't wait until Transmeta PDAs come out.
And it's not like anything but the first stage of the pipeline is running at the full speed. Ooh, the new PIII emulates the x86 ISA at 1GHz...
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
The thought that your puny microbes could harm proud Europa is ridiculous. We Europans can whip your sorry Earthling ass any day, just try and take your probe a little bit closer.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Re:pretty, yet incomprehensible
on
MacOS X DP3
·
· Score: 1
Funny you mentioned it... I'm programming a framework for MacOS apps, and one of the original features is a drop-down menu when you hold the zoom-box down. Others include changing the default button as you type into a dialog box,...
But I dunno if I'll finish it w/ all this new stuff out.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
C++ has given features, like virtual base object initialization, that get added to code behind the programmer's back in the form of short code segments. The C++ definition defines the end functionality of these segments, but doesn't define a standard way to define them.
I am defining my own language as a school project; do you think a standard way to define code segments into keywords would be a good way to get OOP flexibility and extensibility? (as in:
The purpose of "private" and "protected" is to force programmers to use getter and setter functions instead of relying on specific bytes being in memory. This allows more flexibility if the writer of the "private" variable's class decides to change the data structure around. You can still look at the bytes in memory from your pointer, or just go into the header file and change it to "public". It's not a security measure, it's just supposed to encourage client programmers to write for forward-compatibility.
Clear?
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
To use the FireWire protocol doesn't require royalties, you need to pay Apple to use the FireWire brandname and logo. This doesn't count as part of the technology in my book.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Looking through this thread, I see that somewheres around 100% of the posters say something like "Oh no, not another MOSR post! This is total disinformation!" There's next to no discussion of open-source software, emulators, Bleem, or anything that this article was supposed to start discussion of. Instead, the crowd is getting hostile at Rob and Ryan, proposing conspiracy theories. If Rob knows what's good for himself at this point, he'll back away from mosr.com and stay away. Not only is Ryan Meader getting a few thousand additional hits, there are a few thousand people more who know he's a lying bastard. He'll be run out of his job. In the meantime, the small industry of parodying him is doing great...
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
With the recent announcement that all code to Windows will be open to the public, it will be necessary to make a few restrictions to make code readable to the "average programmer" (after all, we are Microsoft, creators of easy-to-use products). Please observe the following guidelines carefully:
All source files must be palindromic. If it is not possible to turn a file into a palindrome, it will be split into multiple files.
Whenever possible, letters must be changed to nUmb3r5 and v0w3ls wI11 b3 c4pI741z3d. This should enhance our already-strong popularity with clueless script kiddies.
File extensions are an obsolete way of identifying the language a source is written in, so we will be moving away from that strategy. Remove the last three characters from every file's name; a replacement method of identification will be specified later.
There are so many conflicting standards of data compression (or at least there's one, and it's not ours), so all source will be distributed in uncompressed monolithic blocks.
We have shown our support of Assembler through the multiple ways of declaring assembly blocks that the Microsoft compiler supports. Recode all inefficient blocks of code (addition, subtraction, etc.) into assembler using Microsoft-style #define blocks.
Thank you for your attention. The manual conversion of the source into a readable format may take time, delaying Windows 2000. The public will not be informed of this, and several more Golden Masters may be necessary. Also, distribution of code modified from its original form will have to be prohibited.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Wow! This will solve the continuing problem of all those crackers that set up wiretaps and undetectable splitters on monitor cables, stealing the monitor image in real time! The world's security troubles are over!
And such an elegant solution - I predict that when this is implemented, Intel will make hardly a dollar. I laud their philanthropic spirit.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
SCSI is busmaster-based: only one drive can use the bus at a time. FireWire is packet-based, so a number of drives that can't hit 50MB/s taken individually can share the bus and saturate it.
I don't know the details of the FireWire standard/protocol, but it seems that fast controllers and a complex protocol make designing the devices expensive. So, I'd say FireWire for everything fast, ADB for cheap+quickly designed crap.
Where is my mind? mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Slashdot Mirror
I didn't realize mot makes stuff like that - that's one small-ass mobo!
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
You don't have to. AltiVec allows fp and int operations to be performed on vec registers. You are allowed to take a value in an int register and replicate it to fill all the spots on a vec register, tho.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Check out this guy's e-mail address. Mebbe he doesn't get enough day-to-day contact w/ women...
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Any fool with a wad of money can buy Soviet nuclear weapons. Only an extremely advanced defense budget will build nanotech weapons.
As technology becomes more advanced, there will be more possibilities of ways to kill lots of people, but the only significant fact is that at least one weapon of mass destruction exists.
The idea of robots taking over the world is stupid. I doubt this guy has ever programmed, much less taken a course in psychology or how the mind works.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
that should be increasing it to 150MHz *from being turned off completely*, and a 10% gain over the 150MHz speed. Sorry...
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
My motherboard (an Apple G4) has a software-controlled L2, so once I wrote a mini-program to determine just what the cache does. It read 512k of memory over and over again (the cache is 1M, but it's no different). It turned out that setting the cache to 150MHz doubled or tripled speed, but increasing it all the way to 300MHz (overclocked) only made a 10% or so performance gain.
So, the main advantage of cache RAM is latency, not transfer rate.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Read this message aloud in a James Kirk / William Shatner voice.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Wow... I never guessed these processors were so $$$$-y. The G4, as I remember (I can't find pricing info any more... odd...) is about half as expensive or less, at half the clock rate.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Well this got rated as funny, and possibly rightly so. Reducing speed to "n times faster!" is pointless.
But my G4/450 has gotten 4+ megakeys/sec on RC5.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Spiner plays Conan O'Brian. Not much airtime, but OK...
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
This is fscking FLAMEBAIT?!? Well, serves you right - a bug in the Slashcode raised my karma by 4 points w/ this moderation!
I should really write a larger rant. People at sid=moderation take notice!
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
The idea of releasing generations of little-improved processors with higher clock rates to give the impression of progress is decadent. What can we do with a 1GHz PIII processor that heats like a furnace and looks like a brick that we couldn't do w/ a 500MHz PIII? Nothin'. But lower the power requirements and heat generated (really the same thing...), and mebbe overall reliability, and you could add uses.
I say, go Transmeta or IBM/Motorola. My PowerBook G3 gets quite a few hours to the charge, without reducing the clock speed as a non-copper "Coppermine" would. I can't wait until Transmeta PDAs come out.
And it's not like anything but the first stage of the pipeline is running at the full speed. Ooh, the new PIII emulates the x86 ISA at 1GHz...
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
That means that it walks on its external brain, right?
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
The thought that your puny microbes could harm proud Europa is ridiculous. We Europans can whip your sorry Earthling ass any day, just try and take your probe a little bit closer.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
heck, it's all pretty invalid!
Did you use > or < signs?
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
You forgot to initialize b.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Hiya rfob!
How's the band?
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Funny you mentioned it... ...
I'm programming a framework for MacOS apps, and one of the original features is a drop-down menu when you hold the zoom-box down. Others include changing the default button as you type into a dialog box,
But I dunno if I'll finish it w/ all this new stuff out.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
C++ has given features, like virtual base object initialization, that get added to code behind the programmer's back in the form of short code segments. The C++ definition defines the end functionality of these segments, but doesn't define a standard way to define them.
I am defining my own language as a school project; do you think a standard way to define code segments into keywords would be a good way to get OOP flexibility and extensibility? (as in:
keyword baseclass::virtual
[method=appendToBeginning, where=constructor]
(long *theVar, ~~~~) {
}
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
The purpose of "private" and "protected" is to force programmers to use getter and setter functions instead of relying on specific bytes being in memory. This allows more flexibility if the writer of the "private" variable's class decides to change the data structure around. You can still look at the bytes in memory from your pointer, or just go into the header file and change it to "public". It's not a security measure, it's just supposed to encourage client programmers to write for forward-compatibility.
Clear?
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
To use the FireWire protocol doesn't require royalties, you need to pay Apple to use the FireWire brandname and logo. This doesn't count as part of the technology in my book.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Looking through this thread, I see that somewheres around 100% of the posters say something like "Oh no, not another MOSR post! This is total disinformation!"
There's next to no discussion of open-source software, emulators, Bleem, or anything that this article was supposed to start discussion of. Instead, the crowd is getting hostile at Rob and Ryan, proposing conspiracy theories. If Rob knows what's good for himself at this point, he'll back away from mosr.com and stay away.
Not only is Ryan Meader getting a few thousand additional hits, there are a few thousand people more who know he's a lying bastard. He'll be run out of his job.
In the meantime, the small industry of parodying him is doing great...
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
With the recent announcement that all code to Windows will be open to the public, it will be necessary to make a few restrictions to make code readable to the "average programmer" (after all, we are Microsoft, creators of easy-to-use products).
Please observe the following guidelines carefully:
All source files must be palindromic. If it is not possible to turn a file into a palindrome, it will be split into multiple files.
Whenever possible, letters must be changed to nUmb3r5 and v0w3ls wI11 b3 c4pI741z3d. This should enhance our already-strong popularity with clueless script kiddies.
File extensions are an obsolete way of identifying the language a source is written in, so we will be moving away from that strategy. Remove the last three characters from every file's name; a replacement method of identification will be specified later.
There are so many conflicting standards of data compression (or at least there's one, and it's not ours), so all source will be distributed in uncompressed monolithic blocks.
We have shown our support of Assembler through the multiple ways of declaring assembly blocks that the Microsoft compiler supports. Recode all inefficient blocks of code (addition, subtraction, etc.) into assembler using Microsoft-style #define blocks.
Thank you for your attention. The manual conversion of the source into a readable format may take time, delaying Windows 2000. The public will not be informed of this, and several more Golden Masters may be necessary. Also, distribution of code modified from its original form will have to be prohibited.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
Wow! This will solve the continuing problem of all those crackers that set up wiretaps and undetectable splitters on monitor cables, stealing the monitor image in real time! The world's security troubles are over!
And such an elegant solution - I predict that when this is implemented, Intel will make hardly a dollar. I laud their philanthropic spirit.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0
SCSI is busmaster-based: only one drive can use the bus at a time. FireWire is packet-based, so a number of drives that can't hit 50MB/s taken individually can share the bus and saturate it.
I don't know the details of the FireWire standard/protocol, but it seems that fast controllers and a complex protocol make designing the devices expensive. So, I'd say FireWire for everything fast, ADB for cheap+quickly designed crap.
Where is my mind?
mfspr r3, pc / lvxl v0, 0, r3 / li r0, 16 / stvxl v0, r3, r0