More like 20 years ago. The other "RISC" chips started to drop off the map in the late 1990s. For general purpose performance computing, we're now left with x86, SPARC, and POWER.
Hahahaha... oh wait, you're serious.Ok, so what high performance, low-cost, and power efficient processor should we all migrate to then? And will you pay to have all my software ported over to this new ISA?
What are you talking about? Carriers have an offense of 1, a defense of 9, and 4 hit points (1/9/4)! About the only thing that has any hope of destroying one is a submarine (10/2/3) or stealth bomber (14/5/2).
It's lesson for all businesses: adapt or become irrelevant. Look at IBM. They used to make tabulating machines. Now they make most of their money selling services. Some industries change at a glacial pace (e.g. oil, cement, Christmas trees) so companies entrenched here can take their time adapting to new realities whereas other industries change pace almost daily (e.g. fashion), so companies in these industries also need to adapt very quickly (e.g. Coach, LV, etc.).
That makes absolutely no sense. You would consider a 32-bit Pentium 4 505 as a "True Pentium" and a 64-bit Pentium 4 506 as something else even though they are both based on Prescott microarchitecture but the 505 processor has 64-bit capabilities disabled???
I have an AMD 1090T (6 cores @ 3.2 GHz) that I've run FreeBSD 8.2 and Debian 7 on. I run Povray 3.7, which is multi-threaded (compared to the prior version which was not), on this machine and was testing out OSes. Using the latest gcc version for each OS (4.6), it turns out running on FreeBSD is about 15% faster than on Debian running the standard benchmark:
FreeBSD 8.2, gcc 4.6, -march=barcelona
Render Time:
Photon Time: 0 hours 0 minutes 2 seconds (2.390 seconds)
using 9 thread(s) with 2.763 CPU-seconds total
Radiosity Time: No radiosity
Trace Time: 0 hours 3 minutes 10 seconds (190.466 seconds)
using 6 thread(s) with 1113.568 CPU-seconds total
Debian 7.0, gcc 4.6.1, -march=barcelona
Render Time:
Photon Time: 0 hours 0 minutes 2 seconds (2.277 seconds)
using 9 thread(s) with 2.648 CPU-seconds total
Radiosity Time: No radiosity
Trace Time: 0 hours 3 minutes 38 seconds (218.326 seconds)
using 6 thread(s) with 1277.363 CPU-seconds total
You're kidding right? I've tried this thing on the desktop, and it sucks. Give me a mouse any day - it's much more precise, especially for doing simple things like click and drag.
Even your current phone if you can install Cyanogenmod on it. Android 2.2 and greater have tethering support built in already so no need for a separate app.
real mode, I/O instructions, etc. can't possibly take up that much of the transistor budget. Especially not when they can cram several cores + 30 MB of cache on one die.
x86 isn't RISC if they decode microcode into smaller RISC like operations; an internal RISC. The outside instructions must be RISC; how they pull those off internally is not really part of it. Its a black box.
You do realize that even IBM's POWER chips (the final bastion of "RISC") decode instructions into uops too, right? So, are you willing to concede that POWER isn't RISC?
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Dammit, meant 15 years...
More like 20 years ago. The other "RISC" chips started to drop off the map in the late 1990s. For general purpose performance computing, we're now left with x86, SPARC, and POWER.
Depends on the chip. Sandy Bridge, maybe. Atom, probably not.
Hahahaha... oh wait, you're serious.Ok, so what high performance, low-cost, and power efficient processor should we all migrate to then? And will you pay to have all my software ported over to this new ISA?
I use them, but I only have one address anyway.
What are you talking about? Carriers have an offense of 1, a defense of 9, and 4 hit points (1/9/4)! About the only thing that has any hope of destroying one is a submarine (10/2/3) or stealth bomber (14/5/2).
It's lesson for all businesses: adapt or become irrelevant. Look at IBM. They used to make tabulating machines. Now they make most of their money selling services. Some industries change at a glacial pace (e.g. oil, cement, Christmas trees) so companies entrenched here can take their time adapting to new realities whereas other industries change pace almost daily (e.g. fashion), so companies in these industries also need to adapt very quickly (e.g. Coach, LV, etc.).
Atom has 16 general purpose registers as well as 16 xmm registers since it's a n x86_64 CPU.
That will just shift unemployable people to other majors!
Well, it can't possibly be any worse than Intel's current naming scheme!
That makes absolutely no sense. You would consider a 32-bit Pentium 4 505 as a "True Pentium" and a 64-bit Pentium 4 506 as something else even though they are both based on Prescott microarchitecture but the 505 processor has 64-bit capabilities disabled???
PT Barnum has him beat.
Well, that's not a very good description. What exactly was he like???
I bet that's where they're training their Sardaukar! Where else can you do that but in deserts?
No.
Next question?
Could you elaborate?
I have an AMD 1090T (6 cores @ 3.2 GHz) that I've run FreeBSD 8.2 and Debian 7 on. I run Povray 3.7, which is multi-threaded (compared to the prior version which was not), on this machine and was testing out OSes. Using the latest gcc version for each OS (4.6), it turns out running on FreeBSD is about 15% faster than on Debian running the standard benchmark:
FreeBSD 8.2, gcc 4.6, -march=barcelona
Render Time:
Photon Time: 0 hours 0 minutes 2 seconds (2.390 seconds)
using 9 thread(s) with 2.763 CPU-seconds total
Radiosity Time: No radiosity
Trace Time: 0 hours 3 minutes 10 seconds (190.466 seconds)
using 6 thread(s) with 1113.568 CPU-seconds total
Debian 7.0, gcc 4.6.1, -march=barcelona
Render Time:
Photon Time: 0 hours 0 minutes 2 seconds (2.277 seconds)
using 9 thread(s) with 2.648 CPU-seconds total
Radiosity Time: No radiosity
Trace Time: 0 hours 3 minutes 38 seconds (218.326 seconds)
using 6 thread(s) with 1277.363 CPU-seconds total
You're kidding right? I've tried this thing on the desktop, and it sucks. Give me a mouse any day - it's much more precise, especially for doing simple things like click and drag.
How rootable is the Kindle Fire? It's trivially easy with the Nook Color; that's why I bought one.
Why would they reverse engineer an Alpha chip in order tp make aIPS chip? If I were them, I'd one of the OpenSPARC cores.
Against other open cores such as the SPARC cores?
Even your current phone if you can install Cyanogenmod on it. Android 2.2 and greater have tethering support built in already so no need for a separate app.
Ben Collins, is that you? Some say he has a full tattoo of his face on his face..
How can you even call it fan fiction when there wasn't any nudity involved?
real mode, I/O instructions, etc. can't possibly take up that much of the transistor budget. Especially not when they can cram several cores + 30 MB of cache on one die.
x86 isn't RISC if they decode microcode into smaller RISC like operations; an internal RISC. The outside instructions must be RISC; how they pull those off internally is not really part of it. Its a black box.
You do realize that even IBM's POWER chips (the final bastion of "RISC") decode instructions into uops too, right? So, are you willing to concede that POWER isn't RISC?