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CtrlPhreak writes: "Anandtech has posted a review of an affordable AMD 760 based motherboard, the Tyan Tiger MP. It's basically the Tyan Thunder K7 without all the integration. For $220, it's a great deal. It has the exact same performance as the Thunder, and it is tested to run fine with those cheap and fast 1ghz durons. They say Tyan is putting out this board to compete with other offerings of a cheap 760 platform, we can only hope."

A number of people wrote in with the news that Intel released the 2 Ghz chip. The Tech-Report article points out a couple interesting meta-ideas - this is Intel's chance to retake the performance crown from AMD, as well as being one of those round numbers that makes people feel warm and fuzzy. I'm sure there's going to be gobs of benchmarks today - post 'em in the comments as you find 'em.

fvdl writes: "Last week, a port of NetBSD to the x86-64 (tm) architecture was committed to the NetBSD CVS repository. The x86-64 is AMD's upcoming 64bit line of CPUs. For now, it is only known to work on the Virtutech simulator, since no x86-64 hardware is available yet. In this environment, it runs multi-user. NetBSD/x86_64 is the 44th architecture that NetBSD runs on (12 different families of CPUs). The porting was done by Frank van der Linden of Wasabi Systems, with kind support from AMD, who provided the simulator and fast machines on which ro run it. The Wasabi press release is here. For more information on the x86-64, see of course AMD's website and x86-64.org"

Mostly Monkey was the first to write to us regarding a new article on Tom's Hardware. The article is about the launch by Nvidia of "...nForce, its integrated graphics, audio, Northbridge, and Southbridge chipset, also referred to as Crush." The implication is that Nvidia is setting itself up to move past the graphics/audio market and get into competing with Intel in the full on chip market. What with AMD's recent success, that doesn't sound so unlikely.

km790816 writes: "I was just reading an article in the EETimes about the possible war over the technology to replace the PCI bus. Intel has their 3GIO. (Can't find any info on Intel's site.) AMD has their HyperTransport. There has been some talk about HyperTransport going into the XBox. I hope they can agree on a bus. I don't want another bus standard war. So when can I get a fully optical bus on my PC?" Now that's what I'd like: cheap transceivers on every card and device, and short lengths of fiber connecting them up. Bye bye to SCSI, IDE, USB, Firewire ...

km790816 writes: "I was just reading an article in the EETimes about the possible war over the technology to replace the PCI bus. Intel has their 3GIO. (Can't find any info on Intel's site.) AMD has their HyperTransport. There has been some talk about HyperTransport going into the XBox. I hope they can agree on a bus. I don't want another bus standard war. So when can I get a fully optical bus on my PC?" Now that's what I'd like: cheap transceivers on every card and device, and short lengths of fiber connecting them up. Bye bye to SCSI, IDE, USB, Firewire ...

TWX_the_Linux_Zealot asks: "Recently I realized that I hadn't heard anything new regarding AMD processors and SMP, which had occasionally been mentioned on various tech news sites. There is no mention of such chipsets on AMD's Website, or on any of the motherboard manufacturers that I would have expected at least a press release from, such as ASUS, Gigabyte, or Abit Does anyone know what's going on?"

HiyaPower writes: "AMD announced today that it has started shipment of its mobile Duron line of processors. While these were supposed to have made it out the gate in 00Q4, it is nice to see that they have finally appeared. Designed around a 1.6V VCore, these processors have a power dissipation of roughly 25W at 600 Mhz, and 29W at 700 Mhz according to the tech specs. Pricing is aggressive as might be expected in this environment. The AMD mobile line has been a good one since the K6-III+ processors. Hopefully, these Durons will live up to the tradition." I bet this release is a spur to the folks at both Intel and Transmeta -- isn't it nice to watch one-upmanship at work sometimes?

HiyaPower writes: "AMD announced today that it has started shipment of its mobile Duron line of processors. While these were supposed to have made it out the gate in 00Q4, it is nice to see that they have finally appeared. Designed around a 1.6V VCore, these processors have a power dissipation of roughly 25W at 600 Mhz, and 29W at 700 Mhz according to the tech specs. Pricing is aggressive as might be expected in this environment. The AMD mobile line has been a good one since the K6-III+ processors. Hopefully, these Durons will live up to the tradition." I bet this release is a spur to the folks at both Intel and Transmeta -- isn't it nice to watch one-upmanship at work sometimes?

An unnamed correspondent writes: "The Tech Report has posted a review of AMD's 760 chipset. This is the one that includes a 133 MHz DDR bus, with support for 133 MHz DDR (a.k.a. PC2100) SDRAM. Benchmarks were done using a 1.2 GHz Athlon, and include everything from memory bandwidth tests to a variety of Quake III scores; they even attempted Linux tests, but Linux and the 760 wouldn't play nice." For another point of view, Fr0child writes "Today is the day that AMD officially announces their DDR SDRAM supporting chipset, the AMD 760. They promise "Increasing Memory Data Rate by Up to 100 Percent," which is quite promising to say the least. Of course, who would sit back and believe what a manufacturer says without verification? Anandtech has taken an in depth look at all the performance and features of the AMD 760. Looks like the combination of DDR + Athlon easily topples the RDRAM + Intel platforms out there."

And on the other, other hand, romeomustdie writes: "According to this [Sharky Extreme] piece, AMD is finally debuting the 760 DDR capable chipset, which is, for the most part, an evolutionary step up from the 750 chipset which has been out for the past year. Boasting a faster system bus, support for DDR memory, and a brand new South Bridge, AMD has set themselves up to not only surpass their first-generation offering, but also the current performance Athlon chipset, VIA's KT133. DDR is finally here to stay."

Malk-a-mite was one of the first to e-mail about the announcement from AMD concerning their demonstration of a Dual Athlon workstation. It is using their "AMD-760 MP chipset, and next-generation Double Data Rate (DDR) memory. "Update: 10/11 06:26 PM by H : My mistake. This was a dupe article - the older story went up yesterday - Microprocessor Forum.

Malk-a-mite was one of the first to e-mail about the announcement from AMD concerning their demonstration of a Dual Athlon workstation. It is using their "AMD-760 MP chipset, and next-generation Double Data Rate (DDR) memory. "Update: 10/11 06:26 PM by H : My mistake. This was a dupe article - the older story went up yesterday - Microprocessor Forum.

Manufacturers are strutting their stuff at the Microprocessor Forum. Some of the rollouts: Turmoil writes "AMD has demonstrated working SMP. http://www.amd.com/news/prodpr/20165.html" hol writes: "German news site Heise.de reports that a German startup named PACT surprise-announced their processor design at the Microprocessor Forum in San Jose. Apparently this thing is a 128 cpu parallel computing deal which has its roots in the programmable gate array world." infodragon writes "All Linux Devices.com is running a pretty cool article about an X86 chip running on 1 AA battery. They demonstrated it by playing a VCD movie. They also say that mp3s can be decoded/played on it."

Christopher Cashell asks: "Does anyone know what is going on with AMD and support for multiple processors (SMP)? I love AMD CPU's, but I've also come to love dual processor machines. Ever since the Athlon was still an 'in progress' chip code named the K7, and AMD stated that the CPU would support SMP, I've been drooling over the idea. Now, especially, I would love to have a dual CPU Duron box. Has anyone heard anything? I couldn't find anything on AMD's site about it. As I understand it, the CPU supports SMP, so it's just a chipset issue, right? Is AMD working on a SMP chipset? And if not, are any of the other big mobo/chipset manufacturers considering it?"

rubyred writes "AMD is at it again today and has added to their Duron line-up and released the 750MHz, which performed well against the Celerons from Intel. There are reviews on Sharky's and Anand's. Also Matrox, who we've not heard from in while has let loose a new .18micron based G450 chip, which is set for the corporate world. The 2D performance looks really good but the gaming... well it's another Matrox product. Still their Linux drivers might get better this time around. Again the same two sites have previews of the card."

KuRL writes "C|Net is reporting that Intel has begun to recall their 1.13-GHz chips, which had the best clock speed on the market, due to a glitch that caused the chip "to malfunction in laboratory tests under certain conditions." Yes, it was only that specific. It is quite clear that Intel rushed this chip out upon hearing that AMD would be releasing a 1.1-GHz chip of their own."

AMD has released a manual in PDF format to allow software developers to migrate their code to its 64-bit Hammer microprocessor platform. The PDF document is here and Sandpile Web site gives excellent explanatory material of the content of the PDF file. Surprisingly, Sun supports the Sledge Hammer. Article can be found here

maniack writes "The AMD Duron, the "Celeron-killer", has finally been released and lives up to the hype. According to these reviews from Ace's Hardware, Gamer's depot, Anandtech, and Tom's Hardware, the Duron thrashes the Celeron clock for clock and even hangs with the P3 in a lot of the benchmarks. Looks like AMD has another winner in the value market to go along with the Athlon."

Devil Ducky writes: "AMD announced that they will release the Duron sometime in mid June, instead of last April. The Duron is intended to compete on price with the fabled Intel Celeron. Duron will include 128KB of primary and 64KB of integrated cache, meanwhile Athlons contain 128KB primary and no integrated cache. When released it will be available in 600, 650, and 700MHz with plans for 750MHz soon. The story even makes some quick comments on the names Celeron and Duron."

smeng58 writes: "If haven't got your Athlon yet, you may have to wait. This article found on CNNfn states AMD has sold out their production of the Athlon for the second quarter. Looks like AMD has capacity problems, or a lot of people are choosing AMD over Intel."

spudwiser writes: "AMD has a press release on their Web page concerning shipment of the 900, 950, and 1000MHz Athlon processors. Also included are times for the live satellite interview with the CEO and VP of AMD." Check out some of the benchmarking info about the new chips as well. I wonder how Andy Grove ^[?] is feeling today.

spudwiser writes: "AMD has a press release on their Web page concerning shipment of the 900, 950, and 1000MHz Athlon processors. Also included are times for the live satellite interview with the CEO and VP of AMD." Check out some of the benchmarking info about the new chips as well. I wonder how Andy Grove ^[?] is feeling today.

chamega writes "AMD demonstrated a 1.1 GHz processor Monday without any special cooling techniques. The processor is said to use "high-performance on-die Level 2 (L2) cache," whatever that means. " Perhaps, unlike Intel, they'll actually be able to /ship/ their high-end chips when they say they will.

MatriXOracle writes "AMD seems to be on fire lately. According to this C|Net article, HP will be including K6-2's in new portable models, and is considering the Athlon for desktop use. Meanwhile, Gateway is blaming its disappointing earnings on supply (or lack thereof) of Intel chips, and will start selling systems with AMD chips very soon. Finally, an 800MHz Athlon is being released today. "

MatriXOracle writes "AMD seems to be on fire lately. According to this C|Net article, HP will be including K6-2's in new portable models, and is considering the Athlon for desktop use. Meanwhile, Gateway is blaming its disappointing earnings on supply (or lack thereof) of Intel chips, and will start selling systems with AMD chips very soon. Finally, an 800MHz Athlon is being released today. "

epoh writes "AMD has finally released their new (fast, affordable, slick) line of notebook processors. They are supposed to blow the Pentiums out of the water. Check out the full story. Yum. I want one. " It's a shame the K7 runs so hot. I'm sure it's just a matter of time, though.

epoh writes "AMD has finally released their new (fast, affordable, slick) line of notebook processors. They are supposed to blow the Pentiums out of the water. Check out the full story. Yum. I want one. " It's a shame the K7 runs so hot. I'm sure it's just a matter of time, though.

I recently read Po Bronson's sophomore effort, The First 20 Million is Always the Hardest (TF20MIATH), and had a few gripes about it. Click below to read mine, and to share your own critiques - compliments - comments - ramblings about the book. The First 20 Million is Always the Hardest author Po Bronson pages 237 publisher Random House rating 4/10 reviewer Jeff "hemos" Bates ISBN summary An attempt at writing a fictional Silicon Valley Story

Several months ago I read Bronson's latest book, The Nudist on the Late Shift . It was good - not quite Microserfs , but definitely worth the time I spent reading it.

So, with that in mind, and having heard a little bit about his other material, I kept an eye open for Bombardiers or TF20MIATH, and eagerly fell upon the first of the two that came to me.

Most of TF20MIATH's main characters are engineers, "iron-men" in the parlance of the book, who work for a research facility that's supposed to attract only the best and brightest. You aren't paid a lot of money to work there. You do it for the love of the work, and to prove you're an Iron Man, or "uber-mann." However, the work done at the lab does have commercial properties, and the lab is funded by commercial companies. The largest sponsoring company, much like AMD, is trying to compete with Intel. This fact creates some of the book's conflict.

The lead character, Andy, joins the lab after quitting his job at that psuedo-AMD company, but his desires to work at The Lab are (major summarization here) soon quenched by the other main character, Francis Benoit, who is constantly seeking to prove that he is the Super-Iron-Man of them all.

One of the ongoing battles of the book is between the powerful "big iron machines" the lab is known for developing and the evolving world of thin client, networked machines. Bronson's treatment of this conflict, coupled with the somewhat Messianic light that these cheap Internetworked computers will bring to the world writ large, is the books's central thought. It's a good thought, and I think it's one that has some validity. That is, as the world's population gets more education, and computers spread, I think things will get better. So does Bronson. And he says this again and again, in slightly different words each time.

The story itself, which in a way is a story about the world of the suits meeting the world of engineers, with the obvious party losing, falls short. The introduction of a female bit player who becomes Andy's girlfriend is contrived. Problems develop in the relationship, and we never hear if they are resolved or not. The disapperance of a fairly major character (Salman) is explained poorly, and is never mentioned again in any fashion.

Summary time: The story involves jealousy and politicking amongst the Iron Men Engineers while they as a caste also do battle with the Universe of the Suits. The main character must resolve issues with his girlfriend. All characters wrestle with problems, includings things like whether or not they will be fired, whether or not they can code something, and whether or not they can afford to buy better food.

It's not a bad book, it's just that unless this type of writing is your favorite, there are better books to read. There's a good book inside this one, but the problem is that the good book is only about one-third the length of the published version. Bronson is an author who seems to constantly be trying to figure out how to best tell a Silicon Valley story. In Nudist he did it succesfully, but in TF20MIATH he didn't. My recommendation: You won't regret reading this, but there's better stuff around..

You can buy TF20MIATH at Amazon.

Since the NDA was lifted early this morning, several sites have released reviews of AMD's new Athlon chip (coming in 500, 550, 600, and 650MHz versions). The first was Bill Henning's CPUReview site. He reviewed the Athlon 600 and has several nice things to say about it. Next up is The Upgrade Center's review, and two more submitted by kimmo, the first at Ace's Hardware, and the second at AGN Hardware. Next, Magnetism submitted a link to Tom's review. Finally, as submitted by pmmay, the ZDNet review. To finish, an article at the SJ Mercury that discusses AMD's strategy for the chip market (thanks to Greg Miller for that one). Update: 08/09 12:31 by J : Thanks to The Evil Dwarf from Hell for links to the AMD Benchmark Page, which even has SPECint and SPECfp scores, and to an anonymous reader for the Ars Technica review.

nemoest writes "Intel is planning on slashing the price on Pentium III's by as much as 15% on Sunday. After which, they also plan to also cut the prices on the Xeon, Pentium II and III, and Celron on August 22nd. It looks like they want to try to run AMD even further into the ground with convenient price slashing just as they gear up to release the Athlon. You can read the complete story here on Cnet's news.com. "

About one billion of you wrote with the news that AMD took a operating loss this past quarter, and the COO and heir apparent to the CEO quit. In related news, IDT has declared that they quitting the x86 clone business. Wow-despite lower then expected earnings, Intel has to be pleased by this turn of events.

|jasper| writes "on AMD's home page they now have Athlon processors benchmarked against P3 550.. Probably still biased.. but its something " They claim that integer performance is slightly faster, while floating point and 3d is significantly faster (at the same clock speed)

Sir-Techlot writes "AMDs wed site has a page saying that the Athlon will be shipping today (6/23/99). Tells a bit of info we already know also. "

Haven writes "News for all you overclockers out there! Get the facts from your peers at www.overclockers.com. You can now see which processors to purchase and how much luck other people are having. It includes everything from the PIII to the K6-2. "

Several folks wrote in to announce that AMD has officially announced the K6-III. Thats a link to the official product release if you're interesting in reading it direct from the horse's mouth.

PianoMan8 writes "AMD has released thier K6-2's at 366, 380, and 400Mhz. The press release is here. Also, it appears that VIA and ALi will be making chipsets for the K7." Oh man that is cool. The 400MHz K6-2 has a faster core than other K6-2 chips. I can't wait for the K6-3 to come out so I can pop it in my K6-2 machine. Go AMD! Update: Diablo sent us a link to a Tom's Hardware Guide article which discusses these chips in a fair amount of depth.

PianoMan8 writes "AMD has released thier K6-2's at 366, 380, and 400Mhz. The press release is here. Also, it appears that VIA and ALi will be making chipsets for the K7." Oh man that is cool. The 400MHz K6-2 has a faster core than other K6-2 chips. I can't wait for the K6-3 to come out so I can pop it in my K6-2 machine. Go AMD! Update: Diablo sent us a link to a Tom's Hardware Guide article which discusses these chips in a fair amount of depth.

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.

bOnEs writes " Led by substantial growth in sales of AMD-K6® -2 processors with 3DNow!(TM) technology, AMD today reported record sales of $685,927,000 during its third quarter, ended September 27, 1998, which resulted in net income of $1,006,000, or $0.01 per share. Nice to see AMD making a serious run at Intel. I have 2 K6-2 300 processors, 1 in my Linux box, and they run superbly. Looking forward to the K7. "

jb goode writes "This is a story about KryoTech's thermally accelerated 450MHz Cool K6-2 PC, running the chess program ``Rebel'' from Schroder BV in the Netherlands, defeated world #2 ranked grandmaster Viswanathan (``Vishy'') Anand by a score of 5 to 3. The match consisted of four blitz games, two semi-blitz games, and two tournament games played July 21-23 on the island of Ischia, Italy. Update I don't have a working link to this story apparently. Anyone got one?"

arp writes "Motorola and AMD plan to announce Monday a technology swap intended to speed development of microprocessors made with copper, an important alternative to the aluminum long used in the brains of computers and other electronics. "
Very cool. With IBM's work in this area, it is good to see this start to enter into the real world.

AMD unveiled the K6-2, saying that it will run 3d graphics as fast as the P2. This is out a full year before Katmai, garnering AMD some kudos. However, the problem of having no software written for it before fall exists, somewhat raining on the parade. But AMD is still releasing a 350 mhz version during the fall.

BadlandZ writes "I saw some stuff on Slashdot about the K6-3D, but I wasn't sure if you had mentioned the fact that it is due out very soon now. Looks like AMD has scheduled it for May 28th! Cool! Check: here The long awaited P2 contender may be within reach now. Looks like they update that URL somewhat frequently. "

AMD will be renaming the chip formerly known as the "K6 3D" to be the "K6-2". The chip will use the 100MHz bus and likely be announced May 28th (coinciding with the Linux Expo).
The company also announced they are naming the 21 MMX-like instructions in the K6-2 "3DNow!". The instructions will be supported by Cyrix and IDT.