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GaAs and GaN are very much already being worked on for fast-switch PHEMTs. And yes, there's a 2DEG in those too.

Here for example: Gold-free 200mm CMOS compatible GaN-on-Si power devices

Here is a more decent description from imec.

Something thats been in development for even 5 years and doesn't show any concrete signs of success should at least have alternatives developed for it. After 5 years if you still can't say for certain if its ever going to work, you definitely need to start looking in different directions.

You are misinformed. On our Alpha development machines, working 22 nm devices were already manufactured last year. (source) We are shipping the first commercial EUV lithography machines in the coming year (source, source) A problem for the chip manufacturers is that the capacity on the alpha machines is rather low and needs to be shared among competitors.

Yeah, I think the OP has a little intuition of the relatively common situation where an ailing older technology's flaws are somewhat obvious and well publicized for years and years, but the older technology staggers on far far longer than expected. For both the reason that EUV has been slow to mature, and that 193nm has been surprisingly resilient. It's wrong to conclude that EUV will never be practical, just that one should be very careful about declaring when it is necessary.

A similar situation is going on with the broader issue discussed here-- the eventual replacement of CMOS with some other technology. People are eager to declare the death of CMOS and the need for diamond substrates or nanotubes or whatever, but CMOS will stagger along much longer than the advocates of the new technologies hope because it is easier to extend CMOS than it is to make something truly different more mature and practical.

I deal with EUV lithography for a living. Not at Intel, but at ASML, the world's largest supplier of lithography machines and the only one that has actually manufactured working EUV lithography tools.

Something thats been in development for even 5 years and doesn't show any concrete signs of success should at least have alternatives developed for it. After 5 years if you still can't say for certain if its ever going to work, you definitely need to start looking in different directions.

You are misinformed. On our Alpha development machines, working 22 nm devices were already manufactured last year. (source) We are shipping the first commercial EUV lithography machines in the coming year (source, source) A problem for the chip manufacturers is that the capacity on the alpha machines is rather low and needs to be shared among competitors.

There is a temporary alternative; it is called double patterning (and triple patterning, etcetera). The first problem is that you need twice (thrice) as many process steps for the small features, and also proportionally more lithography machines that are not exactly cheap. The second problem is that double patterning imposes tough restrictions on the chip design; basically you can only make chips that consist mostly of repeating simple patterns. That is doable for memory chips, but much less so for CPUs. Moreover, if you want to continue Moore's law that way, the manufacturing cost will increase exponentially, so this is not a long-term viable alternative.

You can bet that the semiconductor manufacturers have looked for alternatives. But those don't exist, at least not viable ones.

Is it coincidence that earlier this month there was a press release from IMEC regarding the issues of massively scaling up computational power ("exascaling")?
Press blurb can be found here.
Killer application would be "space weather prediction".

From the article:

The new circuitry topology allows the ILFD to divide by three as well as two.

This tiny change has huge ramifications. A circuit design that can divide by two or three can, for instance, divide 9,999 clock pulses by two, and the 10,000th by 3, giving an average of 2.0001, which could be the frequency at which the cell phone is trying to communicate. Should the phone need to communicate at 2.0002 gigahertz, the ILFD could divide 9,998 clock pulses by two, and the 9,999th and 10,000th by three, yielding an average of 2.0002. By varying how many clock pulses are divided by two or by three, any frequency can be selected, making the power-saving ILFD method viable for the first time.

What does this actually mean? To me it sounds like the writer has no clue as to what they are writing about.

Can somebody please correct me here?

From the above, divide by 3 has little value. Divide by 4 would do just the same. Example: If you can vary how many clock pulses are divided by 2 or 4 (i.e. 2x2), you can get any frequency you want. There is no need for divide by 3.

Divide by 3, however is useful in an oscillator for a totally different reason:

If you can only divide by 2, then your frequency choices are 2,4,8,16 etc, while adding 3 as a factor gives you 2,3,4,6,8,9,10 etc.

This is outlined in detailed in a 4 year old article here:

p. 23: A wide band Modulo-3 ILFD

It states that in inverter based amplifier gives low power.

Hui's chip is described here. (By Hui)

Please give me feedback on this.

Almost every reply seems to think that the only chips in existence are digital. If you are thinking of a digital design then, as the others said, FPGAs are the way to go - certainly for prototyping.

If you need an analogue device or want chip scale packaging of your device, then an asic would be more appropriate. It is possible that FPGAs are available in very small packages but I'm not very up on that.

If you're in Europe, the Europractice scheme provides access to Multi-Project Wafer (MPW) runs to reduce overall fabrication costs. They also provide the software and design kits that allow you to make your designs.

My price breakdown for a 10sqmm chip in the AMS C35B4 process (0.35um, 4 metal, 2 poly, high res) with 20 devices in CSOIC28 packages:

Full Europractice membership (annual): €900
Cadence IC package single license: €1800
Cadence IC package maintenance (might not be applicable for the first year): €1150
10sqmm of AMS C35B4 silicon @ €720/sqmm: €7200
20 packages @ €52/package: €1040

Total: €10,940 or €12,090

Non of the prices include any local taxes.

They also do low volume production, but I don't know anything about the pricing.

So how to bring that down? You could save €1800/€2950 on software by using free alternatives such as on this

Don't be influenced by your opinions of current design processes. We use a 0.35um process all the time. It's perfectly adequate for what we want to do - in fact in many ways it is better than smaller processes for us. You could save a lot of money by going to a coarser process such as the AMIS 0.7um (2 metal, 1 poly) at €360/sqmm or the AMIS 0.5um (3 metal, 1 poly) at €420/sqmm - both with a smaller minimum size at 8sqmm. Silicon cost would then be €2880 or €3360 compared to €7200. 8sqmm is quite a lot really.

Ultimately, you need to decide what you need. If you need analogue circuitry but don't need linear capacitors, go for the cheapest process. If you do need linear caps, you'll have to use a process with 2 poly layers. If you want digital as well, go for something finer and with more metal layers

I visited an experimental fab here (at IMEC) a while ago and there also was a great deal of yellow light in some places. As far as I can remember, it has something to do with the processing. Some methods involve 'developing' photoresist layers on wafers, like developing a photographic film, and this process is insensitive to yellow light -- just like good ol' black & white photographs were insensitive to the typical red light in dark rooms.
However, I recently visited a new cleanroom in the same fab, made for experimenting with 30mm wafers. Next to the fact that all the tiny rooms from the older fab were replaced by one large 'ballroom', all the light was simply white. I guess the new process is insensitive to visible wavelengths.
So maybe they just colored the photograph to evoke the typical cleanroom-look of a decade ago. Or the photograph is simply from an old fab.

No, they are a completely different semiconductor material which is doped with something else. I once did an internship at a semiconductor lab (IMEC) where InP devices were developed (back then: 100 or so GHz). I recall they are VERY fragile (as opposed to Si which you can really kick around). Anyway, when the smallest features on chip are getting smaller, all processing (making masks etc.) needs to be more precise too, which will increase the cost. I think this is more important than the cost of the materials.

The sensor for this camera was made by the Belgian company FillFactory, a recent spin-off of the micro-electronics research facility IMEC

They have a range of sensor, but they can also design a sensor from scratch to your specifications

First off, to see at a greater resolution I guess you also need more nerves from your eyes to your brain, and that might be tricky? But I don't know about that.. a zoom would have been nice ;)
Anyway... for information of the resolution, check http://www.imec.be/bo/ccd/evs.html. Or, taken from the web site: Resolution: #pixels: 120M clones; pixel pitch: 2-3 m; focal plane size: 3 cm.

It's A LOT more that 3500! Just take a look at http://www.imec.be/bo/ccd/evs.html! But it is true that the brain fills in information missing.

It's not only IBM that's working on this kind of technology: IMEC, the largest independent micro-electronics R&D center in Europe is also working on this kind of NVM: Ferroelectric memories

I gotta admit, I haven't read the article yet, but plain jane silk certainly isn't the most durable substance on earth.

Read the article. This is a low-K dielectric with the trade name "SILK" (probably an acronym).