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How Much Smaller Can Chips Go?
nk497 writes "To see one of the 32nm transistors on an Intel chip, you would need to enlarge the processor to beyond the size of a house. Such extreme scales have led some to wonder how much smaller Intel can take things and how long Moore's law will hold out. While Intel has overcome issues such as leaky gates, it faces new challenges. For the 22nm process, Intel faces the problem of 'dark silicon,' where the chip doesn't have enough power available to take advantage of all those transistors. Using the power budget of a 45nm chip, if the processor remains the same size only a quarter of the silicon is exploitable at 22nm, and only a tenth is usable at 11nm. There's also the issue of manufacturing. Today's chips are printed using deep ultraviolet lithography, but it's almost reached the point where it's physically impossible to print lines any thinner. Diffraction means the lines become blurred and fuzzy as the manufacturing processes become smaller, potentially causing transistors to fail. By the time 16nm chips arrive, manufacturers will have to move to extreme ultraviolet lithography — which Intel has spent 13 years and hundreds of millions trying to develop, without success."
Make them bigger. More space to put stuff on them then anyway. Tostito's Restaurant style tortilla chips can fit much more guacamole and salsa on them than their bite size chips. Bigger is better when it comes to chips.
They're going to hit atomic scale transistors fairly soon from what I can see as well, the manufacturing process for those is probably prohibitively expensive but that is as small as they can go(according to our current knowledge of the universe at least).
I can't imagine Intel has all of its eggs in one basket on Extreme Ultraviolet Lithography though. Something thats been in development for even 5 years and doesn't show any concrete signs of success should at least have alternatives developed for it. After 5 years if you still can't say for certain if its ever going to work, you definitely need to start looking in different directions.
Why does Intel need to push the envelope that hard and that fast just to create a product that will, in the end, have extremely low yield and extremely high cost?
Just so they can adhere to some ancient "law" proposed by one of their founders? It's time to let go of Moore's Law. It's outdated and doesn't scale well... just like the x86 architecture! *ba-dum, chhh*
Referencing science fiction, Star Trek's Voyager was the first ship to utilize bio-neuric computer technology. I imagine that the cells in the sacks are smaller than any chip that the Enterprise D had. I would consider the cells in Bio-neuric computer technology as "chips", and it exists in our brains. We just don't know yet how to harness it. So yes, smaller computer chips are possible.
I have a feeling that once doing smaller and smaller lines becomes prohibitive, we will see a return to either revving up the clock speed (if possible), or adding more cores per die. Maybe even adding more discrete CPUs, so a future motherboard may have multiple CPUs on it similar to how mid to upper range PCs ended up with multiple procs present around 2000-2001.
There are always more ways to keep going with Moore's law if one item gets near exhausted.
I miss the pressure AMD used to put on Intel. When Intel had an agile competitor often leaping ahead of it chip speeds shot up like a rocket - seems like they've been resting on their laurels lately...
When all those people died when steam engines could go faster than 25mph. And no aircraft has gone faster than the sound barrier.
All these so-called rules and laws are meant to be broken.
And the fact that Intel cant make something work after 13 years means nothing. They will surely make up for that with all the profits they make in the discrete graphics business.
I think there has been a major article asking this question every six months for the last decade. Then: surprise surprise, there's a new tech development that improves the technology. We've been "almost at the physical limit" for transistor size since the birth of the computer, why will it be any different this time?
Well I can say with absolute certainty that they will not go below the Planck length.
'We are trying to prove ourselves wrong as quickly as possible, because only in that way can we find progress.' RPF
Perhaps as we get closer to these physical limits of classical computing we'll start to see more and more money invested in quantum computing research.
Larger dies generally cost more because it's more likely that they'll have a defect. I haven't done any chip design since college (and even then it was really entry level stuff) but if you could break the chip down into 10 different subcomponents that need to be spaced out, you could put 100 of those components on the chip and then after manufacture you could select the blocks that perform best and are defect free, spacing your choices accordingly.
I'm pretty sure chip makers likely already
At some point, we're going to see an argument that starts out with "It's like a Nazi eating a Tostito with ..."
At least a Tostito is a chip.
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Intel and AMD have both been producing it for a number of years now.
No sig today...
Actually, the issue of decreasing linewidths has been a major concern ever since UV lithography came into play. The progress is really amazing. It was a big deal in the late '80s to get under 100nm, now there is consistent production at 32nm. There have been research programs investigating X-Ray lithography and electron-beam lithography, but I don't think any of these have panned out for mass production. Now, another concern is electron leakage from these tinier linewidths. Sure, high-K materials help, but there is still some loss.
I think, therefore I am - Rene Descartes; I yam what I yam, an' that's what I yam - Popeye
The article mentions "dark transistors", which are transistors on the chip that can't be powered because you can't get enough power onto the chip. This is the problem that reversible computing was supposed to solve.
Current technology is based on a single planar layer of silicon substrate. A chips is built with a metal interconnect on top. But the base layers are essentially a 2D structure. We are already postprocessing things with thru vias to stack substrates into a single package. The increases density from the package perspective.
Increasing technologies in stacking will keep Moors law going for another decade (as long as you consider Moor's law to be referencing density in 2D).
or WiMAX
because "X-rays" is such an UGLY word....
Since they are so parallel they are made as a bunch of blocks. A modern GPU might be, say, 16 blocks each with a certain number of shaders, ROPs, TMUs, and so on. When they are ready, they get tested. If a unit fails, it can be burned off the chip or disabled in firmware, and the unit can be sold as a lesser card. So the top card has all 16 blocks, the step down has 15 or 14 or something. Helps deal with cases were there's a defect, but overall the thing works.
For one, Itanium is still going strong in high end servers. It is a tiny market, but Itanium sells well (no I don't know why).
However in terms of the desktop, you might notice something: When AMD came out with an x64 chip and everyone, most importantly Microsoft, decided they liked it and started developing for it, Intel had one out in a hurry. This doesn't just happen. You don't design a chip in a couple months, it takes a long, long time. What this means is Intel had been hedging their bets. They developed an x64 chip (they have a license for anything AMD makes for x86 just as AMD has a license for anything they make) should things go that way. They did and Intel ran with it.
Ran with it well, I might add, since now the top performing x64 chips are all Intel.
They aren't a stupid company, and if you think they are I'd question your judgment.
It seems to be almost an article of faith with geeks that if only we didn't have that nasty x86 we could have so much better chips. However the thing is, there ARE non-x86 chips out there. Intel and AMD may love it, others don't. You can find other architectures. So then, where's the amazing chip that kicks the crap out of Intel's chips? I mean something that is faster, uses the same or less power and costs less to produce (it can be sold for more, but the fab costs have to be less). Where is the amazing chip that uses a bunch less silicon but does the same work?
You can't find one, and there's a reason for that. The API of the chip is just not such a big deal these days. For a lot of reasons you can have many kids of APIs and it doesn't really increase the complexity of the chip by a lot, nor mess with performance.
I'd love to see that I'm wrong about this, I'd love to see a desktop CPU (remember that's what we are talking about here, not embedded stuff) that can outperform an i7 with less silicon and less power, but I haven't and I don't think I will.
With greater clock speed comes greater heat dissipation needs (most heat is created at clock switching); they have basically hit this wall already, hence the multi-core direction everyone is taking (can't go faster, so lets just go the same speed, but in parallel).
People have been proposing circuits for regenerative switching (mainly for clocking) for a long long time. The problem always being that if you add an inductance to your circuit to store and feedback the energy, you will significantly decrease how fast you can switch.
Also, you think transistors are difficult to build in small sizes? Try building tiny inductors.
That's how small they can go. Beyond that, increasing the functional density of our CPUs will get really challenging.
"Who is the Journal of Quantum Physics going to believe?" --Stephen Hawking
Sort of off topic but there was a science fiction story about this scientist who created a potion that could make him smaller, and he just kept shrinking and shrinking, and all the different worlds he went thru each time, atoms turned into solar systems, and he just kept going down, down, down into infinite smallness. The story is here.
try { do() || do_not(); } catch (JediException err) { yoda(err); }
Actually, it's pretty common practice to put spare arrays and spare cells in the design that aren't connected in the metal layers. When a chip is found defective, the upper metal layers can be cut and fused to form new connections and use the spare cells/arrays instead of the ones that failed by use of a focused ion beam.
But that still adds time and cost. Decreasing die area is pretty much always preferable. Also, larger dies means even more of the chip's metal interconnects have to be devoted to power distribution.
How about writing better software. Stuff that doesn't require 24 cores and 64GB of RAM?
The diameter of a silicon atom is roughly. 0.25 nm. That means that 32nm is about 120 atoms across. A 16nm line is about 60 atoms across.
For reliable use, there is going to be an approximate minimum to number of atoms in a line. Electron interactions among individual atoms are quantum events, so for any sort of predictability you're going to need enough atoms for the probabilities to average out enough. I don't know how many that is, but it pretty much has to be more than one.
I have a great deal of faith in the ingenuity of the companies involved, but there is a lower limit that's independent of fabrication, and we've got to be getting fairly close to it.
"When you have eliminated the unacceptable, whatever is left, however improbable, must be the truthiness" - Holmes
Why hasn't Intel rolled out 3D chips stacked in layers, with microfluidics cooling between layers? I used to see all kinds of engineering PR about it, but it's been years since I saw any progress, and it's taken way longer than I expected.
3D would not only increase the amount of transistors (and other devices) fit into a "chip", but put the circuits closer together, requiring less voltage/power and shorter propagation times. What's holding it up?
--
make install -not war
Perhaps the answer is to use something like electron beams or atomic beams instead of photons.
graphene.
I wonder if the mobile chips are a good excuse to introduce the public to a new architecture. You start selling a phone with the new architecture where it's low risk and the software isn't entrenched. Then, scale it up for different devices until at some point you introduce it to desktops? It looks like this is what Apple is starting to do with the Cortex chips.
Seriously, silicon CAN be stacked. Not in a single process but multiple dies in a single package is a good start. No, its not going to start out showing the same speed increases that we've got from shrinking the size of everything, but once you get so small you're done. Once you start getting every single drop of computational power out of a particular bit of matter, the only thing you can do is add matter.
Its just another way to add cores essentially. Given some time, someone will start figuring out WAY better ways to interconnect the stacked dies, or eventually make one die with layers of silicon in a truely 3d chip.
Its not going to advance until we start doing it and learning what works and what doesn't. Until we put some effort into 'work arounds' that almost achieve what we really want, we'll never likely jump directly to the end result.
Car Analogy:
Instead of trying to jump from cave man to Aston Martin, the wheel was invented first, and then various methods of attaching wheels to seats and animals, and finally to where we are today.
We may even find out that our current thoughts about building chips in layers is just a bad idea anyway and we go an entirely different and far more useful direction, and then all the buggy whip makers will be freaking pissed but society will be better off for it.
Persistent Volume manager for Kubernetes - https://github.com/dwimsey/openshift-pvmanager
making a smaller die size means you can fit more on a single chip, which in turn makes it go faster right? Well only if you keep to the same idea.
Why do we need so many? Well the speed in which electricity travels, and from which something can switch from + to - is pretty much constant. Our current technological method is simply making them small and cramming more and more and more onto a chip, which can then of course do more, because it has more stuff. All that stuff is still all working at the same "speed", just more of it is working.
While not very far along the development line, using "light" rather than current solves a lot of problems. A) it is a lot faster, and B) likely does not produce the amount of heat due to resistance along the material.
More exotic is quantum chips, which I don't know all that much about, so they may, or may not exist... :)
Hopefully, I'm not duplicating someone's post... Being able to cut a tighter line is one thing. Being able to do it on a "making license plates" scale is something else. As you move increase the density of what is being packed on the chip, you have to be able to increasingly control for smaller and smaller particles. Each jump in Clean Room Technology is neither easy, nor inexpensive. For details, and a whole lot more related material:
http://www.lowtechmagazine.com/2009/06/embodied-energy-of-digital-technology.html
Faster processors are fine for servers and research...but as a consumer I'd prefer to have programs that don't require 100s of MB or RAM, Operating Systems that don't require GBs of space....so use this shrunken die to make my stuff smaller and cooler to the touch...and have it run longer....and write some freakin efficient software so I don't need more RAM every few yrs.
This would work better, of course mining Neutron stars for it would be very hard. But you could really shrink down those chips...
Tsukasa: All I really want, is to be left alone...
Folks don't often realize how much work we software writers go through to write this big, complex, core-eating software. Back in the day with 8-bit 500 KHz CPUs we could write a simple 1000-iteration loop with a bit of code in it, and it might lag the CPU for a whole second. Now with these fast processors we have to go through all kinds of hoops to use up all those cycles! Building languages on top of languages, interpreted languages, all kinds of extra error checking (error checking can often take 80%-90% of the cycles and code), objects on top of arrays on top of pointers on top of objects ... you get the idea. SOMEBODY has to make the software to use up all those cycles.
It's a dirty job, but somebody has to do it!!!
WE CAN NOT LET THE HARDWARE PEOPLE WIN!!! For every added processor, every bump in Hz, we WILL come up with a way to burn it! Soon we will embark on the new 3D ray-traced desktop - THAT will keep the HW folks busy for a while!!! And (don't tell anybody) soon we will establish the need for full time up-to-date indexing of everything on the LAN. Of course, that could be done by one machine, but if we all do it independently on each machine, that will burn another whole 2GHz CPU's worth of cycles.
Our goal and our motto: "A computer is nothing but a very complicated and expensive heater." :D
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where are my mod points when I need them? Thanks, I LOLed this, and needed that. Not to mention its true in a sick way...
I was curious about this, and looked into it (about ten years ago). The results I got implied that an inductor Q better than 2 wasn't possible for normal processing at the transition times of interest, and the cost was poorer layout due to the space the inductor would consume on a metal layer. Overall, there might be a benefit, but it would be small and difficult to design in.
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But why arent we running our OS's on Video cards yet?
GTX 470:
Video Memory: 1280MB
Memory Type: GDDR5
Memory Interface: 320-bit
Stream Processors: 448
Core Clock: 625 MHz
Memory Clock: 3402 MHz
Shader Clock:1250 MHz
I refuse to believe there isn't a group of linux nerds that cannot port the kernal into some Vector form to run on my Video card.
Just saying...
Working with chips for 100GB long-haul optical transport, we're already at the stage where we can't actually fill the die with active gates because of power dissipation.
The basic problem is that power efficiency (MIPS/mW) no longer scales with the square of gate length like it used to, because supply voltage no longer falls proportionally to gate length.
-- 0.35um chips ran off 3V supplies
-- 0.18um chips ran off 1.8V supplies, same power density
-- 40nm chips run off 0.9V supplies, should be 0.4V for continued voltage scaling so power (CV^2) is already 5x higher than it "ought" to be
We've already managed to design some high-speed circuits with 10W/mm2 peak power dissipation; if all circuits were like this a 300mm2 die would dissipate 3kW...
http://www.newsdesk.umd.edu/bigissues/release.cfm?ArticleID=2190
You need to go into 3 dimensions. You need to roll up the silicon into a scroll and circulate cooling fluid between the layers. As you roll the layers into the tube you soldier connections between the layers.
Or you need to make a computing cube, which is a few mm squared made up of hundreds of layers of silicon and circuits.