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Low-cost Reconfigurable Computing (FPGA's)
Anonymous Coward writes: "People at the at Chinese University of Hong Kong have developed a reconfigurable computing card which uses the SDRAM memory slot instead of the PCI bus. Measurements in the paper show greatly improved bandwidth and latency - why aren't more people using this idea?"
Someone want to post text, pdf, or ... something?!
sulli
RTFJ.
well can you?
Nuron did this two years ago. They were bought by Intel this year.
the idea of FPGA computing has been around for a little while at least (look here for examples). i think Scientific American even wrote about "configurable computers" in 1997 or so. why aren't they more popular, then?
modern processors are well-adapted to general computing tasks.
FPGAs (read: custom iron) might be good for a few specialized tasks (breaking 3DES, for instance), but most of us will be a lot happier on our UltraSparcs and Athlons and G4s.
Catalina Research offers a card line called the "Chameleon" based on Virtix-E series FPGAs. This allows the card to provide millions of reconfigurable system gates that the use can apply. Connected to the FPGAs are independent blocks of ZBT static RAM which can support a single read or write operation per cycle. The Chameleon products have three high-speed IO daughtercard sites compatible with the industry PMC standard.
Chameleon VME Block Diagram
the byproduct of years of oppression by the white man
Does anyone have a plain text copy?
III.IIVIVIXIIVIVIIIVVIIIIXVIIIXIIIIIIIIVIIIIVVIII
If this were so cool and such an awesome way to do computing, then why do we even have the PCI standard? They should make motherboards with 6 SDRAM slots instead of 6 PCI slots. They would help out SETI@Home!
Avoid The Rush, Hate OU Early!!!
StarBridge Systems uses these to make their supercomputers that run in Standard ATX case... And I think they charge around $15 million for the low end models. These info came from a slashdot story but I can remember when and I don't have time to verify. I just remember CmdrTaco being very sceptical.
I have also wondered why more people aren't using the memory bus for peripherals. For instance, the VGA adaptor would greatly benefit from that interface (3d work, video games), also, using that bus as a network connection in a renderfarm would probably be nice too. Seriously, the PCI buss can only offer so much (132 MB/S) which is certainly going to be a problem with anything faster than gigabit ethernet... Meanwhile, modern memory busses are upwards of 4.8Gb/s. Imagine multiple machines strung together with that kind of bandwidth between them!
Another question I've had bouncing around in the back of my head is why no one uses MPEG decoder circuitry for MP3 playback? All the players I've tried, windows or linux, take 10-30% of the CPU for noraml playback operation. This is unacceptable when working in big apps like 3DStudio Max, make-ing a big app or running big scripts. I have an old MPEG decoder card from a Creative DVD, also I believe my G-Force has MPEG decoder acceleration... How much trouble would it be to write a driver for Winamp that uses preferred devices like that?
:)Fudboy
I guess I'm only a Fudboy, looking for that real Transmeta
This may help a little, but in general, people haven't figured out how to make FPGA-based computing sufficiently useful, cheap, and easy in order for it to catch on. Programming an FPGA is still rather hard and the architecture limits severely what you can do. And there is the chicken-and-egg problem with the boards: if you write software for them, few people can run it, and few people are motivated to buy a board because there is no software that uses it. Right now, you are probably a lot better off buying a dual processor board or a cluster than an FPGA add-on.
AHHAHAHAHAHAH THAT IS HILARIOUS MAN!!!!!!!!! mod this up right away!
Here is a PDF version
Top Most Bizarre/Disturbing Error Messages
PDF (thanks to ps2pdf.com) available at http://homer.artificialcheese.com/fccm01_pilchard. pdf (I'm not putting an HTML link in for a reason, I don't want everyont to get it from me) /. effect!
PLEASE MIRROR! I dont have nearly enough bandwidth to withstand the
FPGA technology to replace (or more like having a "flashable") Current processors could/would be a great leap in computing, it would mean having a "soft-hardware upgrade", microcode or "sillicon" bugs could be addressed, but there would probably be the downside of everything else in the computing industry: companies would released bugged stuff, beta would go around like current drivers :), etc etc.
All this said, unless some big breakthrough happens, we won't see out Athlon or Pentium IV system replaced by these, the 2 main limitation of FPGA are the number of available gates, and the speed at which they operate.
While they've managed to increase the number of gates to something quite big (last time I read about this I think it was in the low million? 1 or 2, but I can't be sure), this is enough to "emulate" microcontrollers or lower end processors, but not enough for higher end microprocessors. While eventually they will catch up and maybe someone will do his thesis on emulating an Athlon off FPGA stuff, by that time we'll be at the 2nd or 3rd rev of Post-hammer processors, so it will look like today being able to emulate a 486 (granted, there could be some use in that, but none come to mind right now.. parrallel processing? 1 athlon can replace zillion of 486s...) Also the developpement of microprocessor is going at a faster pace than FPGA technology. I am not saying this couldn't happen, but it would need a serious bump in the fab process and technology to be able to reach Ghz speed, and probably few 100M's of gates.
Still, it's a very interresting technology.
--- Metamoderating abusive downgraders since my 300th post.
Configurable logic boards have been around for a while, the main problem is cost. Last I heard, you could get one that could be configured into a 386 for about $2000 but that was a few years ago. It would be great if they could do stuff like program the chip into a divx decoder when you play a divx or an processor dedicated to executeing the 3d graphics engine when playing a game.
Any sufficiently advanced influence is indistinguishable from control.
I wasn't able to read what the post-script file said (nor do I have a pdf reader on this system), but from the description on the slashdot posting it almost sounds like what the Panda Project team was trying to do. Maybe someone that was able to read the article could tell me if this "new" idea is similar to the Panda Project.
http://www.starbridgesystems.com/prod-hal1.html
.000000001 seconds.
Build a super computer and run 98SE on it? Imagine a BSOD in less than
Get a free ipod.
Using memory slots for devices is a bad idea. The interface is not designed for devices. There are no IRQ lines. The address space can be configured by the chipset to fall anywhere in the address space of the whole machine (your device may end up starting at 0). The address space may even be interleaved with other memory devices in other slots. And the next generation of memory will use a whole different interface, and most new motherboards will soon migrate to it with little concern for backward compatibility.
now we need to go OSS in diesel cars
wouldn't you be willing to sacrifice a RAM slot to excel your computer at a particular task? maybe fast mp3 enc/dec, genome grinding, SETI@home, Photoshop filters, etc? i mean, i don't see the Linux drivers coming around anytime soon, but that's no reason to shun this development; we have to embrace the future sometime... maybe we can even make a Linux card, and since these are _Field-Programmable_ Gate Arrays, we could even update kernels when necessary!
Cretin - a powerful and flexible CD reencoder
Anonymous Coward writes: "People at the at Chinese University of Hong Kong ..."
--> Shuld't it be "The People's University of China"?
As of Postgres v6.2, time travel is no longer supported.
I prefer open communication and spam to closed communication and no spam.
Would there be any speed advantage to useing a reconfigurable chip vs. a programmable DSP for a very processor intensive task, like MPEG encoding or real-time full-screen graphics rendering? (think Fractal Flames as a music visualization plug-in) Assume that all your algorithm code can fit in on-chip cache or high-speed L2 so you don't clog up the memory bus)
What sound card? The SB Live only takes 1-2% CPU usage on most systems, but if you have a lesser card the CPU use can go WAY up.
No, you shithead! The university's situated in Hong Kong, not mainland China, and was established before Hong Kong was returned to China.
There are several FPGA cpu's available already. For loadsadetails, go to http://www.fpgacpu.org/ and see just how easy it is to create a CPU. I've even managed to (starting with Jan's work) build my own without any prior knowledge of verilog.
The main drawback is always going to be speed though - it's simply far and away more complex to have reconfigurable hardware than static h/w. The current "hot" CPU of any generation will almost certainly never be reconfigurable!
Simon.
Physicists get Hadrons!
I find it very interresting that a Chinese Universesity is allowed to use a board produced in Taiwan. Maybe it is just too hard to find a board, that isn't produced in Taiwan.
Jan
as expansion slots were used by a few companies that sold G3 expansion cards for older PowerMacs.
IIRC, they had an expansion card that you'd attach to the cache slot near the original PowerPC CPU.
This way the new CPU would have all the memory bandwith it needed to run at 400 Mhz. 400 Mhz in a performa 6200... wow!
What ? Me, worry ?
Not that I'm recommending using the memory bus for 3d, but...
PCI/AGP are great for uploading static textures, on that you are correct.
However, there's more data than that to saturate the bus:
* Procedural textures
* Vertex cloud animation (bones aren't always appropriate!)
* Swapping textures when insufficient video ram is available.
Any of these can cause bus saturation. While many games are following the Half-Life model (static everything, use matrix driven hierarchical bones animation), this creates pretty bland worlds.
If you want to realistic water, more organically animated content, or more subtle animations, this bandwidth becomes critical. Vertex/pixel shaders regain some of this by allowing processing to be moved back into the 3D GPU, but that only works for inherently procedural and low order polynomial effects - data driven or more complex procedurals still need to upload obscene amounts of data!
I should also mention that accelerator card drivers are optimizing pipelines for static textures, Unreal ran into this problem badly, and it continues to this day.
Most mobos only come with 2-3 memory slots. 4 if you're lucky, more if you're paying through the nose for a server mobo.
http://booya.dorm.duke.edu/temp/fccm01_pilchard.pd f
Suck that bandwidth up.
With no prior knowledge of verilog, I followed Jan Gray's articles in Circuit Cellar and extended the design on my own. Verilog is superficially similar to 'C', so long as you remember that each "function" will operate in parallel.
:-) on your own processor rates up there, as far as geekdom is concerned. At least to me, but maybe I'm biased :-))
:-)
Boards are cheap (approx $110 US for a 200k gate chip that could easily hold 4 processors and a lot more).
My own direction is interfacing stuff to my own processor that is based heavily on Jan's design. It's for purely personal use, and saying that you are running code (assembly language only
Jan's site is at fpgacpu.org if you're interested. There are lots of details about all sorts of issues on the site. Some technical, some not so technical. Have a look under GR CPU's or XSOC
Simon.
Physicists get Hadrons!
It must not have run Linux. ;)
If Gates were reprogrammable, then we wouldn't be in this mess in the first place.
Bowie J. Poag
On FPGAs as PC Coprocessors, redux:
http://www.fpgacpu.org/log/aug01.html#010811
On FPGAs as PC Coprocessors (1996):s sors.html
http://www.fpgacpu.org/usenet/fpgas_as_pc_coproce
The sound card is not that important. The most important thing is the decoding speed of your CPU. Faster procs mean faster decoding. Better FPUs also give smoother mp3 playing (ouch Cyrix & Via!!!). And let's not forget about the mp3 player itself (eg. winamp has better decoding algorithms than some windows media player.) You may not believe it, but the OS is also VERY important. Winamp in NT uses 50% less CPU time compared to the same Winamp with the same settings in win9x. (Linux with winamp in wine is somewhere in between, if you care.) And the best combination is a reasonable fast CPU (with a good FPU, like the AMD ones) with a well design OS and a sane mp3 player (like xmms in linux :-)
I started with nothing and still have most of it left.
Let's see, you'd need to modify whatever OS you got to NOT use everything it has. Modify the BIOS to NOT check the memory status in certian areas (or tell the periphrial to emulate being ram for the moment. And then to actually use it you'd have to poke values into memory and peek at them after blowing off a couple clock cycles (kinda like in a Commodore 64.) Heck isn't that how normal buses work anyhow? Just slower & has a way to find your perhiphrial other than memorizing memory locations?
Then again I hardly know squat about how this stuff works, apologies to those who know what they're talking about. (:
--Roy
Actually, CUHK is the official name of the university (since I'm from Hong Kong). CUHK has been ranked #6 best university in Asia by Asiaweek Magazine. But the most famous university in HK is Hong Kong University, which is #3 on that same ranking.
http://sage.che.pitt.edu/~harrold/tmp/fccm01_pilch ard.pdf
-- john
greed is always the reason
The opto-electrical conversions (one at each end) for throwing in the fiber would damage your latency significantly more than just running wire.
I seem to recall some one actually did an implementation using the 2nd level cache space
on a 21164 as a network processor. It could address 16 MBytes of cache, the bus would run
at 66-83 MHz, and was 128 bits wide. The major
drawback was the power on the CPU prohibited
1U card slots.
SDRAM slots are relatively sparse. They don't
DMA to another location in main memory either.
as was stated in the main post, it was just *developed*. Do you even try to think about what you write before you write it?
If someone is looking to tinker with some (F)PGA's I would recommend Altera's student kits and software. You can use the standard part schematics included or you can define your own using VHDL. Only $150 or $105 if you're a Georgia Tech student.
I am afraid that I must disagree with many of the comments posted concerning FPGAs. First off, FPGAs have been successfully demonstrated in the multiple GHz frequency range using SiGe as a base material (Dr. Jack McDonald's group at RPI has done such an implimentation with SiGe BiCMOS based systems.) Further, the contention that FPGAs are "difficult" to program, is I believe an oversimplification of the hardware/software relation in general. Are FPGAs more difficult to program than to implement C++ code on a PC? Yes, but they are also significantly more powerful pieces of hardware than the current computer architecture. For example, one of the most visionary uses of high speed FPGAs would be to replace component cards in the PC of today. For example, in a base system today, one typically has a video, audio, and I/O type card (i.e. hard disk/floppy disk/CD-CDRW-DVD). Imagine now a computer that consists of a large number of FPGAs, essentially reconfiguarable hardware. Now drivers can be reset on the fly, power up ready OSs with no boot time (using non-volatile configurations), and a host of other interesting and desirable properties are possible. If you want to send email the FPGA bank can reconfigure itself into a network or wireless ethernet card. This has some significant advantages over the current paradigm.
Several readers commented concerning the adoption of FPGAs is not going to happen quickly(i.e. no development support) or that the problems with bus interface speeds are nontrivial. However, these difficult problems are not the problem of the hardware, and attempting to interface it to the standard PC, however kludgy, is a rational approach. Criticizing the implimentation here is a bit like telling someone that they should have used a Porsche instead of a Pinto to build a time machine.
... a beowulf cluster of these.
It's been so long.
-Gabe
In normal CPU design, you have to take into account the distances between various parts of the CPU. The greater the distance, the slower (and hotter) the CPU.
That's just fine, when you can control exactly where the transister goes on the die, but FPGAs throw a curveball in:
The components in an FPGA are, IIRC, arrange in one big, massive grid. While it's still possible, controlling what a transister does by location is going to be much more difficult and time-consuming, in the development process.
Don't forget that one FPGA is different from another, so you can use the same 'ROM image' for different hardware. That's going to impact portability and development time.
Finally, don't forget that no matter how encrypted or secure the ROM image is before it gets flashed, it still has to be put into the hardware raw. Just build a virtual machine to intersept the flash data, and viola! You now have your (or your competitor's) CPU layout in a semireadable format. Now to run it through an FPGA emulator...
When (not if) this all comes about, you'll probably have hackers trying to tweak the trace lengths in their CPUs.
What Linux is to operating system kernels, a future hacker group will be to CPUs.
What's this Submit thingy do?
Well, while I was doing my final year project at Department Of Computing, Imperial College London we have the actual card made by Chinese University of HK. Bascially it is just a matter of having a SDRAM contoller "programmed" onto the FPGA, and wired correctly(it uses Xilinx Virtex series of FPGA, and Xilinx has implemented a SDRAM controller on it - see their tech notes - their sites is down when I write this). Having done my project with FPGAs, I would say the problem with this thing is that it is very fiddly to program the thing - it requires the understanding of software as well as hardware. I also agreed with some comments above that it lacks interrupts on SDRAM bus - therefore it is even more difficult to program the card.
Anyway, PCI FPGA cards has always been available, and they are hugely expansive. But they are getting down in price. One of the problem of FPGA is that the speed of the chips are slow (depends on the complexity of the circuit, you can only clock it to around 1Ghz for very simple cores, lot slower for complex circuit) so consider the speed of microprocessor it is not worthwhile to use them in normal computer systems - but a new niche is open up in embedded market.
Notice the name of the university is right! Chinese name of the university suggested that the "Chinese" in the university name is actually means Chinese language, not China the country.
The closest thing like this I have seen in person is my Mac desktop machine. It was a PowerMac 6400 (a PPC 603e fixed to the motherboard). It was never meant to be upgraded. 3rd-Party upgraders developed G3 processor cards that snapped into the L2 Cache slot. The card then tells the original 603e CPU to "sleep" and the L2 mounted G3 takes over all CPU functions. It works perfectly.
Oregon State's ECE department switched over to using FPGAs in all labs last year. They are great learning tool and you dont have to worry as much about miss wiring individual componets. I think they are a valuble tool in an accidmeic environment where students are constantly working and updating there projects. I also think they are graet for proto typing projects.
Back when machines came with 4K of memory (yes, K, not M), but could address 64K, it wasn't uncommon to memory map devices. It was an easy thing to do; a few discrete nand gates (7400 series ICs) for decode logic and you were done. Since a lot of the code was written in assembler then, it was easy to move stuff in and out of the memory locations.
:-)
Everything old is new again... I wonder how many other ancient techniques would be useful now...
Anyone remember hardware memory swaping (bank switching)? You could take that machine with a measly 8GB memory limit and expand to 256 banks of 8GB for 2TB of memory (assuming you could afford all that) with a single memory mapped bank select byte. Only 1 memory access cycle to swap 8GB.
Actually, that might be pretty cool.
Can You Say Linux? I Knew That You Could.
A friend of mine worked for a company called Nuron that had a DIMM card with at least one Virtex plus a bunch of SDRAM on it. Their killer application was accelerating public key cryptography. Intel bought them just for that.
As far as I know they decided to go for PCI in the future.
They had big dreams of accelerating all sorts of things, but I don't think that there's a huge market out there for this kind of thing given the cost and limitations. And also different applications require different architectures.
At work we prototyped a $5 ASIC with four Virtex1000 parts, each of which cost well over $1000 at the time. We designed our own prototyping board, and they must cost at least $10000 a pop in our limited quantities. I don't see the average end user willing to pay so much for a FPGA based solution, when they could wait a year and get the same thing at 1/100th the cost.
Actually, Pilchard isn't the only project looking at this idea. Our design group at Penn State is working on a similar project; it's a bit more complex of a design but based on the same idea. Our web page is at http://www.cedcc.psu.edu/SmartDIMM
I would give up my left nut and my first ammendment rights if it meant no more spam.
Just wondering: many algorithms have much faster parallel versions, eg set operations, sorting. Why not use FPGA's to implement a subset of the C standard library using parallel algorithms, wouldn't that be a cost effective way to get faster computing?
this is the damn funniest freaking post i have seen in my entire life hahahaa fucking hilarious
PostScript is probably older than I am, and my stupid Windows machine can't read it. Thanks Microsoft for being too cheap to license someone else's standard!
.. I feel this is a great idea!
Come on, if FPGA CPUs catch on in a big way, I can start writing my own paychecks and stop designing these boring circuit boards, just concentrate on Logic design.
Furthermore, FPGA is embrassingly *slow* technology. ASIC is the real custom/screaming fast stuff. In embedded envrionment, you usually use FPGA for slow custom computational stuff, if you need 1-clock-cycle-latency or 6GB/s bandwith or anything like that, you need an ASIC. Just look at those motherboard chipsets, they're not FPGAs, no way..
From R&D point-of-view, FPGA is really nice to work with, tho. You can play around with it to your heart's content until you get it right and there's nothing to stop you from burning/flashing/uploading a new logic code every day if you want to. There are tools for FPGA-on-ASIC which gives you the capability to tape out that groovy logic design into mass-marked ASIC once you're sufficiently sure you got it right. Naturally, it's as slow as the FPGA would be, since otherwise it'd screw up your logic timings..
Comment 1 RE:Linked directly to Postscript?
Try using ghostscript/GSView which will display the postscript file directly. (A quick search on Google gave the following link which should be useful
GhostScript
Comment 2: I don't think this is ever really likely to be part of 'consumer' system. FPGA's are great for
1) prototyping circuits that will later be implemented as an ASIC where the cost of "respinning" a chip is extremely high or
2) Situations where the system is only produced in very small numbers.
The main problems with FPGAs are that they are
1)Expensive!.
2) Relatively small in terms of the gates they can implement and
3) The clock speed that can be achieved is probably about an order of magnitude lower than an equivalent ASIC.
For many situations a multi-CPU system may be a much better option, and I certainly think that they'd be impractical for a mass produced system.
Simon
Having first heard about FPGA tech a few years ago, and realising that while it presented some interesting "tricky" problems, I completely failed to think of one application proving both interesting and vaguely plausible for which an FPGA would be the best practical "way to go". Recently I had several ideas - for which only IO bandwidth seemed an unavoidable problem. Is there someone who can comment on the feasibility of implementing:-
It seems like the Nforce chipset from Nvidia is working somewhat like that. The graphics controller is integrated into the chipset and uses the internal memory, but since you have dual memory buses (and current AMD processors don't need more than one 266 MHz bus) the chipset can have the same bandwith to the system memory as the processor.
This only makes the point that the processor should be able to use the bandwith better and that the 8xAGP bus the chipset is getting is 16 times faster than the PCI bus you are referring to.
Lets hope that the next generation point to point databuses is open enought to make adding an extra co-processor as easy as adding more storage.
I remember reading about star bridge a while ago, the general consensus on slashdot was that it was probably a scam, or at lest an operation with a dim chance of success. The benchmarks they touted did things like compare 4-bit integer adds (on their machine) to full blown 64bit operations on IBM iron.
Like I said, most people didn't buy into it, but the company is still around a year or so later, so who knows. Maybe they are selling some systems. Either way, they certainly aren't making much of an impact on anything in the computing world. Let's not forget that $15 million would get you a fuck of a lot of conventional CPU as well. It's enough to buy 10,000 high-end PCs and network 'em together (resulting in about the biggest Beowulf cluster in existence). And that wouldn't require any new programming technology.
I think these guys also claimed that they'd sell these things for $3-4k...
autopr0n is like, down and stuff.
For instance, the VGA adaptor would greatly benefit from that interface (3d work, video games),
Um... just what do you think AGP is?
autopr0n is like, down and stuff.
If you can write in C type languages you can design on FPGAs.
A Handel-C (C with extensions for parallelism and timming models etc.) to FPGA, development environment called DK1 was released by a UK company Celoxicaearlier this year.
There's an eval download for DK1 on their site.
The Chinese are the most technologically advanced people on earth, and will likely eclipse the Americans as world leaders in short order. As a nation, their industriousness and ingenuity are unmatched. While "fat cat" nations like the USA and those of Western Europe rest on their laurels of years long gone by, China forges ahead with a clear purpose and not a little justifiable umbrage at the rest of the world's perception of it. Advances like this FCPGA will more and more often come from China in the future.
That was like, the lamest joke ever...
autopr0n is like, down and stuff.
You have demonstrated an amazing lack understanding in current Chinese politics... First of all, the University is in Hong-Kong SAR (Special Administrative Region), which while technically a part of the PRC has it's own economic system, and is pretty independent from the central government. Also, the mainland Chinese don't have any real problem with Taiwan, and they believe that it is in fact a part of their country. Taiwanese citizens can buy land in China, for example. They aren't happy with the current government, though. But they wouldn't have much of a problem with Taiwanese motherboards (especially since Taiwan is the only country in the world where motherboards are made... which was the point of your joke, I know)
autopr0n is like, down and stuff.
The cheapest FPGA I know of is the Altera Educational board, you can get it for about $150 if you are a student (I'm not sure what else, you might have to go to one of the schools (colleges) that participate in their program.) For $150, you get suprisingly little performance, I'd be suprised if you could get a Mips 3k (one of the first mips cpu's, 32 bits and really slow), or an early Sparc cpu in one. I'd be really suprised if you could get a fast 486 or early pentium in one.
I always prefer to start the year off with a bang - or, to be more precise, a series of loud hums, a crackle or two, and
Or didn't you read the article? I'm specifically referring to section 3 on page 5. Now go crawl back under your bridge before Ozzi Binni gets it!
It seems a lot of people think all peripherals are created equal. Considering that many high end CPUs have more cache memory than the total memory of any PC produced before 1989 one could consider main memory to be "peripheral" already anyway.
At any rate, placing the FPGA on the memory bus allows the massive amount of communications required to reconfigure the board to occur in a reasonable time and also effectively gives you parallel processing for free. You treat part of the FPGA board as a second CPU (but not a general purpose one) and the rest of it as memory. When you've got an instruction stream that is better adapted to the FPGA's current confuguration, you write the data to it's memory, let it run and you can use the CPU for other tasks. Since most algorithms you'd want to run on the FPGA have a deterministic time of completion (even searches because you can bound the time it would take to search the entire data set) you just read the results off the FPGA memory after a little while.
Anyway I haven't read the article yet, so I'll go do that now.
As many here have already noted, FPGAs cannot yet approach the complexity of current processors, yet current processors lack some basic (and very useful) features of FPGAs. Perhaps the best way to leverage the strengths of both would be to embed a small FPGA in processors that is controlled (bitfile, I/O, etc) from the cpu itself. That way, if you had need for say, a priority encoder or massively parallel ALU, you just load a module into the onboard CPU and away you go. This would eliminate one of the biggest bottlenecks for off-board FPGA coprocessors (memory bandwidth) and limit the complexity of the implementation. I'm taking a FPGA design course right now and you'd be amazed what you can do in 10-20k gates. Anyone else have any experience in this area?
Derek
Don't Panic...
thats not offtopic u moronic moderators
hahahaha yeah I know lmao fuck dem moderators they come from goatse or somewhere
"I have not failed. I've simply found 10,000 ways that won't work." --Thomas Edison
Umm, I didn't post that. I clicked on a link at some website and it did it for me. Someone at slashdot should fix this.
"I have not failed. I've simply found 10,000 ways that won't work." --Thomas Edison