ohmygod2 wrote to us with a story from
SF Gate that Apple, unsurprisingly, is going to be one of the purchasers of IBM's PowerPC 970. At this time, though, it's unclear where Apple is going to actually *use* said chip.
Update: 10/14 15:53 GMT by
H : Follow-up to Tim's
story.
Slashdot Mirror
I predict that Apple will use the chip in a high end personal computer.
Google News of course has pretty much all the acticles. They are all based upon the same IBM press release, but many make slightly different predictions.
its used in the IBM z series servers and these servers can serve up like 100,000 pages per second its insane. this chip is only second to the dec alpha in FPU processing! macs running on these are going to be smokin``
Apple has been slowly expanding in the last little while.. OS/X is becomming ever more popular and Apple's hardware is slowly but surely getting much better as time goes on.. If Apple creates a 64-bit arch market before Microsoft does, Apple could really take off and beat MS.. Dreams CAN come true!!
Critics -- notably Intel -- argue that most desktop users have no need for 64-bit processing.
then to be redundant, Intel should face up to the fact that most users have no need for 2.8 Ghz processors.
There are so many options:
- Stacked up to make that annoying table in the engineer's break room stable
- Ceramic heat thingys for toaster ovens
- Dropped out of airplanes over Alaska as a NORML protest
- Thrown at people pumping gas
- As party favors at Job's next all-night coke party
- The latest thing in West-Coast gansta rapper accessories
I mean, seriously, where the fuck else would you use a new CPU than inClock speed does not measure processor speed. These chips running at 1.8 ghz are faster than P4's running at twice that speed. IBMs Power4 has a huge die and processes tons more information per cycle than a P4. So, if clock speed did measure speed a 100 ghz chip that does 1 operation per second would be 10x fast than a 100 mhz 486!!! right?
Now all we need is a good portable 64 bit OS. ;-)
>SELECT * FROM users WHERE clue > 0
0 rows returned
THis is an interesting story:
:)
The 970 is a derivative of the Power 4 chip (with what I assume to be the Altivec extensions)
These run in the 1.6 -2.0 Gig range
As a Risc chip
with 64 byte chunks.
Granted, I am unsure as of yet if Darwin runs 64 bit natively, but when it does, imagine a dual processor of these (with of course, quartz extreme pushing all of the video over to the Graphics processor).
Maybe I am getting my hopes up, but this is what I have been waiting for. New macintosh, here I come
Blah Blah Blah.
so i'm guessing that this is the first iteration of this proc. (even tho from what i read, it just a stripped down version of the chips they use in their own servers). and that their roadmap indicates some kind of wild and crazy ramping up in chip speed (since 1.8GHz will be puny compared to whatever intel and amd have out by then). cuz that's the only way they'll stay competitive with x86 hoopla (unless somehow consumers magically understand the difference b/w chip clock and the speed of the chip
anyone know if ibm's powerpc architecture allows them to do this?
----
i do not use drugs, i AM drugs -- Dali
http://www.eet.com/semi/news/OEG20021014S0059
Essentially a derivative of the company's Power4 microprocessor, IBM's PowerPC 970 adds 64-bit PowerPC compatibility, an implementation of the Altivec multimedia instruction-set extensions and a fast processor bus supporting up to 16-way symmetric multiprocessing.
I hope they use a memory controller that does at least DDR 333.
The law is a weapon of the government, not a protection for the likes of you. Surely you understand that.
Keep in mind most of these articles are coming from the BusinessWeek article, or an IBM press release. IN the IBM release, *nothing* about a real date of shipping was stated. What was stated was "Second Half of 2003".
As for the GHz issue, the chip does more per-clock than the P4. This means that it can still be competitive. Just wait another day for the MPF, and maybe we'll be able to see some initial SPEC numbers.
I think you'll be pleasantly surprised.
.
Blocklevel: Practical Information Architecture
This is an IBM chip. The fabled G5 is the next generation chip from Motorola, Apple's current supplier of G3 and G4 chips. It seems Motorola is aiming the G5 squarely at the embedded market, either because Apple already decided to go with IBM or Motorola did not feel the development effort was worth designing for Apple's needs.
I predict that Apple will use the chip in a high end personal computer.
...but the 64-bit iPod project is already in high gear, so we can't stop now, can we?
Wow! That's an even better idea!
pi = 3.141592653589793helpimtrappedinauniversefactory7
http://www.wired.com/news/mac/0,2125,55722,00.html
This is being discussed all over (here, Ars, Macworld) but the Wired article takes a much more "done-deal" tone than any of the other commentary I have seen yet. It suggests the possibility of Macs with 4TB of ram too :-)
--is not to be confused with user #672982 - Bame Flait
When Apple started selling FireWire-based Macs, Intel immediately tried to marginalize it by saying that the technology only appealed to a niche of consumers, and oh-by-the-way here's our specs for ATA/66 and USB 2.0 (for which the detailed specs hadn't been finalized, and which didn't start hitting mainstream systems until some 2 years later).
Intel takes seriously Andy Groves's words about only the paranoid surviving.
Slashdot: SF Gate: Wake me when one of the companies comments please. They will, but be patient before yelling CONFIRMED!
Thanks
So close and yet so far from the world's perfect ID number
"Critics -- notably Intel -- argue that most desktop users have no need for 64-bit processing"
:-)
Critics -- notably Microsoft -- have argued that most desktop users have no need for more than 640kb of memory.
the 'slide
"Corporate rock still sucks. What are you gonna do about it?"
"Corporate rock still sucks. What are you gonna do about it?"
Okay, actually read the stories. "According to industry sources..." is what it says. Nowhere is there confirmation from Apple or IBM that Apple has comitted to purchasing them. This is not new, this is just the same news as the last story, only centered on one specific rumor, instead of the main story.
As soon as Apple or IBM officially states that Apple has committed to purchasing these processors, don't title the story 'Apple is Buyer...' since we still aren't sure.
Yeah, I'll admit, I've been expecting it since IBM announced the chip, and I fully expect that Apple will be the main customer. BUT, my belief (or the belief of any 'industry source', without hard proof) doesn't make it a fact.
I'm not asking that you not to rumormonger on it, I'm just asking that it not be presented as fact when it is still just rumor.
(Bah, and now I've forfietted three of my moderator points by posting in a thread I moderated in... :-( It just got me pissed off when I finally noticed that there still isn't any proof.)
Another non-functioning site was "uncertainty.microsoft.com."
The purpose of that site was not known.
In terms of die size, a rough measure of cost, the PowerPC 970 measures 118 mm2, against 131 mm2 for the Northwood 2.X-GHz Pentium 4. Both the IBM and Intel parts are being made in 130-nanometer CMOS on 300-mm wafers.
This indicates that the price could be competitive in desktops.
Way to go IBM!
The law is a weapon of the government, not a protection for the likes of you. Surely you understand that.
There aren't 2 architectures... they're all PowerPC chips, thus the same instruction set... and the new IBM chips are also 32 bit compatible, so they will run code from current PPC chips without a recompile.
.technomancer
Don't be surprized if Apple calls this a G5. Its all about marketing. Its a bit like intel sticking with pentium even after major changes in the chip.
Business News and Resources: www.usasource.net
The 'G5' will be whatever chip Apple slaps on their next 'big' processor upgrade. The G3, G4, G5 designations have nothing to do with the chips themselves or their model numbers. They're just spin that Apple uses to compete with the Pentium 3, Pentium 4, etc lineup. Apple could decide to throw AMD Hammers in their next generation systems and would still call the chip the 'G5'.
Ignorant consumers are unlikely to percieve any performace improvements in models unless there is some underlying technology that gets a new name or a new version number. It's like model years in cars, the 2002 has a higher number than the 2001 model, so it MUST be better, and people drool over it.
Article X: The powers not delegated... by the Constitution...are reserved...to the people
Actually IBM makes most of the G3's that Apple uses.
There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
Exactly. This is pure speculation, once again elevated to implied fact by a lazy, unverified summary. The story said no such thing, and quoted no verifiable source.
-- http://frobnosticate.com
Cupertino, CA - Apple Computer (AAPL) is expected to buy a record number of the new "PowerPC 970" CPU, but in a suprise move, isn't expected to actually do anything with them.
"We're doing great with the iPod, the warehouse is totally empty," said Apple VP Phil "All your Jaguar" Schiller. "Steve thought it would look more lived-in if we had some big boxes of stuff in there."
Steve Jobs was hard at work developing a new way to mispronounce the name of the new CPU and was unavailable for comment.
ZOMG I WOULD LOVE TO KNOW ABOUT YOUR FEELINGS ON MACINTOSH VERSUS WINDOWS, VI VERSUS EMACS, AND HOW YOU'RE NOT A DORK
I imagine that thoses Apple computers will only be sold to the inhabited continents.
MHz and GHz are fine, but that's just RPMs. As anyone who has driven a bored out V8 or massive V10 will tell you, there is no replacement for displacement. You can rev a crappy 2L engine to 7,000rpm and make your itty bitty wheels spin and make a nice smell. But if you want to throw asphalt into the air and stike terror into living things you put the pedal to 8 or 10L of fire-breathing cast iron.
The Power line from IBM has that kind of displacement. You don't need GHz, or at least not as many, to get a lot of torque out the back end. And of course once you get torque, you can work on the revs. As we've all seen, higher revs happen with improvements to production technique, and are a given. But more torque (ie, more and better logic on the die) takes a strategic investment, and some amount of risk. But I'll take a bigbore Dodge Viper over this years higher-revving econo Tondabishi any day.
=^..^= all your rodent are belong to us
Despite the fact that the PPC 970 will be introduced at 1.8 GHz while the P4 is expected to be around 3GHz, the 970 will execute 8 instructions per cycle. I can't recall how many instructions per cycle the P4 executes but I believe it is far fewer than 8. Of the handful of articles I read about it, somebody said that the 970 would effectivly compete with a 4-6 GHz P4 as a result of the instructions per cycle efficiency of the chip.
Plus, it's gotta run cooler than a 6GHz P4 would. As a laptop owner, ignoring the superior performance potential of this chip, the cooling and power requirements alone would make me choose a 970 architecture over a Pentium.
The fabled G5 is the next generation chip from Motorola, Apple's current supplier of G3 and G4 chips.
Sorry, but you're wrong. IBM currently supplies Apple with the G3s (for the iBook). Motorola only supplies Apple with the G4s.
The Gn style of naming is Apple's doing. Motorola and IBM use names like PPC 750 or PPC 7440.
If Apple uses this chip in their future you can bet it will be called G5s (if they decide to keep with that naming convention).
sin(6cos(r)+5A)
Uhm, what are you talking about? This IS a PowerPC chip. It uses the PPC instruction set and is backward compatible with the 32 bit G3 and G4.
.technomancer
Your missing a ";".
sin(6cos(r)+5A)
No need. The PowerPC 32bit ISA is a subset of the 64bit version. 32bit apps run in 32bit address space perfectly happily.
You only need to recompile if you need to see the full 64bit address space.
Oh, and don't worry about AltiVec. The AIM alliance jointly developed the Vector SIMD extensions. Apple calls the unit Velocity Engine, Moto uses AltiVec and IBM calls it VMX.
"it's unclear where Apple is going to actually *use* said chip"
This reminded me of an exchange from the animated series "Freakazoid," when Douglas Douglas received a long-coveted computer chip for Christmas.
"Can I put it in, Mom?" he asked.
"Okay, but only in your computer."
(Well, I thought it was just as silly...)
Those who can, do. Those who can't, write technology blogs.
MHz and GHz are fine, but that's just RPMs. As anyone who has driven a bored out V8 or massive V10 will tell you, there is no replacement for displacement. You can rev a crappy 2L engine to 7,000rpm and make your itty bitty wheels spin and make a nice smell. But if you want to throw asphalt into the air and stike terror into living things you put the pedal to 8 or 10L of fire-breathing cast iron.
Bad analogy. A 3L F1 engine puts out in excess of 850HP, courtesy of a high tech design that can go in excess of 18,000 RPMs. A 3.5L modern engine in the Altima can put out 240HP, versus the 220 or so horsepower of a 5L Mustang engine of but a few years ago.
From the article:
"Critics -- notably Intel -- argue that most desktop users have no need for 64-bit processing. In fact, Microsoft Corp. has yet to release a 64-bit version of Windows that will run on AMD's Hammer chips."
Is it any wonder, given they just lost their defense against Intergraph's patent lawsuit which may result in them not being able to release the Itanium series?
Hey, Intel, last I checked, no one had a use for 32-bit processing or 640K of RAM on the desktop, either.</sarcasm>
blog |
http://www-3.ibm.com/chips/news/2002/1014_powerpc. html
moox. for a new generation.
>You can run the same binaries on a 80486 that you can on a Pentium 4.
Not true. If you use MMX or SSE2 instructions then it'll barf on the 486. I imagine there are other new things on the P4 that code *can* use that aren't available on the 486.
Of course a common workaround is to ship both kinds of code (with new features, and without) in your binary and let it decide at runtime / install time which to use. I imagine that some folks also ship source and decide at runtime which code to compile.
5Ghz of spinning it's wheels is a fraction of what a few Ghz of actual work is worth.
Last I checked the G4 had a 4 stage bus, and the P4 had a 20 stage bus. Although the P4 at full effiency can really move, the extra bus stages make it very hard to ever utilize the chip at it's full rating as instructions must "predict" that they won't interfere with the other 19 operations already in progress.
Add to that a growing lack of interest in Ghz as even the lowest powered machines are amplely powered to run a word processor / spreadsheet.
There are many other points to argue (like 32 bit processing vs 64 bit processing) but I don't think that 1.8Ghz will hurt Apple in the least. Especially with the history of thier 500 Mhz machines outperforming 1Ghz Intels.
The first iteration of these chips, if Apple buys from IBM, are likely to be desktop only. Only once Apple is content with the power consumption and heat immition will we see these in portables. Also, Apple might also want to sell a line of towers before they start seling portables with these.
I know this doesn't answer the question, but there isn't really much in the way of specs at the moment.
Jumpstart the tartan drive.
I doubt IBM would design a memory controller that uses a proprietary memory interface. This would raise their memory costs enormously without providing much in return.
I would guess that IBM would build a multichannel switched memory interface to DDR SDRAM. The controller would handle say four simultaneous requests for 64-bit memory values. This is what Nvidia does in their GPUs, and it seems to work for them. I believe the Sparc chip also has a similar on-chip memory controller.
It's like he never even thought about what he wrote. Someone conveys the thought that marketing hype may be costing you money, but let's ignore that and perpetuate the marketing hype.
On the other hand, the "Megahertz Myth" is marketing hype aimed at opposed marketing hype, so who really cares what either Apple or Intel offer as the "fastest"?
My PowerBook G3 runs just fine, my Pentium III runs just fine. If you need the power, go for it, but if you don't, go refurbished.
Just my opinion.
This kind of technology can be more easily implemented by burning porn directly into ROM reducing lookup times to almost the speed of the bus.
Apple could appeal to the hardware hackers with offers of ROM upgrades packaged in convienent easy-to-bend pinned chips using tightly machined push-down sockets. Withing months there would be a "Burn your own Porn ROM howto" and instructions on how to mill the pin thickness down to permit easy insertion!
(puns, unfortunately, were intended)
the P4 executes 1 instruction per cycle. the G4 does 3 (the basis of apples "megahertz myth" myth), so this is a huge step up.
as for the laptop part, hell yeah. my tibook by the end of 2003 should be nearing the end of it's "useful lifespan" - whatever that is, and i'll probably sell it for half of what i bought it for then and buy the latest, greatest "G5" laptop once it's avalible. that's the plan, at least. i'm in college after all.... and apple has a tendancy to take forever to release a new laptop based on a new processor design.
moox. for a new generation.
If they put it into one of those sexy Titanium Powerbooks, they got themselves a convert. Woot! I would love to be able to afford one
More likely they will start in the Xserve. The server crowd is much more likely to be able to use 64-bit and much more likely to be able to afford the new chip.
Can someone explain this?
Sujal
politics, food, music, life: FatMixx
Ahhh, touche.
sin(6cos(r)+5A)
And will run for five minutes before melting down from the heat they generate.
How ya like dat?
I'm wondering though.
I remember part of the reason apple went with motorla G4's was for the altivec engine. Back when Motorala and IBM split they forked the powerpc chip (the then G3), when this happened the definition for the chips changed slightly.
Motorola's definition of the G4 was a faster chip with the altivec engine. This is what allows for superfast processing during high floating point calculations (similar to MMX only phatter). This was also the part Apple was talking about when they used to advertise "twice as fast as pentium pc" because during those moments of super-intense number crunching, they were. IBM's definition of the G4 was a chip made with copper, shorter pipelines things like that. How is the switch to an IBM chip going to affect altivec? Since it's motorola technology I think it's safe to assume it won't be on the IBM chip. Will the IBM chip suffer at all during those slowdowns? Or will the extra 32 bit data path, in conjunction with copper, etc... be more than enough to make up the difference?
/* oops I accidentally made a comment, sorry */
i'd like to see the source of your "P4 executes 1 instruction per cycle" or perhaps clarify on what you mean by "executes"...
because even after a basic architecture course in college your would realize that all modern processors have multiple functional units which allow for much more than a single or even 3 instructions to be on the fly in a processor. I took my graduate architecture course from someone who was on the design team of the P4 and he eluded to us that the P4 has something like 130ish instructions on the fly at any given time, not just 1...
dave
You also forget that Apple has already gone through two major platform changes withoug much trouble by using emulator systems in the OS.
The first was 68K to PPC. No-one HAD to recompile anything, it all just worked.
The most recent was OS-9 to OS X. Again, emulation allowed most of the older apps to run without recompiling.
There where others like the switch to System 7 I believe where basically the entire OS was re-written in C.
Of course all of this is irrelelavent. The PPC designs have since the early stages planned for seamless progression to4 bit without breaking any 32 bit code.
Article X: The powers not delegated... by the Constitution...are reserved...to the people
FYI, the G4s have 7 stage pipelines It's in the side bar about halfway down the page.
T Money
World Domination with a plastic spoon since 1984
People often don't mention the effect that processor pipeline length (and effective branch prediction rate) has on performance.
Let us assume that the PowerPC 970 (AKA GPUL) will have a 10-stage pipe (AFAIK). "Average code" is 20% branch instructions, and a good branch prediction unit can give 90% correct predictions. So this leads us to need a pipeline flush every 45 instructions (on average). We then need to add the pipeline length to this number to get the number of cycles that the chip needs to be fully ready for the 46th instruction.
So:
PPC970 = 56
G4 = 53
P3 = 56
P4 = 66
On the first run of a piece of code the branch prediction unit will only get a 50% prediction rate (i believe). This prediction rate would also be the case if the cpu was running complex code that had random branching. The string of instructions before a pipeline flush would then be 10 instructions.
In this case the numbers look a little different and the g4/p3/PPC970 camp looks really good:
PPC970 = 20
G4 = 17
P3 = 20
P4 = 30
So to run this code at the same speed, the P4 would have to run 50% faster then the P3/PPC970 and 75% faster then the G4. Remember, when you are doing serious multi-tasking, the branch prediction unit will not get a 90% prediction rate as its resources will be split between several different applications.
Is life so dear, or peace so sweet, as to be purchased at the price of chains and slavery?
robotboy, projected performance of the 970 based is that it will be basically a 2 for 1 against a P4. So a 1.8Ghz 970 will be roughly equivalent to a 3.6Ghz Pentium4. But then again, we've all heard that before, except this time we can kind of look at the Power4 to get judge of what this processor will do.
Over 10 years ago I remember all the "twice the performance for half the price" predictions, and the similar prediction every time a new generation of PowerPC is announced. There are always exceptions that actually do legitimately (as opposed to rigged comparisions using 486 optimized code, Altivec but no SSE, etc.) run twice as fast on PPC compared to x86, but most comparisons show a 25-30% advantage for PPC against an x86 running at the same clock. More likely the 1.8G 970 will be equivalent to a 2.3G Pentium 4.
Breakfast served all day!
And IBM said no one needed the power of the 80386. Then Compaq released their 386 monster and IBM stopped mattering in the PC world.
Boobies never hurt anyone. - Sherry Glaser.
I agree with you, but I hope you're not confusing instructions per cycle with length of the pipeline.
The P4 processes instructions in a pipeline. The pipeline can contain 20 instructions at any one time, but each instruction is only finished once it exits the pipeline.
Same goes for the 970, I'd imagine.
To truly increase instructions per cycle, you have to add extra pipelines (and a lot of extra circuits to prevent instructions from stepping on each other)
If pipelines were always full, and all instructions were equivalent, the P4 would beat the pants off of the 970. But the pipeline is not always full because instructions often depend on the results of other instructions, and not all operations are equal in their requirements.
So shorter pipelines often handle instruction dependancies better resulting in better performance, while (for other reasons) longer pipelines are easier to design for higher Ghz.
G5 is shown on the Motorola PPC Roadmaps. With the advent of this IBM CPU, I expect the G5 to be exactly one thing: Cancelled.
...those charts Apple put out projecting PowerPC "risc" performance increaes into the future compared to Intel "cisc" performance? They are hilarious now, kind of like the book "Dow 25,000." I wonder if anyone has a copy? I totally bought the claim back then that the PPC would eventually cream the crappy but backwardly compatible Intel architecture, but not only has Intel kept up it has exceeded the PPC.
Syntax error: loose != lose, affect != effect, then!=than
You're living in the 1990s. The computer world has moved on considerably since DTP and Word Processing were the state-of-the-art. Today's "Ignorant consumers" are using extremely processor-intensive apps like iMovie, iTunes, etc. I just upgraded, and the "performace" [sic] improvement is very noticable.
Just to throw some math out there to help screw up the difference between clock speed and processor speed.
These equations give a performance ratio n...
Performance(a)/Performance(b) = n
Execution Time(b)/Execution Time(a) = n
CPU execution time for a program = (CPU clock cycles)(Clock cycle time for a program)
-or-
CPU Ex. Time for a program = (CPU clock cycles for a program)/(clock rate)
Where (CPU clock cycles for a program) = (Instructions for a program)(Average clock cycles per instruction)
Now we are dependant on the chips architecture as stated in the above response by Slashdotess. Are we running CISC (Complex Instruction Set Computer [IE. Intel]) or RISC (Reduced Instruction Set Computer [IE. SPARC, MIPS]). I'm not sure what Mac's are running.
When in doubt break out the math.
Chris
A possible reason: Sexium, Heptium/Septium, and Octium are really stupid names.
Let me clarify... I wasn't talking about actual hands-on performance. What I meant is that unless something gets a new name, a new model number, a new shape or something, consumers don't see a need to purchase the new product. This is the reason that auto makers hype model years.
Most consumers need to sense there is some need to replace a perfetly good product with a new model. Why buy the new PowerMac when you already have a working PowerMac? Because you have a G3 and the new one is a G5. Why get a 2003 car when your 2000 model works fine? bigger number in the model year of course.
This is like the "xeneon technology" in that junk air cleaner or "whirl-wind canister" in the new vacuum. They give consumers something that they percieve as a performance improvement. The fact that the name is meaningless, and perhaps even worse at the job than their existing "fan forced" product is irrelevant.
Article X: The powers not delegated... by the Constitution...are reserved...to the people
Skip to the happy ending where a 1.3Ghz Power4 beats a 2.2Ghz Pentium 4.:)4 /
http://www.digit-life.com/articles/ibmpower
Not speaking as a pro here, but I do know that Apple's mobo architecture recently has been to split as many system pieces onto their own independent buses as possible. Surfing over to apple.com's hardware section should provide some insight, as should ars technica & tom's hardware, which recently had some articles about this.
Its been cited as a key difference between the Mac system architecture and the PC system architecture - different buses for AGP bus data, processormemory, processorPCI, etc.
I imagine this will continue to be the case - don't know if it impacts the aforementioned speeds, though.
Not to mention P4 is going hyper-threading, and adding a bunch of execution units, and altivec and SIMD are different approaches to the same job.
It's all going to get quite interesting.
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
The people that are spouting about the G5 being Motorola have forgotten or never realized that the G3 is an IBM chip. Apple could call this G5 or anything else they wanted.
Encryption: I may not agree with what you say, but I will defend your right to encrypt it...
IIRC, Apple's been shipping non-PowerPC chips for a while. They've been shipping chips that 'implement the PowerPC instruction set', or something like that. Something to do with copyright, trademarks, and terms of the AIM alliance.
My God, it's Full of Source!
OUTSIDE_IP=$(dig +short my.ip @outsideip.net)
By "in flight" I'm assuming you mean "in some stage of the processing pipeline at any given moment" - I believe the P4 has something like a 20stage pipeline, the G3/G4 I believe is more along the lines of an 8 stage pipeline, if memory serves.
..
Part of what's at stake here is how many instructions are decoded/dispatched each clock cycle and then other factors like branch-prediction and such muddy the waters a bit more. In the end, the 'instructions per cycle' is really more of an average than anything else, as not every instruction will be a candidate for sending through the parallel functional units, etc. Taking into account the efficiency of the branch-prediction unit is important, too, since you could take a wrong turn and have to clear out all your functional units, at every stage of the pipeline and start over again, in certain circumstances. The fewer times this happens, the more effective your CPU will be at pushing the bits around.
Bottom line: modern processor mechanics are far more sophisticated than can be easily summarized by any one number or neat phrase. Just ask AMD about that one
There is a big difference between OSFMach [the part of XNU that is Mach] and GNUMach [the Mach part of GNU/Hurd].
Yes... they are both Mach but not quite the same.
I wouldn't call the Mach that Tru64 is based on the same kernel as the other two either [its Mach 2.5 I think]
People claim that the current G4s can't really make use of DDR because the processor bus can't handle it. This bus would obliterate those problems.
DMA avoids the processor all together BTW, routing data directly from memory through the chipset to other devices and vice versa.
--
The internet is the greatest source of biased information in the history of mankind.
No, you haven't lost it altogether. The first generation of G4 processors had a 4 stage pipeline. The move to 7 stages came later, because MOTO couldn't get the chip past the ~500 MHz hump with the 4 stage pipe.
-- Still waiting for the Nike endorsement
Because the pages in question where developed with Apple as part of the marketing. Motorola does not have any CPU part that is sold as "G4-1250" or "G5-2200" They're all MPC7450, MPC603 or stuff like that.
Likewise with IBM, all the chips have more cryptic part numbers. They only use the "Gx" designations in relation to Apple's use of the chips or as internal short-hand.
I can't locate any "official" pages from IBM or Motorola that refer to a PowerPC Book E type processor as a "G5".
All of that leads me to believe that the "Gx" designations are markeing spin from Apple that Motorola uses in some informal presentations to make it easier for the end users (Mac buyers) to understand those few documents.
The terms "G4" and "G5" do not appear in the Apple trandemark list, but I think they fall outiside the limits of a copyrightable or trademarkable term as they are too short. Though "PowerPC" is trademarked by IBM.
Article X: The powers not delegated... by the Constitution...are reserved...to the people
But the really big difference is number of registers. In short, the more registers you have, the more instructions you'll be able to run in parallel, in general. The PowerPC architecture, like many RISC architectures, specifies 32 general-purpose registers, whereas the P4 specifies only 8. With 32, there's a lot more room for recognizing parallelism by singling out which operations depend on the result of which other operations. Such dependencies force you to run operations sequentially, whereas the lack of such dependencies allows you to run them in parallel.
The chip with more registers, therefore, will take better advantage of its parallel execution units. It's also a good reason for Intel to pump up the clock speed (although doing it at the expense of pipeline depth can be counterproductive) while IBM pumps up the parallelism.
http://www.spec.org/osg/cpu2000/results/w ww.spec.org/osg/cpu2000/results/res2002q3/ q 4/
http://
http://www.spec.org/osg/cpu2000/results/res2002
It's interesting to see how well the x86 chips do compared to the rest.
You can see the details too - e.g. gcc, gzip, bzip etc. P4s seem to be better at the gcc benchmark than Athlons.
And IBM didn't see a world-wide demand for more than a dozen mainframes.
By the time you factor in biometric security, voice recognition and Christ's own gaming engines, VR generation, desk-top video editing and so on, 64 bits gets chewed up pretty fast even if you offload some processing to custom chips (and anyway who wants to build boxen with more ASICs that cost more money?)
64-=bitrs on the desktop? In five years it may be the majority of new box builds are 64-bits and 32-bit will be for poor for folks stuck on Windows without a migration path.
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>"Average code" is 20% branch instructions,
Well, as wanted to indicate "Average" is very vague. SPECInt has 14-16% conditional branches. SPECFloat has 3-12%.
>On the first run [...] 50% prediction rate
Not really. Statistical prediction and profiling can be applied. 85% of back branches are taken (loops), and 60% forward branches are taken. With predict taken you get roughly a miss prediciton rate (MPR) of 35%. With profiling you can get a MPR of 10%-20%.
>[...] and a good branch prediction unit can give 90% correct predictions.
Let's say an average one. (At best)
A two-level adaptive scheme (T. Yeh, Y. Patt) delivers a MPR of 3%. Hybrid Branch Predictors deliver even better results.
>We then need to add the pipeline length
The penalty is not always the whole pipepline length.
For the P4 the pipeline has 28 stages. But only 19 have to be flushed (8 are needed for the trace cache).
So lets review your calculation:
>So this leads us to need a pipeline flush every 45 instructions (on average)
20% branches 10% MPR means to me 2% pipeline flushes. How do you come on every 45 instructions?
I'd say something more like this:
Conditional branch instructions: 20% (your guess is as good as mine).
MPR 10% = 2E-2 Pipline flush probability
MPR 5% = 1E-2
MPR 3% = 6E-3
Some Guesses:
MPR: P3 5%, P4 3%, PPC970 3%
Pipeline penalty: P3 10, P4 19, PPC970 10
Overhead: P3: 10%, P4: 12%, PPC970 6%
So, at least according to my estimation the P4 has actually not 18% penalty towards the PPC970 but only one of 6%.
> multi-tasking
Umm, you are running with something 1GHz for something like 10ms. So you'll have 10MI. So most probably, the penalty for a cold BTB is probably neglectable. Otherwise, you're probably IO-bound anyway, and the CPU will be you're least problems.
The reason for better (or worse) performance may probably lie somewhere else. Actually, the increase of other pipeline hazards may be one of them. How long instructions take another one. (Well, for RISC processor an (non-fp) instruction takes 1 cycle, but for x86...) Not to mention caches and memory.
"Between strong and weak, between rich and poor [...], it is freedom which oppresses and the law which sets free"
On top of that, I think you should add about 30% for 64-bit processing
Not really. A few specialized apps will benefit from 64-bit, just as a few specialized apps benefit more from Altivec than SSE. But in general 64-bits is irrlevant to typical apps and tools.
64-bit may help indirectly in that the processor will need to fetch instructions and data more quickly, so more transistors will probably be dedicated to this. However these improvements could have been made in a 32-bit CPU as well. It's just that with 64-bit it becomes more of a necessity.
All just speculation, looking forward to seeing what Apple eventually comes up with. That said I'm a bit skeptical since we've had so many PowerPC advancements that were finally supposed to let PowerPC catch up to Intel, and of course nothing really changed.
http://www-3.ibm.com/chips/news/2002/1014_powerpc. html
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" Despite the fact that the PPC 970 will be introduced at 1.8 GHz while the P4 is expected to be around 3GHz, the 970 will execute 8 instructions per cycle."
The IBM processors are RISC processors. The Intel ones are CISC. RISC do less per instruction, therefore, it is stupid compare the way you do.
A slashdotter who didn't build his own computer is like a Jedi who didn't build his own lightsaber.
And anyone who works on both computers and cars can tell you that trying to equate mhz to rpms and displacement to bit-size is retarded.
;)
By the way, the NSX, with it's little tiny V6 performs in the same class as a Viper. So I guess it's not all in displacement in cars
Intel based chips typically have deep pipelines and fewer execution units and registers. Chips designed like this lose speed every time a pipeline flush is necessary (bad branch prediction, for instance), or during pipeline stalls (caused during some "exclusive" instructions and some synchronization tasks, notably when you need to stall out the pipeline). Intel makes up for this with higher clock speeds and larger high speed caches.
Number of parallel units and parallel execution is a very important factor in some performance tests - the original Pentium could either do int/float or MMX and required a context switch to flip between them, while Altivec could run at the same time as Int and Float operations (and multiple - I think 3 - could be processed at the same time). Alas, Motorola was slow out the gate, delaying the G4 multiple times, and Intel released the parallel-able SIMD around the same time (if not first) and had kicked performance well above the Motorola chips shortly afterward, which mostly made up for the aformentioned flaws.
Also, I believe some of the extra non-general purpose registers are used for context switching by the processor in PPC systems, where Intel's chips grab this information from L1 cache. I don't know if this is true for newer chips, though (even circa Pentium 2)
One has to wonder what kind of SEC fun Slashdot would get if the SEC were to pay attention.
Slashdot, owned by a publicly-held company, frequently posting highly inaccurate stories about other publicly-held companies to a technology industry audience, that could potentially damage a company's reputation and/or profit.
"Ahem. 128MB L3 cache (on the POWER4 in the benchmark)? Daaaamn. I'm not saying that a fat L3 cache has anything to do with SPEC benchmarks (I'm guessing it doesn't), I'm just making an observation: that's a lot of cache!"
In fact, it absolutely does have an effect on the SPEC benchmarks. You'll note that IBM's world beating POWER4 SPEC scores were recorded on a *dual core* module -- in other words, they cut the number of active cores in half, but the shared cache architecture meant that the L3 for each active core was thus doubled. Coincidentally, the SPEC working set will fit within the 64mb of cache per processor.
It's still hellaciously fast, but that monster cache IS there for a reason.
'jfb
To spur "enterprise Linux," Big Bang, the distributed two-phase commit.
Actually, in this case, it would be an Appleseed cluster.
Imagine clustering for anybody.
Wouldn't there be a rather large overlap between the applications that run no faster on 64 bits and the applications that do not benefit from faster chips period? How fast do you need your word processor to run?
I'm betting that most of the apps that really could take advantage of more speed (graphics, video, intense mathematical calculations, large database manipulations) will also be the ones that will benefit from 64 bit goodness.
Don't worry, by the time the G6 is released, I'm sure the G5 will have a power/heat profile that will be just fine for a laptop.
Now here's a case of when life hands you lemons you make lemonade. The parent was talking about simultaneous execution, i.e. how many instructions per cycle can come out of the end of the pipeline. You're twisting it around to take that number and multiply it by the horribly long pipeline.
Let's go back to basics, every time the processor makes a mistake in guessing what's going to happen next, the pipeline has to be cleared. Every modern CPU faces this problem so you want short pipelines so your penalty is low. Intel has vastly longer pipelines and thus they pay a higher price every time predictive branching screws up.
So having a large number of instructions being simultaneously worked on is a *bad* thing unless they are also being pumped out and executed in large numbers as well. AFAIK, in the P4 they aren't.
According to Ars Technica the P4 in the real world gets 2.5 instructions per cycle done. With the new G5 getting 8 done per cycle with half the pipeline depth, performance should once again favor the Mac side of the PC wars.
IBM unveils new 64-bit PowerPC microprocessor
The new chip, called the IBM PowerPC 970, is derived from IBM's award-winning POWER4 server processor to provide high performance and additional function for users. As the first in a new family of high-end PowerPC processors, the chip is designed for initial speeds of up to 1.8 gigahertz, manipulating data in larger, 64-bit chunks and accelerating compute-intensive workloads like multimedia and graphics through specialized circuitry known as a single instruction multiple data (SIMD) unit.
"IBM's new PowerPC 970 64-bit chip is all about bringing high-end server processing power to the desktop, low-end server and pervasive space," said Michel Mayer, general manager, IBM Microelectronics Division. "IBM is committed to helping more customers put our expertise in advanced chip design and manufacturing technology to work for them."
The chip incorporates an innovative communications link, or "bus," specially developed to speed information between the processor and memory. Running at a speed of up to 900 megahertz, the bus can deliver information to the processor at up to 6.4 gigabytes per second, to help ensure that the high-performance processor is fed data at sufficient speeds.
All currently shipping Intel and AMD desktop microprocessors internally translate x86 instructions to much smaller instructions that are functionally similar to RISC style instructions.
Why compare it with the Pentium 4 at all?
Wouldn't it more useful and accurate to compare it to compare it to Intel's 64bit Itanium 2?
I guess most of us are more familiar with the P4 but for someone try to choose a platform for a future 64bit app, the choice will be I2, G5 or Hammer. To a great extent, how these compare to their 32bit cousins will be moote if your app actually has 64bit precision or memory requirements.
Just being able to address over 4 GB will be a boon to anyone using CAD or high-end video or graphics, or running a mid-level server. Forget any cache loss loading 64-bit, think no more paging memory to try to get over 4 GB.
All indications are the new CPU has AltiVec which probbably means AltiVec code on it is not slower then non-AltiVec code, and one hopes faster by about the same mesure as it is on the existing G4.
Well they are implmented in Silicon, but somehow I think that is not what you really want to know :-)
The compiler can be given a flag that asks it to gennerate AV code if it can, but I don't think this helps a whole lot because compilers are not that good at finding places to use SIMD instructions. Esp. not in C code (as Cray about that kind of thing some day). One can also hand code the assembly, but that isn't so common these days either. Most people use C compiler extensions that look like normal functions. I beleve normal practice is to write one AltiVec version and one stright line version because the stright line version is faster then pretending to have AltiVec and packing and unpacking results "by hand".
Many of Apples library calls, and maybe OS calls will use AltiVec if your CPU has it. Kind of depends on what you define as "the OS". If the GUI stuff is "the OS" then your set. I don't know if the IP checksum code, or bzero(2) use it or not.
Can you show me a reference on the 28 stage pipeline so I can update my article?
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
Why I got interviewed for a position at IBM about a month ago... They wanted me and a group of 20 other people to write device drivers for "Apples 64bit powerPCs"...
I hope Apple has great plans for this chip...
We're talking about a vapor chip. We can't have real numbers except on real chips. The parent I was responding too had a bunch of purposeful hooey and all I wanted to do was retire it to the jumk opinion pile it deserves to be in.
If we're going to speculate on comparative Ghz numbers, the G5 is supposed to come out sometime next year. That could be June for all we know. Also, Intel might or might not make it to 4Ghz by next December.
It's all a speculative probabalistic cloud with some speculations generating wins for both chips. We'll see in a year but it's very definitely an improvement for the current state of the mac.
Now that
Protoplasm. Quiet Protoplasm. I like quiet protoplasm.
SPEC int2000 consists of gcc, gzip, perl, bzip2, crafty (a Free chess engine), and some other stuff. I happen to be interested in building a computer to run crafty fast, so it's very handy to have good benchmark results for it on recent AMD and Intel CPUs. (Athlons kick P4 butt on crafty, probably because of bit shifts and things like that that P4 is slow on.) Many people would find the gcc, perl, and compression benchmarks interesting when buying a *NIX workstation.
SPEC fp2000 includes Mesa, but only doing software rendering. The other programs are mostly scientific computing apps. (Not just synthetic matrix multiplies or things like that.)
#define X(x,y) x##y
Peter Cordes ; e-mail: X(peter@cordes ,
pentium sounded stupid to me the first 1000 times I heard it.
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