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Grid Processing
c1ay writes "We've all heard the new buzzword, "grid computing" quite a bit in the news recently. Now the EE Times reports that a team of computer architects at the University of Texas here plans to develop prototypes of an adaptive, gridlike processor that exploits instruction-level parallelism. The prototypes will include four Trips(Tera-op Reliable Intelligently Adaptive Processing System) processors, each containing 16 execution units laid out in a 4 x 4 grid. By the end of the decade, when 32-nanometer process technology is available, the goal is to have tens of processing units on a single die, delivering more than 1 trillion operations per second. In an age where clusters are becoming more prevalent for parallel computing I've often wondered where the parallel processor was. How about you?"
To make a brick of these things, or some kind of cube, with massive processing power that one could just carry around and interface with via their PDA?
Just think about carrying around something as fast, if not faster, than your desktop that fits in the palm of your hand.
Edward@Tomato - /home/Edward/ man woman
man: no entry for woman in the manual.
"Qua!?"
A question for anyone with such experience:
I assume it would be somewhat difficult to program efficiently for such systems. I don't mean just getting programs to run, but getting the most bang for your buck. Can anyone here confirm or deny this? Also does anyone know where to find resources on the topic of programming such machines (and no, I am not talking about smp docs or bewoulf docs or even pvm docs)?
Anyone remember from T2 what the CPU looked like? It was a 3 dimentional grid of CPUs...
Don't say I didn't warn you!
Slashdot's rate-of-post filter: Preventing you from posting too many great ideas at once.
This is not an example of the Grid Computing (ala Globus) that we've been hearing about. This is another example of laying out processor cores on a chip. So a better thing would be to compare this to the ideas for the UltraSPARC V and IBM BlueGene computers where multiple processing cores are put on one chip and then arranged in a grid (think physical grid) architecture.
Grid Computing deals with computation and information sharing seemlessy across a network, they used to always say like how the power grid works. Which in reality is about right as it doesn't always work as advertised.
Anyway, Grid Computing is mainly concerned with software to allow multiple computers to work together seemlessly. This includes registry services, single sign of, information transfer, etc.
This appears to be the rather fortunate result of a phenomenon called "Buzzword collision", where two different projects pick the same buzzword in hopes to really confuse people who don't read the articles and trick PHBs into thinking that each project is ueberimportant.
My Slashdot account is old enough to drink...
There are some programming languages designed for parallelism. Biggest hassle is efficiently partitioning problems into something parallel. Not all problems can be done faster by doing more of it at once.
Normally I don't pimp Sun, but here's something that makes me think they still have a finger on the pulse of things:
;-)
Read about plans for Sun's "Niagra" core
I understand they hope to create blade systems using high densities of these multiscalar cores for incredible throughput.
There's your parallel/grid computing.
Fuck Beta. Fuck Dice
I still think this is not what is commonly understood by the term "Grid Computing". Maybe it's the environment I work in but to me Grid Computing means something else
And is exemplified by projects like MyGrid.
I don't read your sig, why do you read mine?
It's funny how people always seem to find a way to confuse what is meant by a "grid". The posting talks about a "4x4 grid" without clarification of the term "grid", which is confusing because grid computing has nothing to do with processing units being lined up in a grid. The "grid" in "grid computing" comes from an analogy with the power grid, not from any form of "grid layout". The analogy is based on the fact that with grid computing, you simply plug your "computing power client appliance" (not necessarily a PC, could be the fridge) into the "computing power outlet" in the wall (a network port, usually), and you can "consume computing power", like you would do with electricity. Computational grids don't even necessarily have to support parallel programs; it is easy to imagine grids that have a maximum allocated unit of a single processor. What makes such grids grids is that you can allocate the power on demand, when you need it, instead of that you have to have your own "computing power generator" (read: megapower CPU) at home.
I use parallel computing on a cluster, in which I divide up my computational domain into a number of chunks, and each chunk is farmed out to a processor. Communication between the processes is required at the chunk boundaries.
For this case, I see how my code is partitioned, and I also understand (on a general level, at least) what the limitations on speed are: information based between the chunks.
Now, how will this processor do its 'instruction level' parallelization? Will it be great at do loops (one 'do' per processer)? Will it be like a mini vector processor? What will break down the efficiency of the parallelization?
I have found that efficiency in parallelization is very application dependent after about 8-32 procesors. Will this break that barrier?
Most importantly, will it kick butt for MY applications?
The article doesn't actually have anything to do with "grid computing", but the processor's design is like a grid. The term "grid computing" often refers to large-scale resource sharing (processing/storage).
The prototypes will include four Trips processors, each containing 16 execution units laid out in a 4 x 4 grid. By the end of the decade, when 32-nanometer process technology is available, the goal is to have tens of processing units on a single die, delivering more than 1 trillion operations per second.
At 32 nanometers, Intel could put tens of HT pentium cores on a single chip, achieving the same result.
"One key question is, Will this novel architecture perform well on a variety of commercial applications?"
For computational problems that can be broken down into parallel computations, the answer is yes. For all the other types of problems, the answer is no. Although I have to admit that most algorithmic bottlenecks is in iterative tasks that are highly parallelizable.
On Trips, a traditional program is compiled so that the program breaks down into hyperblocks. The machine loads the blocks so that they go down trees of interconnected execution units. As one instruction is executed, the next one is loaded, and so on.
*cough* EPIC *cough* VLIW architecture *cough*
I support parallelism and I am looking forward to seeing it on my desktop, as it will increase the computational power of my computer tremendously. Unfortunately, it will mean new compilers and maybe programming languages that have primitives for expressing parallelism.
By the way, the transputer chip was promising. The idea of lots of computational units running in parallel is nothing new(maybe each memory block must have its own processor to locally process and compute the data).
Forgive me if I'm off base here, but perhaps a proccie nerd can explain the differences between this design and say VLIW. They seem closely related, breaking the app into parallelizable chunks and sending them to n execution units. The article doesn't mention if the trips processing nodes can 'talk' to each other. If they can't, then this seems very similar in concept to vliw (if not different in physical and logical layout).
If you want to know more, I'd be happy to consult at $300/hour.
Which is why most of your tech jobs are being shipped overseas.
This story already appeared, but was posted by someone who was not confused by the use of the term "grid"... Doug Burger, one of the two key profs on this project (and no relation!), answered lots of questions, which you can see here.
-- emery berger, dept. of cs, univ. of massachusetts
parallelizing the data-processing itself (Eg Seti@Home) whereby the data being worked on itself is spread amongst 'loosely parallel' execution units is much more practical, and doesn't suffer from the overhead involved in creating parallel processor servers, or even parallel execution chips. It also alleviates the memory bottlenecks of parallel execution cores.
I always wondered what kind of an app demands the kind of big iron that Cray and NEC churn out - that couldn't be more cost effectively realized through distributed processing amongst many independent computers (a la Google).
It seems, even cyclical, result-dependant processing (weather prediction) could be coded to work in such a manner.
1000 bare bones p4 3ghz PCs (~$600) have more processing power ( 2500 MFLOPS each ) than a single X1 cabinet ( 819 GFLOPS @ $2.5M ) and as you can see - for less than 1/4 of the cost.
( 2.55 TFLOPS @ $600,000 vs 819 GFLOPS @ $2.5M )
( p4 MFLOPS hit 5700 each w/ SSE2 )
Now I imagine there have to be exceptions. There -has- to be a reason to have such big iron for certain problems. There must be a reason that very smart people advise their superiors to buy up around $8b of this stuff each year.
but i don't personally see the applications, and given the monumental cost of developing a new processor nowadays - the market doesn't seem to either.
so that's my $0.02 as to why more complex esoteric parallel execution designed chips remain so rare.
// "Can't clowns and pirates just -try- to get along?"
- MIT's RAW project
- Berkeley's Garp architecture
- CMU's PipeWrench
Quite a number of researchers are looking at the performance and density adavantages of reconfigurable architectures in addition to the work mentioned in this article. What's really intriguing is considering how opreating systems could support reconfiguration. Doesn't seem to be much work on the subject.If even with one CPU core, if your system is main memory bandwidth limited (or mostly), then extra cores won't help (much). So this kind of design looks good only for non bandwidth limited tasks, which is a much smaller market.
They don't seem to be considering business servers here, but they are more main memory latency limited than bandwidth limited, so multiple cores can help a lot. But you need more than simply lots of cores to have a good design. A critical thing to have is major software support which means using an existing ISA, not a new one.
So I'd expect this to be quite an obscure product in reality.
In an age where clusters are becoming more prevalent for parallel computing I've often wondered where the parallel processor was. How about you?"
Danny Hillis, the guy who founded ThinkingMachines designed a mchine called The Connection Machine, (this story has a cooler, more sci-fi lookin' pic of the old beastie) the central design philosophy was to achieve MASSIVE computing power through parallelism. It had 65,535 procs, each of lived on a wafer with dram thereon and a high bandwidth connection to up to (if I remember correctly) up to 4 other of the procs. Young sir Danny wrote a book on his exploits, well worth checking out (seemingly, it's been calling to me from my bookshelf for about a year now).
And as someone pointed out, it seems we've seen this topic before. I'd have modded him up, (hint, hint) but I really like mentioning the connection machine where appropriate.
Quod scripsi, scripsi.
This is very much not new. The basic idea has come and gone several times in the last twenty years, to my knowledge. Both SIMD and MIMD systems have been tried several timed. NCR even had one called the Grid, IIRC. Thinking machines (as seen on Jurassic Park I). The Inmos tranputer was designed for exactly this sort of connectivity. Intel had a development machine (?iWarp?) which tried to use it. And I am sure there were others that I don't recall. (As a user and fan of the transputer, I used to follow the field from a distance).
But the problem has always been the programming. Ordinary software does not map very well onto these architectures. Certain specific problems can be mapped well onto them, which results in spectacular performance claims for the system. But generally such systems perform well only on those problems for which they were specifically designed.
Communications is a common reason for failure. They scale very badly. In the early days of development, the first few processors have any-to-any connectivity, so the application will really fly. But since the connectivity rises as the square of the nuymber of processors, this cannot hold for very long. As soon as connectivity becomes limited, communications bottlenecks start to appear, and you get processors being held up either sending messages or waiting for them to arrive. Buffering (which many did not implement in their communications architectures) helps, but itm doesn't solve the problem. (A bit like lubrication - a small amount brings a considerable improvement in performance, but past a certain point, it only adds to costs).
Another problem is load balancing. It is very difficult to design your system so you don't end up with most of the CPUs waiting for one, overloaded, CPU to finish its job. The only architectures which really worked were the farm model - a central dispatcher sends tasks to a "farm" of identical "workers", which therefore request work units as and when they need them. This means that the whole code for the system has to be loaded into each worker; not necessarily a killer at todays memory prices, but it would be nice to be more efficient. It also requires the task to be divisible into a vey large number of chunks, which can executed independently without too much communications. OK for large volume simulations etc., but a disaster for (say) database programming, image/voice recognition.
It also doesn't help that not may people really think multi-threaded in their program design. Again, no-one that I know has a good Object Oriented multi-threading model. Current models are analagous to either pre-structured programming or early structured programming. Which means that people, reasonably, approach multi-threading as a dangerous monster to be approached only whan absolutely necessary, with great care, and if possible in flame-proof armour. For this sort of system to be much use we need a development which does to current threading what inheritance did to pre-OO languages: something that makes is so simple that, one over the hump of initial unfamiliarity, people use it all the time without even thinking about it.
I designed one of the larger heterogenous transputer based system to ship - up to 100 transputers in 6 different roles. Load and communications balancing was a real hassle from the the day the system first started to work for real, and we were constantly tuning buffers, fiddling with routing algoirithms, movong bits or processing from this CPU to that to get the perfomance up. (Not to mention that inmos completely blew their second generation transputer, which we had been hoping would solve many of our problems).
Consciousness is an illusion caused by an excess of self consciousness.
They have some papers available there...
No no no.
Ok, HT double clocks the Cache! so you have two cache's for the price of one! The G5 is a multicore chip so is Cell Linky and The Opteron are all multicore chips, the diffrence (apart for the arch!) is the way VLIW's are feed to each of these. They are NOT paralell processors, paralellisam can be defined as the maintence of cache coherence, it is either inclusive (cray) or excluseive (rs6000), and requries a lot of bandwidth (local x-bar versus network). Where as parallel computers are not cache coherent and have a remote x-bar architechure, it all adds up to the same hypercube.
Die verifacation will be modified to accomidate the core level verifacation prior to multiple cores bieng used. Since you are layering dies on one another they will be verified individually, then as a whole if they do not add up as individuals then off to the scrap heap. But that all depends on the number of cores and process. Keep in mind that currently design sofware limits are around 20K layers of interconnects, so if a core is only 20 layers of interconnects (not uncommon) it's only 100 layers if its scrap and since it's vapor deposition the losses are neglegable (compareable to white noise or pennies on the hundred). Fab's spend more finding problems (and fixing them) than they do on materials. Yelds are much more prone to design flaws and external condition errors than failure due to a singular element (rmember the Pentium Floating Point error due to the capacitors not bieng sprayed at the right density?).
for parallel processing fortran boast many language level features that give ANY code implicit parallelism and implicit multi-threading and implicit distribution of memory WITHOUT the programmer cognizantly invoking multiple threads or having to use special libraries or overloaded commands.
An example of this is the FORALL and WHERE statements that replace the usual "for" and "if" in C.
FORALL (I = 1:5)
WHERE (A(I,:)
A(I,:) = log(A(i;0)
ENDWHERE
call some_slow_disk_write(A(I,:)
END FORALL
the FORALL runs the loop with the variable "i" over the range 1 to 5 but in any order not just 1,2,3,4,5 and also of course can be done in parallel if the compiler or OS, not the programmer, sees the opportunity on the run-time platform. The statement is a clue from the programmer to the compiler not to worry about dependencies. Moreover the program can intelligently multi-thread so the slow-disk-write operation does not stop the loop on each interation.
The WHERE is like an "if" but tells the compiler to map the if operation over the array in parallel. What this means is that you can place conditional test inside of loops and the compiler knows how to factor the if out of the loop in a parallel and non-dependant manner.
Moreover, since the WHERE and FORALL tell the compiler that the there are no memory dependent interactions it must worry about. thus it can simply distibute just peices of the A array to different processors, without having to do maintain concurrency between the array used by different processcors, thus elminating shared memory bottlenecks.
Another parallelism feature is that the header declaration not only declare the "type" of variable
Other rather nice virutes of FORTRAN is that it uses references rather than pointers (like java). And amazingly the syntax makes typos that compile almost impossible. that is, a missing +,=,comma, semi colon, the wrong number of array indicies, etc... will not compile (in contrast to ==, ++, =+ and [][] etc
One sad reason the world does not know about these wonderful features, or repeats the myths about the fortran language missing features is due to GNU. yes I know its a crime to crtisize GNU on slashdot but bear with me here because in this case they desereve some for releasing a non DEC-compatible language.
for the record, ancient fortran 77 as welll as modern fortran 95 DOES do dynamic allocation, support complex data structures (classes), have pointers (references) in every professional fortran compiler. Sadly GNU fortran 77, the free fortran, lacks these language features and there is no GNU fortran 95 yet. This is lack prevents a lot of people from writing code in this modern language. if Gnu g77 did not exist the professional compilers would be much more affordable. So I hope some reader who know about complier design is motivate to give the languishing GNU fortran 95 project the push it needs to finnish.
In the age of ubiquitous dual processing fortran could well become a valuable scientific language due to its ease of programming and resitance to syntax errors
Some drink at the fountain of knowledge. Others just gargle.
Read the article - this isn't the case that you've got a whole bunch of traditional processors and you try and divide the work between them. They're talking about the CPU itself being split into several smaller general units, so that each instruction gets excecuted by several of these units. The instructions are grouped together and then sent to the CPU in blocks. All the work for that block is then split between the units, taking into account any interdependencies. I suppose the closest thing to it would be to have microcode being executed in parallel.
There's a good book explaining a lot of this stuff in detail available from O'reilly. I can vouch for it having some neat stuff, and it covers how to write fortran in such a way as to take advantage of the parallelism features.
I wouldn't put much blame on GNU. Fortran 77 was a fairly unpleasant language, even before GNU existed. Compiler extensions sometimes helped but weren't too great for portability.
Not that I don't want to see a GNU Fortran 95, but if you can tolerate free as in beer software, Intel makes their fortran compiler available for free for noncommercial use on Linux: IFC
There is also the F programming language which is a (mostly) tastefully selected subset of Fortran 95: F. Mostly it just throws out redundant features and stuff inherited from Fortran 77. It's a little picky in a teaching-language sort of way and takes some getting used to, but I have ported code to F without pulling my hair out. And the code did end up a bit clearer for the changes.
I spent 13 years at the Supercomputer Computations Research Institute, an interdisciplinary research institute whose job it was to figure such things out. Amongst other goodies, we had the first CM-2 (a SIMD box with 65536 processors) with floating point chips, at the time the fastest machine in the world. We also had a homegrown machine for quantum chromadynamics. And a cluster with 150+ nodes, and some shared memory machines, yada yada yada. Lots of stuff.
So, from my experience:
It's a little bit tricky to do. Sometimes you find an algorithm that someone abandoned fifty years ago that turns out to map better onto the hardware. However, it isn't all that tricky to do, and there are plenty of algorithms and libraries to make the job easier.
But it still doesn't happen anyway, because even a small amount of work is more than no work at all. And besides, what people want to do is run their old dusty decks but just have them run faster. And in the mean time, Intel has just come out with a faster scalar processor, so why bother?
The only thing I can see coming out of this is if, say, NVidia makes a faster graphics card based on it.