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Strained Silicon Chips From Intel
Quirk writes "NewScientist is reporting...
"Intel has taken the wraps off a secret technique it is using'Strained silicon' chips to increase the speed of its Pentium and Centrino chips. The technique boosts the rate at which transistors switch, without having to make them smaller.""
true, I was going to post something similar, here is the link to IBM's research about Strained Silicon.
I first thought it was the submitter's mistake, but actually the story is taked off the article.
Maybe someone can shed some light here.
The IT section color scheme sucks.
Dupe, Maybe read this 2.5 year old story
we are coming to the ends. for Intel, they need to reduce the leakage or they will not be able to compete.
I am the Alpha and the Omega-3
Indeed, in fact this is of absolutely _NO RELEVANCE_ to strained silicon FETS. Please inform yourself before posting, and consider not posting halve-knowledge.
Note that Intel improved the P channel devices 25% and the N channel devices 10%. Since N channel devices are usually 2 to 3 times stronger than P channel devices, this reduces the difference and makes CMOS design a little bit nicer.
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I spoke with Intel about this in the spring.
Apparently the strained silicon technology came about due to research related to mechanical stress problems they were encountering across the entire chip -- so it already was an issue. Their research solved the mechanical stress problem, and they later realized by intentionally localizing the effect they could basically place the strain at individual transistors to improve performance.
Because the effect is localized and controlled it's no longer an issue of concern, AFAIK.
Heat sinks, etc, shouldn't alter the strain at the transistor level. Remember, we are talking about this at the atomic level, so any macro-level strain like a heat sink would have to be pretty substantial to work its way down into the crystal lattice structure to the point of affecting performance. (Sort of humorous if it did, though, as it would imply microprocessors would go faster if you squeezed them. In reality Intel is actually stretching the size of the normal silicon lattice structure, so heat sink stress (compression) would actually be working against you, but it's also occuring in the wrong axis (the lattice stretching is 2D X-Y, not Z-axis.)
The only way to get 3D straining would be to have a 3D substrate, with the transistor material embedded within.
It seems to me that, in such a configuration, the substrate would interfere with the operation of the transistor.
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There are several new technologies that either are speeding up chips, or will speed up chips, and the best part is that they'll all work together.
For some time, SOI (silicon-on-insulator) has been helping chip manufacturers squeeze out extra performance. And the straining of the silicon lattice (strained silicon) helps as well. And you can combine them into SSOI, strained-silicon-on-insulator.
Well, there's also one other technology that's been developed, called "fully depleted silicon". And guess what - it should/will be possible to make fully-depleted, strained silicon-on-insulator chips. (FDSSOI?)
Between moving to 90 nm, then 65nm, and then further, as well as integrating high-K dialectrics and fully-depleted, strained silicon-on-insulator manufacturing technologies, we've still got a lot of headroom to keep cranking out faster and faster processors. Moore's law has still got a long time to live. And that's even if we don't make any new breakthroughs, but my guess is that the chip makers will continue to pull aces out of their sleeves, so to speak.
steve
Oh, you're not stuck, you're just unable to let go of the onion rings.
There is a difference between understanding and using. Intel has announced that they are using strained silicon in a production environment. The big difference here is scaling the process up. As they mentioned in the article, they have disclosed their use of, but not how their strained silicon electronics are made.
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Since when is Strained Silicon Secret?
The idea of strained silicon is to apply a mechanical stress to the silicon. This will change the spacing between the silicon atoms (the lattice spacing), which will indirectly reduce the channel resistance, therefore allowing faster transistor switching speed.
Indeed, this has been known for a long time, but so far it has not been used in commercial products due to the problems involved with the actual manufacturing of theses devices.
The classical way to manufacture theses devices
is to grow a thin layer of silicon germanium on your wafer. The SiGe layer has a slightly different lattice spacing than silicon. When a silicon layer is grown on top of the SiGe layer it adapts its lattice spacing. Therefore it is possible to grow silicon layers with a slightly different lattice spacing.
This way is persued by IBM and others and is quite expensive.
Intel managed to find a different way. They just build their transistores on common Si-Wafers, but deposit mechanically stressed layers on top of their transistors. This will result in a mechanical stress in the transistor channel and does therefore lead to the same result.
The difference is that Intels method is a lot cheaper (adds only 2% to overall cost), they have all the patents, and it does actually work in a manifacturing process.
I attended a lecture on this topic several years ago. One of our professors used silicon straining to alter the wavelength of LEDs. He had originally noticed how the wavelengths of LEDs of different materials correlates with the interatomic separation in the material. That led him to think whether it's merely the lattice separation, instead of the material itself, that matters.
Escher was the first MC and Giger invented the HR department.
I'd like to know if the lattice could be stretched in all three directions, rather than just one. And if so, would that provide any benefit? Or does the benefit come from that directionality?
It would be stretched in all directions, but usually the thickness is kept as small as possible, so the effect in that direction is minimal. The idea is to increase the carrier mobility between the source and drain, which is mostly a 1-D proposition: the electrons (or holes) flow from the source towards the drain, in as close to a straight-line as possible. Of course, the other 2 dimensions count as well, but not nearly as much as on the plane between the source and drain.