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Chip Power Breakthrough Reported by Startup
Carl Bialik from WSJ writes "The Wall Street Journal reports that a tiny Silicon Valley firm, Multigig, is proposing a novel way to synchronize the operations of computer chips, addressing power-consumption problems facing the semiconductor industry. From the article: 'John Wood, a British engineer who founded Multigig in 2000, devised an approach that involves sending electrical signals around square loop structures, said Haris Basit, Multigig's chief operating officer. The regular rotation works like the tick of a conventional clock, while most of the electrical power is recycled, he said. The technology can achieve 75% power savings over conventional clocking approaches, the company says.'"
Chip Power Breakthrough Reported
By DON CLARK
May 8, 2006; Page B6
A tiny Silicon Valley company is proposing a novel way to synchronize the operations of computer chips, addressing power-consumption problems that are a major issue facing the semiconductor industry.
Multigig Inc., a closely held start-up company in Scotts Valley, Calif., says its technology is a major advance over the clock circuitry used on many kinds of chips.
Semiconductor clocks work like the drum major in a marching band, sending out electrical pulses to keep tiny components on chips performing operations at the right time. In microprocessor chips used in computers, the frequency of those pulses -- also called clock speed -- helps determine how much computing work gets done per second.
One problem is that the energy from timing pulses flows in a one-way pattern through a chip until it is discharged, wasting most of the power. Clocks account for 50% or more of the power consumption on some chips, estimates Kenneth Pedrotti, an associate professor of electrical engineering at the University of California at Santa Cruz.
Partly for that reason, companies such as Intel Corp. have all but stopped increasing the clock speeds of microprocessors, a popular way to increase computing performance through most of the 1990s.
John Wood, a British engineer who founded Multigig in 2000, devised an approach that involves sending electrical signals around square loop structures, said Haris Basit, Multigig's chief operating officer. The regular rotation works like the tick of a conventional clock, while most of the electrical power is recycled, he said. The technology can achieve 75% power savings over conventional clocking approaches, the company says.
A typical chip would use an array of timing loops, in a grid akin to a piece of graph paper, Mr. Basit said. The loops automatically synchronize their timing pulses. That feature helps address a problem called "skew" -- the slightly different arrival times of timing pulses throughout a typical chip -- that tends to limit clock precision.
Multigig says its self-synchronizing loops can run efficiently at unusually high frequencies.
Mr. Pedrotti said past attempts to address the skew problem have tended to increase power consumption. He and his students, some of whom receive research funding from Multigig, have performed simulations that so far back up the company's claims, though the team is just about to start tests using actual chips, he said.
Multigig is in talks to license its technology to chip makers, as well as design some of its own products to use the clock technology. Besides microprocessors and other digital chips, the approach could help synchronize frequencies of communication chips, Mr. Basit said.
"This is a dramatic way of clocking circuits," said Steve Ohr, an analyst at Gartner Inc. He cautioned it could take years to get existing manufacturers to modify existing products to take advantage of the new technology. "Intel is not going to redesign the Pentium tomorrow because of it," he said.
Conventional electronics uses circular loop structures to send electrical signals as the electrons would get caught on corners that were too sharp. These people must have overcome that limitation.
D'oh! Looks like I won't be getting 12 hour battery life on my laptop anytime soon!
So "up to" 75% savings on "up to" 50% of the electricity usage. So 3/8 or 37.5% savings, all in all... Of course this is only for the CPU... Could be noticeable in production... Maybe...
75% thats pretty good
"Intel is not going to redesign the Pentium tomorrow because of it," he said.
Why not? If this works it sounds like Moore's law would continue, and would give whatever company that deployed it first a performance advantage.
Is this really so radical we'll have to wait years to get it on our desks?
We're getting ever closer to the perpetual motion machine, just 25% energy savings to go ;-)
Seriously though, I'll look forward to seeing this new chip in production, since more energy efficient chips means less waste heat, and thus quieter computers with fewer fans. I'll trust it when I see it, I'm not so swayed by a company that is still just a "startup" probably looking to get a boost to its stock price by anouncing a breakthrough.
Oh You POS
" Multigig, have performed simulations that so far back up the company's claims, though the team is just about to start tests using actual chips, he said. "
Given lots of unknown factors that can arise when you're using real electrons on real silicon, I like the idea, but I'll happily wait for the prototype before thinking this would be a net good thing.
Quo usque tandem abutere, Nimbus, patientia nostra?
Most of the power in a computer is used once and wasted. The input to a gate acts like a capacitor. When the input is driven from a zero to a one, the current is limited by the resistance of the output gate driving it. That resistance is where the power is dissipated. The charge is drained to ground when the input is driven from a one to a zero. If there was some way to re-use the charge stored in the inputs, the power dissipation of a chip could be dramatically reduced. There would be a limit to how much efficiency could be gained but we haven't done anything about it yet. One of the major limits to chip performance is heat and doing something like this would help to keep Moore's law valid.
You can't readily adjust the amount of time it takes electricity to make its way around a fixed-size loop. If this is what is actually clocking the chip, it'll have an official frequency (or two, perhaps, for low-power usage) and you'll be stuck with that. The manufacturer would have to throw out, rather than derate, any parts that don't work at that frequency.
First of all, I can barely grasp how chips work in the first place, lots of yes-no-maybe so gates that the electrons have to pass through.
So, would it be possible to make a 3-D chip? Where, instead of one line or branches that the electron follows but a crazy ass network for it to flow through?
"No one will really be free until nerd persecution ends."
Like with asynchronous processors, maybe its downside will be the silicon area required to implement it.
Other techniques like multiple independant clock areas that can be shut down when not in use seem far more beneficial, IMHO.
Open Source Drum Kit, LPLC deve board - mjhdesigns.com
Now, whether it is linear or not, any heat reduction is a Good Thing (tm).
Hopefully we can choose between faster chips at the heat levels we have now, or the same speed chips at a 37.5% reduction in heat (and points in between).
This will go well with the robotic tentacles. Now your berserker can use even less power, reserving more for the really critical things like the LASER (we need a /. article on military LASERS).
It just amazes me that a small, never-before-heard-of-company offers a solution to a problem that Intel, IBM, and AMD have been trying to solve for over a decade, each of which have 10 times the budget, expertise, and personel. Did I mention a headstart of a minimum of 10 years of R&D tossed at this problem? I hate to be a pessimistic troll-like poster, but without even a working proof of concept, I can only call this vaporware until they show me a working product. This article says nothing except "we have technology every computer in the world will need in the next ten years... please invest in us and we'll get you a demo soon."
Are you saying regenerative braking doesn't exist?
The Prius isn't all that uncommon of a car.n g.html
http://www.toyota-hawaii.com/vehicles/Prius/braki
An impossible concept only invented like a hundred years ago. Next, they will be charging things known as capacitors from the induced current.
Is there a technical paper on this? I know it's probably patented and they want to keep as much detail as possible but it seems like a somewhat abstract paper of how this works would convince the chip makers they want to sell this to to be interested. And satisfy curious people like me.
so as always the main question i have about this new chip is.....
how fast will it run DOOM 3?
I share your doubts, but must point out that current hybrid cars already use regenerative braking. The efficiency is only something like 30% (losses to transmit through the CVT, generate, store, spin the motor again), but it's still a little bit of return. Since the motor is already designed to act as a generator, it should be little extra investment to program the transmission to load the motor before mechanically engaging the brakes.
The startup's name isn't BitBoys!
In your average laptop, the power consumed by a CPU when running something (i.e. not just idling around) is about half the total power. The other half, roughly, is consumed by the screen.
The Raven
I've read the FA and despite having a couple of CMOS designs behind me I don't understand a bit of what they are saying. Either the reporter that wrote this has absolutely no idea what he is writing or this entire 'breaktrough' is just vapourware.
The article seems to say that the 'tick' of the clock is carrying energy throughout the chip and when the 'tick' hits the edge, the energy is lost. Electronics in your typical digital circuit does not work that way. Energy does not flow through the chip with the signals (ok, it does theoretically, but that amount is negliable with the dynamic losses in the gates mentioned below).
You get power dissipation in each gate or buffer that changes state because of some signal, irregardless of the direction in which the information is flowing. You can not recycle this power. This comes directly from the basic principle behind CMOS technology (used by almost all digital chips today) - you are charging and discharging a capacitor.
Typical example, that running signals in a circuit does not save power: take a ring oscillator (a number of negators wired in a loop). This circuit will oscillate (send changing signals through its loop) and consume an considerable amount of power.
Is it really that inefficient? The electric motors used in the prius (for example) are reputed to be 85% efficient when acting as a generator, and something like 90% efficient when acting as a motor. Where's the rest of the loss, the charging system?
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
There's nothing inherently stopping you from making a fully 3d chip (existing chips already have many layers) however it's really difficult to get the heat out.
Current CPUs keep the transistors very very close to the heatsink and still struggle to keep them cool. If you had a cube shaped chip then it would be near impossible (with traditional processes).
There are some interesting projects to get miniture coolant pipes running through the chip, but that's a way off.
What a breakthrough
Wow, a chip with that many synchronized, circular clocks is probably going to radiate like a giant antennna...
That'll teach me to preview more carefully in the future!
Sci-Fi Weapons to Join US Arsenal
U.S. Considers Anti-Satellite Laser
The gift of death metal does not smile on the good looking.
Reading the article before posting your first post is cheating... do you hear that... CHEATING!
As the GP mentioned, CVT transmissions (and other parts of the drivetrain) typically have other efficiency losses. (as a quick example... the reason that manual transmissions get higher MPG than automatics is that the torque converter in an auto has high efficiency losses)
Actually, it surprised me, too. I believe the major inefficiency comes from the battery. The number I gave was rounded off from the wikipedia entry (I hate turning to an unaccredited site everytime I need an answer, but it's soooo easy). I will assume the efficiency values you referred don't account for the CVT, which also run 80-90% efficient (compared to 90-95% for geared transmissions). So on these assumptions:
eta(trans) * eta(gen) * eta(charge) * eta(discharge) * eta(motor) * eta(trans) =
0.85 * 0.85 * eta(battery total) * 0.9 * 0.85 = 0.553 * eta (sigma battery)
Where battery total is the total efficiency of the battery-related processes. 0.3 / 0.553 = 0.54. So the overall battery charge*store*discharge efficiency would be on the order of 54%. I don't know if that's reasonable or not, but I suspect there's somebody around here who can enlighten us.
Posit this: if a square loop lets us save 3/4 of the power, shouldn't an octagonal loop let us save 7/8 of the power?
...
Of course, if that's so, then a circular loop
I think I can decrease my gas consumption by up to 75% by throwing square wheels on my car! Of course the reason would be because i would be 75% less likely to use a car that really cant go anywhere.
Honesty may be the best policy, but apparently by elimination, dishonesty is the second best policy.
The problem is the inductor is to small to give you any gain and the positive rail-negative rail drop remains constant. What you really need is a triangle wave power supply so that the waste heat is lowered on chip, and an inductor recovers some energy at the power supply. The chip is just to small. Unless they have created a material with better magnetic specs then ferrite I call BS.
Inventions have long since reached their limit, and I see no hope for further development.-- Frontinus, 1st cent. AD
"Intel is not going to redesign the Pentium tomorrow because of it," he said.
Why not?
For starters the automated design tools will need a rehack.
Current synchronous chips use a "clock tree" to try to get all the flops and latches to clock at once. Then the design tools assume that the outputs flip at the same time and try to route the signals so they all get through the logic to set up the flops in time for the next clock.
This scheme will produce waves of clocking that propagate across/around the chip. So different flops will be clocked at different times. This is good for signals going the same direction as the clocking wave (though not perfect, since the propagation time of a signal on a wire is NOT linear with length), because they get extra time to set up the next flop. It's rotten for signals going the other way.
But it's disaster for design software that doesn't understand the issue.
So new versions of the tools will be needed that can take the non-simultaneous clocking into account, both to compute the layout and wiring right and to take advantage of the effect to achieve improved performance by arranging for timing-tight data paths to "go with the flow" and slower stuff to go the other way.
Even if this hack works, getting those tool mods done, and getting them right, will hold up large projects using it.
(But something can be done meanwhile, with unaware tools, by doing some manual layout of blocks with respect to the clocking waves and telling the tools to treat each block as if it had a simultaneous clock internally, skewed with respect to other blocks and with less setup/hold time margin to take into account the internal skew.)
Bantam Dominique roosters crow a four-note song. Once you've heard it as "Happy BIRTHday" you can't NOT hear it that way
Remember, in advertising-speak, "up to" means "less than". Values between 0% and 75% fulfill the conditions of being "up to a 75% savings".
Weaselmancer
rediculous.
Yes, batteries are the main loss. Also - their charging rate is the main limit on how much power you can recycle from braking.
There's a new lithium ion variant with a nanotube-array electrode that might be a good solution for that. Charges 85% of capacity in minutes, which implies enormous power densities and minimal precentage losses to heat.
(There's also a new lead-acid cell design using graphite rather than lead for the structural support of the plates that makes a similar sort of improvement in lead-acid technology, though it probably get near the same absolute performance as the LiIon version.)
Bantam Dominique roosters crow a four-note song. Once you've heard it as "Happy BIRTHday" you can't NOT hear it that way
Since clocks take up a large percentage of the power and space on the chips, why not do away with them? Why not use a clockless CPU so results are available as soon as they are ready? There are some processors out there (ARM Amulet for instance) that do this, does it just not scale well to the high speeds we are used to now on our desks and laps, or is it just that current clocking cpu design is way ahead in terms of development?
Due to the heat issues you describe, 3D designs probably won't be common for chips until we stop using electrons and switch to photons for computing. At that point, design complexity trade-offs (perhaps a net reduction in circuit paths or increased storage density needs) will probably drive at least some limited 3D structures.
However, one possible solution to the problem you pose would be to design the chips with lots of little holes and pumping fluid through it. A design could be based on a fractal 3D shape (or perhaps simpler designs might work). It really isn't clear what the advantage of this approach would be right now, though, because the limits of the available area on a 2D chip surface are not really the limiting factor.
Skynet will probably know what a fairly efficient design would be.
If you mod me down, I shall become more powerful than you could possibly imagine.
Design sounds similar to the motor in my 84 RX7
It appears basically that they make a clock loop just long enought to get a clock skew of 360 degrees, and connect back to itself.
Now you can get any clock skew you want just by picking the clock off at the right place in the loop.So circuits with a skew requirement must be at just the right location along the ring.
I can see how this can be anadvantage in fast small circuits like an ADC.
How can this be any advantage on a complex circuit? It appears:
0. The clock loop will impose a lot of layout restrictions on the circuit.
1. you will need a tree of these loops just like a clock tree.
2. The IC has a fixed clock. So initial bringup must be done at maximum frequency. What a nightmare that might be.(Note that the only purpose for using this is to enable as high speed and little jitter as possible.) Does it imply a full layout change every time you try to up the clock frequency?
Notice that the Gartner group financial analyst calls it almost a "perpetuum mobile"
"Fix it"
It's a little bit hard to tell from the article (the eetimes one is better), but it sounds like they're using the ring as a resonator to carry the clock. Ring resonators aren't exactly new (especially in my field, waveguide optics), but using them as clocks poses a few interesting challenges. If you extract energy (signal), you're going to damp out the resonator; if you couple multiple loops, for carrying the clock to internal points in the circuit, you need to ensure that the resonator frequencies are exactly matched. Doing this for a couple of resonators isn't hard. Doing it for the hundreds you'd need for a CPU sounds bloody well impossible. You'd have to actively detect and correct for phase error at each coupling point, adding lots of RF analog electronics, which would suck.
What they're talking about souinds a lot like a resonant-mode switching power supply. Except that every single stage of logic would be its own resonant circuit. This would impose design constraints like crazy on the silicon, so I doubt they'd be able to apply it to all the circuitry on the chip. However, this may be practical for smaller parts of the circuit, such as register banks, that show up in many places (so you can reuse the design). The various busses that crisscross the chip won't benefit from this, though, so you'll still have the usual resisitive and capacitive losses in them.
Other posters have pointed out that companies like IBM, Intel, and AMD have been working on reducing power consumption for decades. This is true, however, the kinds of techniques they look for are ones that can be globally applied to the chip, can be modeled with a high level of accuracy (you want to simulate as much as you can, because etching silicon is slow and expensive), and are compatible with available manufacturing processes. A technique such as one in the article would be passed over as having too low a reward for that level of R&D risk and expense, since it can only be applied in such a narrow fashion.
Background: A switching power supply is a power supply that converts from one voltage to another by either switching the voltage (if you're reducing the output voltage) or current (if you're raising the output voltage, which reduces the current) on and off in a repeating cycle, then heavily filtering the output, which averages out the output voltage. Normally, the rate you switch at is fixed, and you lose a bit of power when the switch turns on or off; there is almost no loss when the switch stays on or off because either the current or voltage through the switch is near zero.
One way to reduce switching loss is to set up a resonant wave, so the voltage or current through the switch is near 0 when it switches. This can be accomplished by changing the switching frequency, or by adding in a DC offset to a prefiltered switching waveform. This is much more complex, requires custom controller circuits, and there are patents involved, so only big power-supply companies can do this.
> the current is limited by the resistance of the output gate driving it. That resistance is where the power is dissipated. The charge is drained to ground when the input is driven from a one to a zero. If there was some way to re-use the charge stored in the inputs, the power dissipation of a chip could be dramatically reduced.
Capacitors stores charge (potential energy), not power. To discharge a capacitor, you have to transfer the charge from it to another place. You can do it fast or slow, but you always have to move the full amount of energy. Resistance during discharge causes an instantaneous power loss of P = V^2/R, where V is the voltage across the resistor (this varies with time). Although raising the resistance reduces the power loss, it also increases the time constant. That means it takes proportionally longer to transfer the charge, and your clock rate goes down. And remember that you have to pay the 'conservation of energy' bill sometime: for example, a doubled time constant means the area under the curve is twice as large, so the resistor still consumes the same amount of energy.
Faster clock rate -> lower time constant -> more heat (unless you figure out how to reduce the capacitance).
In the opposite corner we have the asynchronous processing folks who tell us that removing clocking will improve power consumption.
These are at odds with eachother and someone has gotta be wrong. I smell a VC scam.
Engineering is the art of compromise.
In addition to the already cited
t ml;jsessionid=SG3NCFVRB3QWEQSNDBESKHA?articleID=18 7200783
http://www.eetimes.com/news/latest/showArticle.jh
the EE Times piece (in the printed edition not up on the web) has a sidebar,
with neat background on the inventor:
________
Christmas present leads to ratoary wave epiphany
The Rotary Traveling Wave technology was the brainchild of MultiGig Inc.
founder and chief technology officer John Wood, a self-taught inventor
and son of an inventor who developed a method for self-aligning installed
underground water pipes. In a company filled with PhDs, Wood is the only
employee without a college degree.
Wood earned millions from a patent on this technique for flash-welding
plastic materials. His passion for technology drives him to order textbooks
by the dozen when pursuing a new subject, sometimes noting their errors in
scribbled notes in the margins, said MultiGig COO Haris Basit. "I've worked at
research labs including Yorktown Heights and Bell Labs, and John is clearly
a cut above," Basit said.
In the late 1990s, Wood was researching high-speed serial I/O using
traditional ring and crystal oscillators. "As I started to explore alternatives,
the first thing I looked at was transmission times," he said.
An intitial prototype, using coaxial cables, was "not very exciting."
Then Christmas 1998 brought an ephiphany. "My son had just gotten a
car racing game with a crossover on a single track. That gave me the idea
for arranging the transmission line that way," said Wood.
After a few more months of work, Wood decided to use arrays of loops
to create an approach that could work independently of any frequency
or process technology.
"It took a year or two until we could find direct commercial applications.
Before that, I was just working on it as hobby." said Wood. "But the more we
looked at clock distribution, the more we realized this could be useful."
-- Rick Merritt
I read somewhere here on Slashdot as I recall about clockless CPUs and system designs. Why are people still working with clocked computers and technology if clockless holds so much promise?
without loss of generality, please ignore the typos from my
manual transcription (ratoary->rotary + ephiphany -> epiphany)
e.e. times is simply unhelpful in not linking human-interest
sidebars to the relevant web links.
about the subject at hand -- clearly, this cat is bent.
Jot it down in the list of great inventions from start-ups, which big companies have not been able to achieve. I'm sure the big-companies would not have thought out-of-the-box for an approach like this. only start-ups can "afford" to do such a thing ;)
This remind me of low-power reversible computing that I learned back in college from Prof. Jan van de Snepscheut at Caltech... The basic idea is to reduce wasted power by "sloshing" current within the chip, rather than to let the current spill to the ground... (this is a a gross simplification...)
l
This (highly technical) paper describes what I'm talking about:
http://www.zyvex.com/nanotech/electroTextOnly.htm
This article mentions a "helical logic" which sounds a bit like what this invention is...
actually...sharp turns are a problem for high frequency circuits. when the frequencies get very high compared to the wires length, the waves *do* actually reflect back from sharp corners and will favor a straight path. this is the basis for things such as tdr (when finding kinks) and directional couplers.
A better analogy might be, I can propel my ship by having the crew run from the bow to the stern, dive into the water, then swim to the stern again.
Disclaimer: This subject preemptively escapes my brain.
Standard practice on electric railways - there is even one railway in Africa which is a net producer of electricity (shifts ore from mountains to coast).
This is not always true. As one increases the number of humans, one increases the inherent inefficiency.
A more interesting question is whether a thousand people who love their work can do more work than 10 people who ~hate~ one another. (I'll let you know how it turns out. CV available upon request.)
Rich And Stupid is not so bad as Working For Rich And Stupid.
I love the smell of wrong Physics in the morning.
Signals propagate differently when wires are set up as transmission lines - they propagate at much closer to the speed of light, because you're actually sending a wave down the line (imagine creating a ripple on a trough of water, instead of actually filling and emptying the trough).
Last time I checked, speed of electron flow is only based on the material around it. Higher dialectric constant = lower speed of propgaition. Transmission lines aren't voodoo science, they are a property of the electrical length of the line and the rate of change of the signal on that line. It does not change the rate of propagation at all. Whether a given wire is 1" long, or 200 miles long, it will not change the speed of propagation.
I recently attended a seminar where the presenter talked about clocking based on LRC oscillations and he had actually fabbed chips that worked. The basic idea was to put an inductor on the die, and set up oscillations between the inductor and the clock load capacitance, which results in a ticking clock. Of course, you get a sinusoidal clock instead of a nice almost-square-wave, so your circuits have to be designed a little bit differently, but the point is, it works and is doable.
Not to be cheeky, but it's quite easy to change a sine wave into a square wave: Schmidt trigger. While I can't rule this out entirely, I would imagine that if it was more economical to produce an LRC resonator, it would be built into devices already. These circuits have been around for decades. It's very difficult to beat quartz crystals in terms of stability, ease of use, and power consumption.
You're half right. You're right that what's going on is a charging and discharging of a cap, but you're wrong that the charge can't be recycled. A conventional clock works by connecting the gates of a bunch of devices (i.e. capacitance) to Vdd, then after a little time connecting it to ground instead. Wait a little bit, then repeat. What effectively happens is that you dump some amount of charge from Vdd to ground each switch, and it's gone (i.e. it's heat now). A water analogy would be a tub of water above you (Vdd), a bucket in your hand (the capacitance), and the ground (gnd). You pour some water from the tub into your bucket (charge the cap), then dump it on the ground.
Wrong. The clock drives into a high impedance node. (The CMOS receivers on the other side of the clock line). CMOS drivers do have the problem of connecting to ground temporarily during switching - more akin to spilling some of the water out of the bucket as you pour it, not pouring it entirely on the ground. This can be overcome using clocks that are 90deg out of phase. And if the cap that you're talking about is the 10pF or so that is on the gate of the reciever CMOS - there are larger fish to fry power wise than this minimal capacitance. Try taking on the bulk leakage at 90nm before taking on this minimal source of power dissipation.
Nietzsche is dead. --God
Almost all the heat generated in a chip is generated in the resistance that limits the current sourced by the output of a gate. That current is determined by the capacitance of the input of the gate it is driving and the clock frequency. Moving an input from a zero to a one requires a certain amount of charge. The more often you do that, the greater your current.
Almost no heat is generated by discharging the capacitor to ground when the input is driven from a one to a zero.
What tfa seems to be proposing is some way to re-use the charge stored in the input. If you could do that then you wouldn't have to waste energy in current limiting resistances.
A good reference on power dissipation issues is: "High-Speed Digital Design" by Johnson and Graham, pages 39 to 59
sending electrical signals around square loop structures ... the electrical power is recycled ... the technology can achieve 75% power savings
And I thought P = VI.
But of course! I am educated stupid. According to NATURE'S HARMONIC SIMULTANEOUS 4-DAY TIME CUBE, the opposite hemispheres cancel out. Earth exist as 4 - 90 degree opposite corner quadrants, but not to a 360 degree circle...
If they started out round and then became increasingly polygonal as you sped up, until at high speed they were square. You'd have less contact with the road, so less resistance. Handling would suffer (as would ride smoothness, I imagine), but perhaps it would be "up to 75%" more efficient.
I don't have time to read the detail, but your post and the original article's comment about "recycling power" sounds to me like they are using some sort of adiabatic logic approach. Adiabatic logic is well known for significant power reduction, but at least historically it has required significantly more transistors per gate and cannot run as fast as traditional CMOS.
The ring thing sounds like it's just a new clock generation scheme to go with the existing adiabatic logic techniques (which do have rather unusual clocking requirements that are a bit harder to generate than typical single-square-wave clocks.)
retrorocket.o not found, launch anyway?
Last time I checked, speed of electron flow is only based on the material around it. Higher dialectric constant = lower speed of propgaition. Transmission lines aren't voodoo science, they are a property of the electrical length of the line and the rate of change of the signal on that line. It does not change the rate of propagation at all. Whether a given wire is 1" long, or 200 miles long, it will not change the speed of propagation.
I didn't say electron flow speed changes. I said signal propagtion speed changes, which is true, because if I send a "1" down a long transmission line, the receiver will get it faster than they'd get it if I send a "1" using RC-style signalling. As I tried to explain before, in a normal signalling scheme, you charge an entire line up to Vdd or Gnd, and don't detect a 1 or 0 until the signal crosses Vdd/2. Take an empty trough and start filling it up; see how long it takes the water level to reach half way up on the far side. It'll cross the half way point at the far side pretty soon after it crosses at the near side, but actually filling and emptying it will still take a while. With transmission line signalling, however, you never actually charge/discharge the whole line, but send a wave down it instead. Take a trough of water and make a ripple, then on the receiving side observe the ripple. If you want to read a proposal for on-chip transmission lines, read this.
There are a lot of issues involved with using transmission lines (for example, wires have to be long before transmission-line signalling becomes better, and you have to do impedance matching at the receiver to avoid reflections, and based on the paper I linked to, your wires need to be wide and thick), but they do offer some very cool properties.
Not to be cheeky, but it's quite easy to change a sine wave into a square wave: Schmidt trigger. While I can't rule this out entirely, I would imagine that if it was more economical to produce an LRC resonator, it would be built into devices already. These circuits have been around for decades. It's very difficult to beat quartz crystals in terms of stability, ease of use, and power consumption.
I didn't say it was a flawless idea, and I also didn't say it was a stupid idea. I DID say you have to design your circuits differently (i.e. your flip flops do schmitt-trigger-like things to compensate for the slow slew rates). I brought it up because it was an example of charge recovery that works in the real world. It does have downsides, but every option has downsides (be it power, skew, manufacturability, whatever). Based on the presentation I saw, the downsides of that particular clocking method are enough to keep it out of mass-produced designs for a while, but that doesn't mean somebody else might not have found a way to make charge-recovering clocks more realistic. It's worthwhile research (meaning it might not be in the CPU you buy tomorrow, it might not be in any mass produced CPU ever, but it might also lead to a design that IS mass produced in the future, based on the knowledge gained from this research).
Wrong. The clock drives into a high impedance node. (The CMOS receivers on the other side of the clock line). CMOS drivers do have the problem of connecting to ground temporarily during switching - more akin to spilling some of the water out of the bucket as you pour it, not pouring it entirely on the ground. This can be overcome using clocks that are 90deg out of phase.
That's not what I was talking about. Short-circuit current is not a big deal as long as your signal slew rates are good.
And if the cap that you're talking about is the 10pF or so that is on the gate of the reciever CMOS - there are larger fish to fry power wise than this minimal capacitance.
I mentioned only gate cap on the clock receivers to simplify things. Since you're goin
My server
I would say that Grandparent was soundly refuted.
I do security
why the heck are they not trying to recover wasted energy using thermocouples and things like that? my P4HT usually maintains 55-60 C and if the surroundings range around 20-30 C we have 25-40 C diff. someone plz calculate how much voltage that would generate with $25 equipment.
On its first analog-to-digital converter, MultiGig will implement one physical ring with four phases. Taps can be implemented at any point around the ring to gain access to any of the four phases.
I interpret this as they will have 4 "clock" wires, each carrying a square wave with a 1/4 On, 3/4 Off cycle, with each of the wires out of phase (1/4th shifted) with each other. Since the wire arrangement has previously been described as a square, this creates an interesting geometry... Every side of the square (as an aggregate) is charged all the time, but depending how you tap it, you can get 4 separate clock signals. From my work in the bulk electric utility business, this seems like a nice way to electromagnetically couple the wires together to eliminate field losses; when one phase is discharging, the nearby wire is charging at the same rate, which reduces the total losses. There's a reason why high voltage lines are arranged in either a triangle or all three in a line.
As usual, it seems that a useful British invention is being promoted and developed in America.
We still have lots of good inventors, but they either get no backing, or have to go abroad, or either watch their idea dieing, or being exploited by someone else.
It's no wonder our country is going to pot. You need to be on a TV reality show to be successful these days.
Sig out of date
Is this real??? check out the Multigig web site... I noticed that Multigig has multiple papers on their technology. http://multigig.com/publications/DRAFT_ISSCC_2006_ PAPER.pdf
Multigig comments on multiple application use for Clock trees, RF and analog.
I noticed a paper on analog applications at
http://www.oea.com/document/DesignConPaper_04.pdf
but the most interesting is a copy of an ISSCC paper at UCSD?
http://www-cse.ucsd.edu/classes/wi06/cse291-b/slid e/let8/rotary.pdf
"Served", if you will.
There is a good paper on this given at ISSCC 2001 , paper 25.5 it goes over the technical details. I think there are later updates/refinements as well. John also had several bits of the software used for rotary clock stuff out on sourceforge..Dunno if it's still there.
speaking as someone who designs chips for one of those 3 companies, I can tell you, I can think of at least 2 reasons why that won't really work in the ten minutes since I read the (admittedly light on details) article.... when you actually have to fab things and put them in systems you learn alot.