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Intel's 3D Transistors One Step Closer to Reality
An anonymous reader writes "Reducing power consumption is the name of the game in today's semiconductors and Intel today described its tri-gate transistor technology as one of the key technologies that could free the company from the trap of thinner gate insulators and increasing current leakage. Tri-gate (three gates instead of only one) could reduce the power consumption of transistors by 35% right now and drops off-voltage - one of the main sources of current leakage - by 50%. These results are the good news. The bad news is that tri-gate won't be available until 2009."
Is there a difference, or is Intel just calling it by a different name? (FinFET diagram: http://www.future-fab.com/assets/images/FF19_wp_pa rton_fig1.gif)
Intel.. now 3 times cooler than AMD!
-DaMouse
As I am reading it this really isn't a 3D technology at all, it's more like three normal planes of circuitry stacked on top of each other. Of course I know why they haven't been working on a truly "3D" implementation: even though it would cut down the distance on average between any two gates moving heat away from the inside of the structure would be exceedingly difficult, while on a 2D chip getting rid of heat from anywhere is relatively easy (large surface area / volume).
Philosophy.
"These results are the good news. The bad news is that tri-gate won't be available until 2009."
Are you in a rush?
I don't think the bad news is that bad. This technology doesn't exist in any cpu's currently. 3 years doesn't sound bad to me... my 2c's anyway
How 'bout that. Intel has invented the pentode.
Lacking <sarcasm> tags,
First off, these are field effect transistors, which they don't specifically mention (although they do use the correct terminology for FET's.)
Secondly, it's not really that they have three gates. It's that they have a block of silicon that can conduct from source to drain, and a gate in the middle of it that can deplete/enrich the adjacent silicon to change its conductivity. Where most FETs have the gate on one surface, or 1/4 of the conduction channel's surface area, this one has a gate that stretches around 3/4 of the channel's surface area. Instead of gating like stepping on a hose, this gates like clamping the hose with pliers (for analogy = depletion-mode). Pretty cool, but that should come with a 3x increase in the gate's capacitance, shouldn't it? and fighting capacitance is one of the major struggles of increased speed, right? People doing very low-power stuff should love this. People doing high-speed design, maybe not so much.
Nostalgia's not what it used to be.
At least compared with the new silicon nanowire transistors developed last month. But well, we have to start with something :)
Tunnels sound very interesting. Leakage presumably has many causes, but would boil down to electrons leaving the desired path and going elsewhere. There MAY be ways of replacing the interconnects (which are usually just regular conductors) with superconductors, as superconductors should leak a lot less. (Resistance is a function of leakage, and superconductors have zero resistance.) This won't fix links on the silicon itself, but any improvement would be a good thing.
It's a small world and it smells funny; I'd buy another if it wasn't for the money; Take back what I paid (SoM)
Not really a problem. The transconductance of a transistor is actually proportional to the charge induced in the channel, which in turn is proportional to the gate voltage (limited) and the capacitance. In other words, you aren't going to get more gain without also getting more capacitance. In other words, for a given gain the capacitance is the same, but the leakage is less. [1]
The other reason this isn't a problem for low power is that interconnect capacitance is much greater than gate capacitance for practical circuits.
[1] Size isn't much affected, because so many other features are much larger than the channel. Contacts and required spacings, for instance.
Lacking <sarcasm> tags,
I feel like I'm playing Super Mario Brothers, & I just found a warp zone.
Wanna fight ? Bend over, stick your head up your ass, and fight for air.
I don't exactly expect much from their first, second, third, or any effort.
People get confused with just how damn long it can take to turn the first development of a new idea in to an actual product.
Look at Nanotubes. We STILL don't have any commercial produciton using Nanotubes going on and it's been about 15-20 YEARS in the making (depending on which start point you take). It started in 1985 with the discovery of fullerenes, the carbon buckyballs you hear about. Nanotubes themselves were orignally discovered in 1991. Since then there's been a lot of development in their uses and in their production, but still we do not see products on the market with them. I've a feeling we are getting close, but it's still years off.
That's just how it goes. There's a long time between something first being mesed with in a highly theoritical research context and it being something that we are all buying. It can be decades, hell it can be longer. How long have we been after fusion as a power source? 40 years? Maybe, MAYBE in another 20 we have it? Research is often not a fast process, it just takes lots of time trying things, learning, trying again, etc. It's not always osmething money can accelerate, sometimes it just takes a lot of time to do everything you need, sometimes you have to wait for development in other areas to make yours practical.
Either way, Intel's announcement is exciting for consumers because it's approaching the consumer level. Sounds like in 3-5 years we will be using thigns based on this. The GP's technology is neat, but nothing consumers should care about since at this point there's no prospect of consumer application. Perhaps in 10-30 years it'll be something to look at, but not now.
"But we ought to remember that no exponential is forever. Your job is delaying forever." -- Gordon Moore at a 2003 Conference
Didn't AMD already do this? They must have been REALLY far ahead of their time.
I am not an electronic engineer, but surely having three gates in a FET doesn't qualify a transistor as Three-Dimensional. If Intel had created a cube chip with connections along all the three dimensional axes, we could call the transistor 3D, and that's not the case here.
Your ad could be here!
AMD makes press release.
Intel makes press release.
Other than the timing, is there much difference at all?
I don't see Intel making a bigger or smaller stink than AMD, just at a different time.
AMD definitely knows what they are doing and so does Intel. It's not surprising both companies are working on similar things.
http://lkml.org/lkml/2005/8/20/95
http://www.sciencedaily.com/releases/2005/05/05050 9102339.htm
Yes I know they were thermionic and not solid state, but the physics is much the same.
Since there is a HUMUNGOUS mount of prior art and this is "OBVIOUS TO ALL SKILLED PRACTITIONERS IN THE ART" provided they are over the age of 50, I hope they have not been given a patent for this.
Sent from my ASR33 using ASCII
I don't why we should refer to a tri-gate transistor as a "3D transistor". Truely three dimensional integrated circuits have multiple layers on the silicon substrate, so as the laying extends vertically as well. I know only one company that was doing this, Matrix Semiconductor, Inc, and they claim to be the pioneers of the 3-D integrated circuits. http://www.matrixsemi.com/. They are now acquired by SanDisk, Inc.