Could HP Beat Moore's Law?

John H. Doe writes "A number type of nano-scale architecture developed in the research labs of Hewlett-Packard could beat Moore's Law and advance the progress of of microprocessor development three generations in one hit. The new architecture uses a design technique that will enable chip makers to pack eight times as many transistors as is currently possible on a standard 45nm field programmable gate array (FPGA) chip.""

Comments

Moore's law is not about inefficient FPGA intercon

[chriss]

Since the wiring in an FPGA is not fixed, they have to integrate more flexible ways of routing. According to TFA this takes up 80% to 90% of the silicon, leading to a much worse ratio of wiring to transistors dedicated to logic processing compared to "normal" chips. HP is developing something they call "field programmable nanowire interconnect (FPNI)", which consumes a lot less space. So they are not beating Moore's law, they improve chip space use in FPGAs to become similar to what todays dies with fixed routing achieve.

And even if you are desperately seeking more efficient FPGA, you'd have to be patient. TFA mentions that they are targeting a 25-fold increase packing density compared to todays 45nm chips in 2020. That's thirteen years, which in Moore's laws steps means about eight 18 month periods, each doubling density. My math may be flawed, but shouldn't that mean that by then we have 2^8 = 256 times the density in the normal process as we have today?

Why a law

[gravesb]

I never understood why it was called a law. It was an incredibly accurate prediction, but there was nothing holding is there. I would think that any dramatic increase in technoloby would lead to a jump larger than Moore's law.

Re:Why a law

[fitten]

It's a prediction and actually a self-fulfilling one, to some degree. In fact, it's as much, or more, about economics than technology. If you look, the original wording even states "cost". Upgrade too fast and you'll go broke because people won't upgrade with you that fast (they'll start skipping 'generations' in their upgrades).

Re:Why a law

[Colonel Angus]

Sounds better than Moore's Prediction?

Re:Why a law

[Junior J. Junior III]

I'm waiting for the /. article in which it's announced that some school board has declared that Moore's "Law" is really only a Theory, and should be taught alongside "intelligent design" courses which demonstrate how highly specialized researchers and engineers colloqually known as "gods of tech" design and build denser integrated circuit chips using computer assisted methodologies. These things don't manifest out of the ether, and they don't evolve themselves, people.

Moore's Law

[shirizaki]

http://en.wikipedia.org/wiki/Moore's_law

The number of transistors on an integrated circuit for minimum component cost doubles every 24 months.

Wait a second...

[awing0]

HP has research labs? Honestly, I thought they were an ink company. Damn, and I was getting quite used to mocking their "Invent" logo.

The Singularity is Near...

[PHAEDRU5]

Moore's "Law" is actually a prediction that's been remarkably accurate.

I think, though, that's what happening here is employing the technology is causing positive feedback loops in the design and development of the technology, which is accelerating the improvement of the technology.

It's only going to get faster from here. Human consciousness executing on "silicon" by 2030.

Welcome to the singularuty.

Re:The Singularity is Near...

[Stefanwulf]

I understand why we can't predict the weather.
I understand why we can't _predict_ brain function.

I don't understand why that means we can't build a new brain that will simply remain equally unpredictable.
Just because a system is chaotic doesn't make it impossible to construct.

Re:Moore's law is not about inefficient FPGA inter

[quarrel]

Xilinx is the worlds largest producer of FPGAs.

Their biggest customer? Cisco. (by far)

The big iron routing guys use heaps in high end devices.

--Q

Math says: yes.

[Just Some Guy]

The mean value theorem shows that if the average rate is x, and the instantaneous rate ever goes below x, then it must necessarily also be above x sometimes. Put another way, progress will sometimes be faster than other times.

Re:Math says: yes.

[MicktheMech]

The mean value theorem: Because common sense just isn't good enough for mathematicians.

6 to 1

[guysmilee]

As a rule of thumb i was told ... an fpga normally uses 6 gates to 1 gate used by a custom ASIC chip ... so a 5 million gate chip would require a FPGA with 30 million gates ...

This may have changed over the years ... but i'd like to know how this announcement changes this heuristic ...

Re:6 to 1

[guysmilee]

No true ... because of timing requirements ... if one gate is used it may rule out using others because of how the gates are connected ... i.e. picking one gate and 1 route may not allow certain gates to be connected ... so the 6 to 1 ratio refers to "wasted gates" ... I believe. This is because all gates are not all directly connected to each other ...

If this new technology allows more routes ... i believe you will get less gate waste ...

I am just a software dev ... so i could be wrong though ... but this is my understanding ...

Re:6 to 1

[dextromulous]

i.e. picking one gate and 1 route may not allow certain gates to be connected ... so the 6 to 1 ratio refers to "wasted gates" ... I believe. This is because all gates are not all directly connected to each other ...

FPGAs use lookup tables to simulate gates: See here for a description of a basic Configurable Logic Block

If this new technology allows more routes ... i believe you will get less gate waste ...

This is true. However, it is more important than simply wasting gates. Performance of an FPGA is related to how much delay the signals are subject to from input to output. By cutting down on the number of gates used solely to pass on a signal, you are cutting down on the amount of unnecessary delay.

Re:6 to 1

[imgod2u]

This is only true of some FPGA's. Xilinx, in particular, uses look-up tables to simulate logic (along with dedicated flip-flops). Actel, however, has a fine-grain architecture that uses basically a matrix of configurable (solid-state, flash-based) 3-input, 1 output tiles that very much resemble gates. Upon configuration (done once), a high voltage (higher than normal core or IO voltage) is applied and fuses the interconnects in these tiles to behave like the particular gate/flip-flop it's suppose to be have like.

Re:6 to 1

[imgod2u]

No. Contrary to popular belief, ASICs don't utilize all of the gates they have either. There are limitations (even more so) in ASIC-land where you only have so many metal layers on top of your silicon to route your interconnects. Granted, a human being laying it out by hand is much better than an auto-router, but there will still be waste. The same is true of an FPGA and the general rule is that you never utilize more than 70-80% of your available logic resources. This way, there is some flexibility the auto-router has when placing and routing your logic.

The 80-90% number that the article mentions is in absolute gate number (not equivalent gate-number that your custom logic running on the FPGA would use). So basically, if you design a 4-bit counter that requires, let's say, 20 gates. An FPGA will need roughly 200 real gates (each gate requiring certain number of transistors) to simulate this because it must be able to not only simulate that 4-bit counter but a large set of combinations of interconnecting those 20 gates.

This would take that routing network that is currently done by transistors, and move it into the interconnect. This is an interesting move in that it is the first (IIRC) time that interconnects have been used to perform logic (which is really what a switch fabric is) rather than to simply connect logic. An interesting side-note is that back in college, I had a professor researching into using interconnects (wires) alone to do logical operations without transistors at all. I wonder how that's going.

2008

[mastershake_phd]

HP Engineers Defy Moore's Law, New Nano-Chip Prototype in 2008

They havent even made a chip yet.

Re:Moore's law is not about inefficient FPGA inter

[TheRaven64]

Anyone who wants a low-volume run of custom chips. For runs up to a few thousand, FPGAs are cheaper than ASICs (and have the advantage of being firmware-upgradable). If you don't need latest-process speed or power efficiency then FPGAs are likely to be good enough. Take a look here for some of the people who use them.

Mixed legal priorities...

[__aaclcg7560]

Maybe HP should focuse on beating the illegal wiretapping case before they break another law? They're not Microsoft, you know.

What? What?

[Mike1024]

OK, the actual paper's here (full text freely available).

As far as I can tell this has nothing to do with standard processors and everything to do with FPGAs.

It seems what they propose is: Instead of the FPGA configuration bits being done with gates on the silicon wafer, why not perform configuration by configuring the metal-to-metal interconnects? After all, if the metal layers are thick compared to the interconnects between them, you can blow connections you don't need like blowing a fuse. By removing the FPGA configuration bits from the silicon wafer, they can save a lot of space, leading to higher speeds and lower costs.

They have a clever way of arranging such a system, which should be easy to fabricate.

What Moore's law is supposed to have to do with this I don't know.

Michael

Of course

[Billosaur]

If they wait for it in a dark alleyway with a lead pipe and stay very, very quiet...

For instance, the Open Graphics Project

[Lonewolf666]

See http://wiki.duskglow.com/tiki-index.php?page=Open- Graphics.
The development board is going to use a FGPA, because a custom chip design would be too expensive. For later, they plan to produce it as ASIC to improve the price/performance ratio. With better FGPAs, they could stick to the FGPA for the end-user version which would help to reduce investment costs.
Quote about the ASIC design:

RTL for the ASIC will be released under a dual license (GPL and proprietary) There will be a time-delay on some parts (to deal with investor concerns over the $millions necessary to invest in fabrication), but once the investment is recouped, the code will be released. (We need a law firm to escrow the RTL for us, pro bono.)

Re:Obilgatory

[AKAImBatman]

Can You Imagine a Beowulf Cluster of These?

Yes, actually.

The RPU is a fully programmable ray tracing hardware architecture, with support for programmable material, geometry and lighting. The RPU combines the efficiency of GPUs with the advantages of ray tracing. The instruction set of the RPU is GPU like, which is optimal for shading purposes. In addition the RPU supports fast ray traversal through an k-D tree using a dedicated hardware unit and recursive function calls, usefull for recursive ray tracing. To increase efficiency always 4 rays are handled in a packet and multi-threading allows for high utilization of the hardware units.
 
A working prototype of this hardware architecture has been developed based on FPGA technology. The ray tracing performance of the FPGA prototype running at 66 MHz is comparable to the OpenRT ray tracing performance of a Pentium 4 clocked at 2.6 GHz, despite the available memory bandwith to our RPU prototype is only about 350 MB/s. These numbers show the efficiency of the design, and one might estimate the performance degrees reachable with todays high end ASIC technology. High end graphics cards from NVIDIA provide 23 times more programmable floating point performance and 100 times more memory bandwidth as our prototype. The prototype can be parallelized to several FPGAs, each holding a copy of the scene. A setup with two FPGAs delivering twice the performance of a single FPGA is running in our lab. Scalability to up to 4 FPGA has been tested.

BTW, am I the only one who thinks it darn cool that the SaarCor team does their work in JHDL rather than VHDL or (ugh) Verilog? I wonder if the RPU is also JHDL?

FPGA and Moores Law?

[Stevecrox]

I thought FPGA's were a common microcontroller that *could* be altered to run as a microprocessor. You can configure FPGA's to run as a micro-controller and you can get microprocessors to act like a microcontroller but they are not the same thing. Most FPGA's run at far lower clock frequencies and far lower transistor density's when compared to your desktop CPU. This isn't because one is better than the other its because they are designed for different purposes, getting more transistors on a chip is great for your smartphone but doesn't mean much for your desktop.

I just don't see how this would would allow for moore's law to be broken. The largest FPGA I have been taught about (and gotten to use) had 22,000 transistors on it, I thought your average CPU was supposed to have billions.

Re:FPGA and Moores Law?

[Colourspace]

Hi, I work as field apps for a large FPGA manufacturer. The interconnect lengths count for a large proportion of the delay between each configurable logic cell (LE in our terminology), so a shortening in interconnect is not only useful from a transistor count view, but also an upper performance limit view. As for the first poster the larget current FPGA's (Altera's StratixIII, Xilinx Virtex 5 series) have multiple millions (sorry can't be bothered to look up the exact figures) of transistors. However, the flexibility of an FPGA is not that it can just be configured like a Microprocessor (though it can, see Altera's NIOSII) but to act like almost any digital logic you wish to conceive of. Want a FFT function? Don't write it in C/C++, describe it in hardware - much much faster than code, and getting on for an order of magnitude or more faster than on current DSP chips. To do the this, the simplest architecture element is a Logic Element (in Altera technology at least) - this usually (but not always, different vendors have their own twist on these) consists of a 4 input look up table and an associated programmable logic register. Combining a number of these LE's through the routing can create sequential or purely combinatorial logic functions. On top of this many hardware vedors also include special blocks for on chip RAM or ROM, and commonly now DSP multipliers. Of coures, RAM/ROM and muolts can theoratically also be built from discrete LE's but this can be inefficient so dedicated blocks are used. The latest Altera StratixIII family uses ALM (Arithmetic Logic Units) which are slightly larger than an LE but allow more functions to be implemented in one ALM than an LE, potentially reducing the number of logic levels to privide any given funtion, and in turn this can increase system througput and therefore performance. The current larget FPGA announce is the StratixIII EP3S340, which contains 340K equivalent LE's or if you prefer 340K programmable registers (for simplicity). You should ignore exact gate count comparisons between vendors as these are usually marketing figures. Some will include the gates used to configure the FPGA as well as usable ones accessible for use as general logic funtions, so can skew the figures somewhat.

Re:FPGA and Moores Law?

[AKAImBatman]

The largest FPGA I have been taught about (and gotten to use) had 22,000 transistors on it, I thought your average CPU was supposed to have billions.

You are seriously behind the times, my friend. Xilinx's smallest offerings provide ~20,000 gates, while their largest offerings offer millions of gates placed on a chip of over 1.1 billion transistors.

22K transistors is solidly inside CPLD territory these days. :)

Re:FPGA and Moores Law?

[greenrom]

FPGAs are not microcontrollers. They are programmable logic devices. You can use an FPGA to implement a microcontroller, a microprocessor, or any other logic device.

You probably wouldn't be able to put the latest Xeon processor on an FPGA, but to say that they are far slower and smaller than modern processors is incaccurate. There are plenty of FPGAs that can handle signals in excess of 1GHz, and a 22,000 transistor FPGA is a VERY small FPGA.

Many custom chips including custom processors are first developed and tested on FPGAs before they become ASICs. In fact, you can give your FPGA design files to an IBM or a TI, and they'll gladly turn it into an ASIC for you -- for a fee. Often times, FPGAs are used in designs without ever going to an ASIC. Generally, the only reason you build an ASIC is because the per chip cost is much cheaper. Heat and performance are usually secondary considderations. There is, however, a big up front cost to doing an ASIC, so for low volume parts or designs that might need to be upgraded or fixed later, FPGAs are generally the better option.

There's also a middle ground -- so called "hard copy" FPGAs. This is when you give your design files to Xilinx or Altera with a big check, and they sell you special FPGAs that are guaranteed to work with your design (but not necessarily other designs). In exchange, you get the chips a lot cheaper and they can also disable parts of the chip your design doesn't use to reduce power consumption. The FPGA manufacturers benefit by being able to sell chips that would otherwise be defective but are suitable for certain designs.

Re:Moore's law is not about inefficient FPGA inter

[zeldor]

there are lots of uses for FPGAs in radar processing, image recognition, you can even do small
floating point kernels REALLY fast on FPGAs if done correctly.
granted on most of them you have to know verilog or vhdl to use them, but there are a couple
companies that have fully functional C/Fortran programming environments that take it all
the way down onto an FPGA. using those general codes can run faster on FPGAs.
plus they are really low power. a room full of general computers running a teraflop
takes large amounts of power, fpga based systems take 1/20th or so the watts.

Moore's Law is part marketing hype

[macurmudgeon]

One of the reasons that Moore's law has so accurately predicted the continual doubling of storage and speed is that it offers companies an excellent guideline for product roll-out. It's a self-fulfilling prophecy. Customers expect computers to get more-bigger-better-faster at that rate, so companies have a production target. That provides a much more stable product ecosystem than one that is marked by a punctuated equilibrium of sudden large advances followed by unpredictable periods of status quo.

HP Breaking Yet Another Law

[virtigex]

Those scoundrels at HP are doing it again. They probably managed to do this by tapping Moore's phone line or something.

Re:So, high ink price is explained

[Overzeetop]

Then how come Epson hasn't found a cure for cancer, solved world hunger, and figured out how to bring peace to the world? God knows they charge enough for ink to do all of that in a fiscal year (well, at least 2 out of 3, and the last one probably involves nuking from orbit, just to be sure).

Wow this is great news...

[jeffeb3]

Soon we will have even faster, smaller prototype use graphics calculators with horrible user interfaces! SWEET.

Engrish

[hotdiggitydawg]

A number type of nano-scale architecture developed... Mi scusi? No habla Engrish... Seriously Taco, got editing skills? The whole summary is a direct cut-and-paste of the first paragraph of TFA, grammatical errors and all. Perhaps "A number of types of nano-scale architectures developed..." would've made more sense.

Re:Moore's law is not about inefficient FPGA inter

[bforsse]

So they are not beating Moore's law, they improve chip space use in FPGAs to become similar to what todays dies with fixed routing achieve

Agreed, but if the article were titled "HP Enables Increase in FPGA Logic Density", it would have never made it to a slashdot headline.

Re:Moore's law is not about inefficient FPGA inter

[Tatarize]

Roughly, other advancements... multi-cores etc. We should keep pace with Moore's law. It is a rather stupid suggestion. Every time one of these stories comes along they always suggest they are beating Moore's law, when really they keep pace.

New Wammy Co. method for silicon fab... this is going to double the speed of our computers and crush Moore's Law! It should be on the market about 18 months from now!