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Could HP Beat Moore's Law?
John H. Doe writes "A number type of nano-scale architecture developed in the research labs of Hewlett-Packard could beat Moore's Law and advance the progress of of microprocessor development three generations in one hit. The new architecture uses a design technique that will enable chip makers to pack eight times as many transistors as is currently possible on a standard 45nm field programmable gate array (FPGA) chip.""
Since the wiring in an FPGA is not fixed, they have to integrate more flexible ways of routing. According to TFA this takes up 80% to 90% of the silicon, leading to a much worse ratio of wiring to transistors dedicated to logic processing compared to "normal" chips. HP is developing something they call "field programmable nanowire interconnect (FPNI)", which consumes a lot less space. So they are not beating Moore's law, they improve chip space use in FPGAs to become similar to what todays dies with fixed routing achieve.
And even if you are desperately seeking more efficient FPGA, you'd have to be patient. TFA mentions that they are targeting a 25-fold increase packing density compared to todays 45nm chips in 2020. That's thirteen years, which in Moore's laws steps means about eight 18 month periods, each doubling density. My math may be flawed, but shouldn't that mean that by then we have 2^8 = 256 times the density in the normal process as we have today?
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I never understood why it was called a law. It was an incredibly accurate prediction, but there was nothing holding is there. I would think that any dramatic increase in technoloby would lead to a jump larger than Moore's law.
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HP has research labs? Honestly, I thought they were an ink company. Damn, and I was getting quite used to mocking their "Invent" logo.
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Xilinx is the worlds largest producer of FPGAs.
Their biggest customer? Cisco. (by far)
The big iron routing guys use heaps in high end devices.
--Q
The mean value theorem shows that if the average rate is x, and the instantaneous rate ever goes below x, then it must necessarily also be above x sometimes. Put another way, progress will sometimes be faster than other times.
Dewey, what part of this looks like authorities should be involved?
As a rule of thumb i was told ... an fpga normally uses 6 gates to 1 gate used by a custom ASIC chip ... so a 5 million gate chip would require a FPGA with 30 million gates ...
This may have changed over the years ... but i'd like to know how this announcement changes this heuristic ...
HP Engineers Defy Moore's Law, New Nano-Chip Prototype in 2008
They havent even made a chip yet.
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Anyone who wants a low-volume run of custom chips. For runs up to a few thousand, FPGAs are cheaper than ASICs (and have the advantage of being firmware-upgradable). If you don't need latest-process speed or power efficiency then FPGAs are likely to be good enough. Take a look here for some of the people who use them.
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Maybe HP should focuse on beating the illegal wiretapping case before they break another law? They're not Microsoft, you know.
OK, the actual paper's here (full text freely available).
As far as I can tell this has nothing to do with standard processors and everything to do with FPGAs.
It seems what they propose is: Instead of the FPGA configuration bits being done with gates on the silicon wafer, why not perform configuration by configuring the metal-to-metal interconnects? After all, if the metal layers are thick compared to the interconnects between them, you can blow connections you don't need like blowing a fuse. By removing the FPGA configuration bits from the silicon wafer, they can save a lot of space, leading to higher speeds and lower costs.
They have a clever way of arranging such a system, which should be easy to fabricate.
What Moore's law is supposed to have to do with this I don't know.
Michael
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If they wait for it in a dark alleyway with a lead pipe and stay very, very quiet...
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Hi, I work as field apps for a large FPGA manufacturer. The interconnect lengths count for a large proportion of the delay between each configurable logic cell (LE in our terminology), so a shortening in interconnect is not only useful from a transistor count view, but also an upper performance limit view. As for the first poster the larget current FPGA's (Altera's StratixIII, Xilinx Virtex 5 series) have multiple millions (sorry can't be bothered to look up the exact figures) of transistors. However, the flexibility of an FPGA is not that it can just be configured like a Microprocessor (though it can, see Altera's NIOSII) but to act like almost any digital logic you wish to conceive of. Want a FFT function? Don't write it in C/C++, describe it in hardware - much much faster than code, and getting on for an order of magnitude or more faster than on current DSP chips. To do the this, the simplest architecture element is a Logic Element (in Altera technology at least) - this usually (but not always, different vendors have their own twist on these) consists of a 4 input look up table and an associated programmable logic register. Combining a number of these LE's through the routing can create sequential or purely combinatorial logic functions. On top of this many hardware vedors also include special blocks for on chip RAM or ROM, and commonly now DSP multipliers. Of coures, RAM/ROM and muolts can theoratically also be built from discrete LE's but this can be inefficient so dedicated blocks are used. The latest Altera StratixIII family uses ALM (Arithmetic Logic Units) which are slightly larger than an LE but allow more functions to be implemented in one ALM than an LE, potentially reducing the number of logic levels to privide any given funtion, and in turn this can increase system througput and therefore performance. The current larget FPGA announce is the StratixIII EP3S340, which contains 340K equivalent LE's or if you prefer 340K programmable registers (for simplicity). You should ignore exact gate count comparisons between vendors as these are usually marketing figures. Some will include the gates used to configure the FPGA as well as usable ones accessible for use as general logic funtions, so can skew the figures somewhat.
You are seriously behind the times, my friend. Xilinx's smallest offerings provide ~20,000 gates, while their largest offerings offer millions of gates placed on a chip of over 1.1 billion transistors.
22K transistors is solidly inside CPLD territory these days.
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FPGAs are not microcontrollers. They are programmable logic devices. You can use an FPGA to implement a microcontroller, a microprocessor, or any other logic device.
You probably wouldn't be able to put the latest Xeon processor on an FPGA, but to say that they are far slower and smaller than modern processors is incaccurate. There are plenty of FPGAs that can handle signals in excess of 1GHz, and a 22,000 transistor FPGA is a VERY small FPGA.
Many custom chips including custom processors are first developed and tested on FPGAs before they become ASICs. In fact, you can give your FPGA design files to an IBM or a TI, and they'll gladly turn it into an ASIC for you -- for a fee. Often times, FPGAs are used in designs without ever going to an ASIC. Generally, the only reason you build an ASIC is because the per chip cost is much cheaper. Heat and performance are usually secondary considderations. There is, however, a big up front cost to doing an ASIC, so for low volume parts or designs that might need to be upgraded or fixed later, FPGAs are generally the better option.
There's also a middle ground -- so called "hard copy" FPGAs. This is when you give your design files to Xilinx or Altera with a big check, and they sell you special FPGAs that are guaranteed to work with your design (but not necessarily other designs). In exchange, you get the chips a lot cheaper and they can also disable parts of the chip your design doesn't use to reduce power consumption. The FPGA manufacturers benefit by being able to sell chips that would otherwise be defective but are suitable for certain designs.
Then how come Epson hasn't found a cure for cancer, solved world hunger, and figured out how to bring peace to the world? God knows they charge enough for ink to do all of that in a fiscal year (well, at least 2 out of 3, and the last one probably involves nuking from orbit, just to be sure).
Is it just my observation, or are there way too many stupid people in the world?