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AMD Multi-Core G3MX DRAM Interface Details Emerge
MojoKid writes "New details have emerged regarding AMD's upcoming G3MX technology. The 'future Opteron Platform' AMD mentioned in their press release
seems to be built around a CPU currently codenamed 'Hydra'. Hydra will
still feature an on-die memory controller, but unlike current platforms it will
be geared for DDR3 memory. The processor will interface to one or more
G3MX chips, which
in turn provides the interface to the memory slots. G3MX will act as a memory port extender for the memory controller in the CPU socket and a serial link to the RAM.The electrical signaling between the memory controller and G3MX is based on HyperTransport 3.0."
I didn't even know there was a DDR2. But then again, I'm not a dancing japanophile idiot.
DDR2 has been out for a while though, and AMD makes most of its chips in Germany, not Japan.
Dance, idiot.
Looks like a mini northbridge - just memory and no PCIe or AGP or anything else.
I wonder what the latency hit is going to be with lots of them on a server and moving data from one branch of a tree to another?
BR> I guess if they don't deviate from HT3 spec too much lots of other applications could emerge for this chip, with the inclusion of partnerships to bring DSP's and other accelerators / CPU alternatives to the server line this is turning more and more into Lego.
I think this AC was referring to that weird Japanese game with coloured circles on the ground, trying to be funny or just having no clue at all.
This is Slashdot. Common sense is futile. You will be modded down.
Apple?
You can't talk about Wikipedia's flaws on Wikipedia
Translation: "We've taken some moderately new technology and repackaged it with buzz words to make you think you need it."
can i play halo 3 on it?
When did that start?
It'll be interesting to see if AMD actually get to deliver this technology before they run out of money (http://uk.theinquirer.net/?article=41700)
Despite the propoganda they are not pure angels and Intel is not pure evil either.
Maybe so, but thats not the point. I just dont want to see the mainstream PC processor market to become a one-horse race. If AMD had not been there, Intel would probably still be making P4s clocked at 1ghz today.. Having said that, I dont think AMD can take Intel head on - they are right to (or need to) find other niches..
"A nation that forgets its past is doomed to repeat it." - Churchill
this concept seems quite sensible.
They are using G3MX chips as a sort of multiplexer and connecting it to the CPU though a couple of lanes with high-speed signaling.
Internal logic within HYDRA CPU will have the capability to use either conventional onboard memory controller and drive the DDR-3 RAM directly or when socketed within board with G3MX extenders, use that same lines for communication through the G3MX.
Since the load on the lines will be much smaller and constant and since all lines are unidirectional, each line will be capable of much higher signaling speed, so they will be able to use 4x as much RAM as before per CPU node.
If that is not enough, several Hydra CPUs could be connected through HT links- just like now with existing Opterons.
CPU-G3MX connection is much more direct and probably need not to use extra cycles for node addressing, unlike conventional internode communications through HT links, so time overhead could be considerably smaller...
Also, compared to FB-DIMMs, when accessing to some RAM bank here user only pays some throughput penalty (if any), but doesn't suffer much extra latency- with FB-DIMMs data hos between the modules and each hop costs one clock, so access time for 4-th module is longer than to the first one in a group.
Not to mention that GMX-3 chip could host some L3 cache if needed in some later implementation and that combined speed of all G3MX chips is probably greater than existing solution, so interesting effects could be achieved with meory interlieve.
It could very well be that such combination could have distinct speed advantage even in many workstation applications...
...for the day when processor and memory will come in one piece.
Is it just me or does this product seem to be an alternative to using expensive DIMMS using normal grade DDR3 memory rather than using expensive FB-DIMMS like intel does on their enterprise hardware and also increasing the amount of slots per system since you have a more ideal fanout with the memory split up like its shown in article?
I don't know what it is, but I know I need me some of that Hypertransport 3.0.
Now if I just had some more mana, fiery kernite and tritanium, I could build a time machine.
You are welcome on my lawn.
Just an fyi -- the new chip, code named Barcelona, is not K10. It is a K8 derivative, with changes about equal to the change from Thunderbird to Palomino in the K7 days. The Inquirer, bless their hearts, decided to start calling it "K10" just like they decided to start calling the dual-core K8 "K9" with no prompting from AMD.
So you are an Intel cheerleader...why not just be honest for once and admit it?
Ah, so that's why Apple is using Intel chips? That's why the MacBook and MacBook Pro is such a good notebook? That's why AMD got that behinds kicked when Intel released the Core/Core2 chips? Go read some benchmarks, kid.
"Free software" is a matter of liberty, not price.
Apple was talking about going to x86 useing intel cpus back when AMD was kicking intel a** and at the same time as the AMD VS Intel law suit came out. Also at the same time amd MB's had and still better on board video then what apple was and still is useing in there there systems. Back in the G5 days apple was useing AMD's HT bus and the g5 with pci-e had pci-e lanes then the mac pro.
Apple should be useing better on video then gma 950 or a real video card in all systems.
"P4s clocked at 1ghz today"
Yeah, like Intel does not want to compete with PowerPC or other ISAs eh?
One of the main driving forces in the 90s and still today for Intel has been to beat the RISC ISAs.
Something bugs me about the chart in TFA.
:-)
It shows 13 lanes outgoing and 20 lanes incoming to each G3MX unit.
And then it references hypertransport. However, hypertransport is a duplex standard. It can transfer data 20GB/sec in each direction per 32bit link.
So how am I to interpret this.
Anyway, supposing that each of those 3GMX units is anything at all similar to an 32-lane HT3.0 protocol, we're talking 80GB/sec of memory bandwidth per processor. That's just nuckin' futz!
C//
The Real Question is how much less time will my renders take compared to not having a G34X! chip?
Don't wait! Death is for you!
...
Supposely killed by:
* Intel Conroe 45nm in 2008Q1
* rival ppc970, clean 64 bit architecture of high performance computing, present in PS3, XBox360, G5,
I used to be a huge fan of the AMD CPU architecture. Clearly a better, faster, more product compared to Intel
But over the years there has been so much splitting and fragmentation of the architectures from both companies and I hardly know what I'm getting anymore. Too many cute names and not enough information about what they are really doing. It would have been a lot better for both companies if they just made three lines of CPU and left it at that
Of course, my choice for the simplified structure would be:
- Notebook class: emphasis on power consumption
- Workstation class: emphasis on a cheap ass POS that is affordable but limited (original Celeron)
- Server class: dims the lights in most major cities trying to get that extra squeeze of performance because it's all about performance
But they've got way too many variants right now for me to have a clue what I'm actually getting.