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Low Voltage Is Key To Energy-Efficient Chip
An anonymous reader writes in with news from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designed by researchers at MIT. It's said to be able to run on 1/10 the power of current chips. Texas Instruments worked with MIT on the design, which is maybe five years from production. "The key to the chip's improved energy efficiency lies in making it work at a reduced voltage level, according to... a member of the chip design project team. Most of the mobile processors today operate at about 1 volt. The requirement for MIT's new design, however, drops to 0.3 volts."
But how well does it overclock?
That's why your cell phone has an ARM CPU and not an x86.
Engineering is the art of compromise.
aparently from the Bureau of Slowly and Painfully Working Out The Obivous.
i could live a little longer in this prison
You don't use resistors in CMOS logic. You take a transistor and wire source to gate. This turns it into a constant load, more or less the equivalent of a resistor of 10-100K ohms.
.7 is a common one and thus used in a lot of texts, but it isn't set in stone.
The activation voltage of a transistor is variable- it's a property of the materials its made of.
I still have more fans than freaks. WTF is wrong with you people?
In Germanium the voltage is 0.3, if I remember correctly. So it depends on the materials used.
My work here is dung.
In this case, they're operating the transistors in a sub-threshold voltage environment. A full channel never opens for the transistor, but energy will trickle through at different rates.
Instead of the typical "open/closed water pipe valve" model of the transistor, imagine having a leaky bucket, and then determining 1 vs 0 on how many drops get through.
It's a tough area to design circuits in because of the very delicate balance. It doesn't take many electrons (or much process variation) to bust up your circuit.
If they can just get this thing down to zero volts, this chip will run forever!
With the latest hardware and fully integrated chipsets, you can already build an incredibly power efficient system for as low as 20watts idle, and yes, it will perform better than the VIA platforms. Here's one example.
It's very simplistic to say that with voltage drops comes power efficiency - process geometry and materials play a part here too (and I'm not even going to mention the issues with noise tolerance and problems with SSO - Simultaneous Switching Outputs at the 0.3v level). So called 'current' (90nm) geoms are a nightmare for power leakage due to the the relatively small atom thickness that goes to make the gate of the switching transistors. You need to look at such tricks as gate oxides and other power mitigating technologies... BTW - When I say 90nm is current, I know people are doing 65nm, 45nm, 32nm and beyond (which are, given process geometry/power efficiency/newer techniques slightly better in some ways) but the lower geoms are slightly ahead of the curve somewhat..
Sure some CISCs have a RISC under the hood, but that just means you need to have a "virtual machine" that emulates a CISC on top of the RISC. Those extra layers mean more internal operations which mean more switching.
Engineering is the art of compromise.
> who the hell still uses BJT's?!?!?!?!?
:) You can get 2N3904s for 3c each, so it doesn't bother me if I accidentally let the smoke out of one. FETs are much more expensive, are easy to fry if you aren't extra careful to ground before touching, and are present in far fewer circuits you can find online. Then there's the fact that my old Horowitz and Hill only has one chapter on them and so I am just not as familiar with their properties. Eventually, when I'm a "God of circuit design", I'll probably use lots of FETs too, just like the big guys...
Pretty much everyone who uses them for fun
Of course I just knew some jackass was going to use this fact to try to downplay the achievement. Okay, yeah, every computer engineer knows that to reduce power by four you drop the voltage by half, but the trick is actually making this work. That's why not every chip runs on 1E-20 Volts, Mr. Anonymous Idiot.
The enemies of Democracy are
There have been 150-200mV microcontrollers (pdf) at the University of Michigan for some time now: http://wimserc.org/research_highlights/Submiminal_Processor_Research_Highlight.pdf Conference paper 3: http://vlsida.eecs.umich.edu/resource.php?grp=1 what is new is TI and MIT are involved in a commercial low voltage product. But thats still 5 years out. MIT is good at getting press.
Power consumption in a digital circuit can be approximated by the formula:
Pavg = N*f*C*Vdd^2 + Pleak
where N is the probability of a gate switching during one clock cycle, f is the clock frequency, C is the average gate capacitance, Vdd is the supply voltage, and Pleak is the power loss due to current leakage. Since power is proportional to the square of the voltage but directly proportional to everything else, reducing the voltage has a much greater impact on total power consumption. Going from 1V to 0.3V implies a >10x dynamic power reduction.
Visit the
TFA isn't very techincal, and makes it sound like the MIT team isn't doing anything very interesting (they mention 8-transistor SRAM cells, but even regular CPUs sometimes have to use them). The interesting story here is that the chip is being operated at a voltage below the voltage where the transistors are normally viewed as being "on". In this region, transistors operate more like amplifiers than digital switches.
One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage.
Another cool thing is that the chip can actually operate at the low voltage. It's not too hard to make a chip retain state at very low voltages, but as soon as you want to do anything you usually have to raise the voltage back up before execution resumes. Any task that requires a small amount of work frequently will benefit from something like this. A contrived example of where this make a big difference is in a poorly-architected MP3 player in which the CPU has to shuffle a few thousand bytes per second to a sound chip, but in very small chunks (this poorly-architected sound chip has a very tiny buffer), hundreds of times per second. A normal chip would be constantly jumping to a high voltage and going back to sleep; depending on how long the voltage transition takes, it might have to stay in a higher voltage state constantly. This chip, on the other hand, could operate continuously at the "sleeping" voltage.
The catch is that transistors operating in the subthreshold regime are going to be pretty slow, so for any tasks that require high performance you'll have to bump the voltage back to a more normal range.
My server
You need to buy them in bulk. For example, Intel will sell you about 500 million FETs for only $200.
self correction/clarification: in subthreshold leakage current beings to become more important, eventually you stop gaining from dropping the voltage. That can be well into subthreshold, I've seen chips which run at 0.2V (a 45nm process has a threshold on the order of 0.5V). I didn't mean to imply that any drop into subthreshold was self defeating.
Power = Current * Voltage
To reduce power consumption, you either have to reduce the voltage or the current.
While your formula is right, it's not too applicable for chip power usage because current is not a constant. The formula you will normally see is
P = P-switching + P-leakage
Now, P-switching = fCV^2, so you can reduce it by reducing the clock frequency, voltage, or the number of transistors. But, P-leakage actually increases exponentially as the gate threshold voltage is reduced -- so, reducing the voltage too much will not help, either. There's only so far you can go before leakage power becomes the dominant one and reducing voltage further doesn't help.
Never underestimate the bandwidth of a 747 filled with CD-ROMs.
"One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage." leakage is more dependent on threshold voltage than Vds. running a chip subthreshold means you are relying on leakage to charge up capacitance. we've had this research going on for years at MIT.
Contrary to popular belief, voltage is *not* power. To use the analogy properly, what this article says is closer to "low horsepower key to better gas mileage". Which, while still obvious, is at least not a tautology.
It is possible for a low voltage system to transfer more energy than a high voltage one in the same amount of time if the low voltage one transfers more current (current is measured in amps, not volts). The exact relation is volts * amps = power (in watts). So if this chip ran at lower voltage but needed more amps, it could still use more power.
main(c,r){for(r=32;r;) printf(++c>31?c=!r--,"\n":c<r?" ":~c&r?" `":" #");}
From what I can remember from my Low Power VLSI class...
1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance.
2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor).
3. This substrate current ends up contributing to massive amounts of leakage current.
I couldnt resist - the handy eq. from my VLSI Design for Deep submicron book says something along the lines of
Isubstrate =u0*cox*(w/l)*Vt^2 *e^((Vgs-Vth )/n*Vt)
u0 : carrier mobility
Cox: gate oxide cap
w&l: transistor dimensions
Vt : thermal voltage
n : some tech parameter
Vgs: Voltage between Gate and Source
Vth: Threshold Voltage
Dear God, how did this get modded Informative? The parent is confusing CMOS logic with NMOS logic (you do NOT use static loads with CMOS logic), and FETs do not have a parameter called "activation voltage".
For a description of CMOS logic that's actually accurate, check out the wikipedia article here:
http://en.wikipedia.org/wiki/CmosYou are correct about power lines. The high voltage / low current reduces power lost due to the resistance of the wires. When you're dealing with long pieces of wire, the resistance adds up. Integrated circuits, however, are very small and though they are made of semiconductors (which are generally more resistive than metals) resistive losses aren't the big concern. In a semiconductor the important things are electric fields and charges moving about. Making a transistor work at low voltage means there are smaller potential barriers involved for charges to cross.
Basically, anyway.
It's also a property of the doping levels of the silicon. Basically, you need to bring a certain amount of charge under the channel to turn the device on. This depends on the substrate material, but also depends on how much charge is available (i.e. doping).
In a given process, you can different flavors of transistors, each with its own threshold voltage. In a 90nm process I'm currently designing in, the digital devices have a threshold of about 250mV. Of course, I'm an analog designer, so that just make my work harder. :) We would normally design with 0.6V threshold devices. The digital devices are faster, but the analog devices have much more gain. But you can't design with higher threshold devices below about 2V. We're at 1.5V, so we need the lower threshold devices.
The ultimate goal of science is to unify all forces of nature to a single law that can be silk-screened onto a T-shirt.