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Scientists Pave Way For 25nm CPUs
arcticstoat writes in with word that scientists at the Space Nanotechnology Laboratory at MIT have found a new way of extending Moore's law into the future — they have succeeded in etching a grid of 25nm lines into a silicon wafer. The article notes that this technique could be used for writing the grid on which chips are laid down, but that the electronic elements would have to be written using more complex techniques. "[Researchers] created an interference pattern using light from a laser with a wavelength of 351 nm. The pattern consists of alternating light and dark zones repeating every 200 nm. This allowed them to etch 25-nm lines into a silicon wafer, each 175 nm apart. They then repeated the process three times, each time shifting the interference pattern by 50 nm and etching another 25-nm groove. The resulting grid has alternating 25-nm stripes and grooves..."
Let see - 10Ghz chip running at 1.2V
and my DSL broadband still at 800kbps on a good day.
25nm is nothing to write home about, companies are already planning for 25nm. What's exciting is that they created a feature that was smaller than the wavelength of the light used to etch it. Had they used 400nm light to create a 45nm feature, would the title have been "MIT breakthrough could lead to 45nm chips!!!"?
Or were they just figuring they'll invent it eventually?
. . . Can it run Linux?
ASML already has working tools for 32 nm litho. 16 nm is planned in next couple of years.
http://www.asml.com
Altera (www.altera.com) are one of the many silicon companies announcing 42nm devices shipping in the next year or so. Xilinx fanboys - I'm sure they promise the same (picture an AMD/Intel bunfight if you will) - though I must confess I am friendly towards them as an ex employee of sorts, I am certain they are not the only ones proposing to produce devices at this process node in the near future. Intel and IBM being very much at the front of the curve, so to speak. The gap between theoretical limits being announced and actual manufacturing at the announced node seems to be getting a lot shorter. Is quantum really next, or is optical? As we get down to 32nm and beyond the so called 'moores law' (which seems only to really serve journalism as such ;) ) seems to really, genuinely be nearing the limits. What IS next after silicon transistors on a die? Gallium is supposedly running out (due to flat panels) and that's only a doping chemical for speed, still in the silicon domain, not a real sea change of technology. Whats going to happen to the size/power curve? Even multicore processors will suffer as long as they are still roadmapped out on the same substrate. Are we really running out of time now? I don't really hear of the 'next big thing' in any form other than conjecture at the moment..?
I've laid floating lines 1 nm apart with my boat in the past. 25 nm could be done if you wanted but that's getting pretty far apart. Who wants this grid, and why the heck would you use a laser to create light and dark zones every 200 nautical miles?
They kept the chips the same size, but imprinted smaller, thus getting like a 4 times more powerful chip, instead of having the same size of power in something that might snap in to when pressure is applied to it.
The process of making smaller features is only a small fraction of the problem in producing 25nm (or smaller) Si-based electronics. Left aside quantum effects, which start to dominate at length scales smaller than 10nm, stability and electrical leakage through the gate are the most significant problems. When Intel went from 65nm to 45 nm, it wasn't just a "shrinking" process, but an all new use of materials design had to be used to deal with the gate current leakage. In simple words, the silicon oxide insulator was just too thin not to leak. The new metal high-K (Hafnium-based) is the major step that allowed those chip to be made. This research is good, but it solves only a small fraction of the difficulties the electronics industry faces in dealing with Moore's law.
I think the only way to win is not to play.
You can create much smaller lines than the wavelength of your light. You use tricks for that, but that's how it is done at Samsung, IBM, Intel, etc. for ages.
Everyone keeps mentioning Moore's Law and all the problems that go with it. Why isn't there anyone to stand up to him so that we're finally free of his damn limiting laws?
Oh wait, that kind of law. My bad.
A 25nm CPU implies that its transistors can have a 25nm channel length. From the article, it sounds like they can simply make parallel lines, not transistors.
Using this technique, would everything have to be separated by 175nm? This would still make an extremely fast transistor due to the smaller dimensions, but it would take up a large amount of space (usually less space implies faster due to smaller capacitances--hence more transistors per unit area is faster). Also, how would this work with a mask? All transistor channels would have to be aligned, and the mask would only block light perpendicular to the channels? That's not very nice.
As stated earlier, this is interesting because they etched a feature smaller than the wavelength of the light.
Though Gordon Moore certainly developed his law around the silicon chip, the interesting thing about his law is that it is retroactive and not restricted to silicon, leading to the possibility that even if there is a real limit to silicon, something else will come along to replace it and keep the law going through another iteration. Whether that turns out to be holographic, 3-D, biological, or whatever is anyone's guess at this point.
If you start out with the Hollerith census counting machines developed for the 1890 census (the ones that used cards the size of dollar bills because they had a bunch of dollar bill boxes, hench the size of the punched card and the 80-column screen), then move to electric relay switches, then to vacuum tubes, then to transistors, then to silicon, the whole thing is an exponential curve with a doubling every 18-24 months.
Every time I hear someone saying, "We're eaching the end of Moore's Law," I think: Not.
How about a moderation of -1 pedantic.
More like etches the way for 25nm CPUs
Moore's Law is not in any way tied to miniaturisation of chip features, as the clueless ones seem to believe.
Somebody better get on that if we're getting to 5nm feature size.
Help stamp out iliturcy.
First, IAALE (I am a lithography engineer) working on Intel's 22nm process technology. Let's clear up a few misconceptions:
1) The name of a logic node is directly related to the size of the features being made. Those names (e.g. 65nm, 45m, 32nm, etc.) used to relate to the "half-pitch" of the minimum pitch that was printed. But that is not true today. 65nm used a minimum pitch of ~200nm, 45nm used ~140nm and 32nm is using ~100nm. The next node, 22nm is slated to use minimum a pitch of 72nm. The features discussed in this article have a pitch of 50nm, which would be equivalent to the node after 22nm, i.e. 16nm.
2) It's not hard to print features smaller than the wavelength of light. For the lens based systems we used, the Rayleigh criterion gives the minimum pitch possible: 0.25*lambda/NA, where lambda=wavelength (193nm) and NA=numerical aperature (1.35 for the best lenses). So 72nm is the minimum pitch, already much smaller than the wavelength
3) I hate to break it to these researchers, but interferometry has been used for a looong time to make gratings. Search for "interferomety lithography" on Google Scholar. The fourth link is called "Nanolithography using extreme ultraviolet lithography interferometry: 19 nm lines and spaces". That paper is from 1999. And they did that one exposure, not three (using a smaller wavelength).
You would actually need at least one more exposure to divide the grating into something that resembled a logic circuit. The technique in this artcle is not practcal for a number of reasons, but we can do better than them using pitch-doubling techniques and only two exposures.
You mean like a Virtex II-Pro?
Yes, I can. I think this technique is based on research described here:
Darks Physics Beats Light Limit
Paper:
Resonant Interferometric Lithography beyond the Diffraction Limit
All this so we can fit another 10 or 20 cores that programmers won't use... Or was that too bitter?
"...Well, there's egg and bacon; egg sausage and bacon; egg and spam; egg bacon and spam; egg bacon sausage and spam..."
Here is a perspective on the size of these 25nm stripes and grooves. If a cross-hatch of these stripes and grooves done both vertically and horizontally each had a pixel of a picture placed on it, then the number of high definition 1920x1080 pictures you could fit in just one square millimeter would be 20.833 pictures wide by 37.037 pictures high, for an average of 771.605 pictures per square millimeter ... a half minute of video at 25 fps. For the metric challenged, that's 529.166 pictures wide by 940.741 pictures high, for an average of 497808.642 pictures per square inch ... over 4.6 hours of video at 30 fps.
now we need to go OSS in diesel cars
I think a better way to win would be to get the other guy to not play. Maybe a well-timed kick to the groin would do the trick?
This will help us to get into the resolutions which will make graphene come alive for us. After all, its semiconductive properties only begin to happen at scales of 10nm or lower. I'm eagerly awaiting the graphene age to commence.
I think the only way to win is not to play.
I think the only way to win is not to play.
Would you like to play a game of chess?