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Intel-Micron Joint Venture Develops 25nm NAND
Ninjakicks writes "IM Flash Technologies is a joint venture between Intel and Micron that is targeted for producing NAND flash memory. With a focus on R&D, IMFT has doubled NAND density approximately every 18 months. Tomorrow IMFT will announce the launch of their 25 nanometer NAND technology — a major advancement in the semiconductor industry. Intel and Micron can now lay claim to the smallest production ready-semiconductor process technology in the world. IMFT took members of the press on a tour of the new 25nm fab and it's an interesting view into this bleeding-edge manufacturing process."
This is sorely needed to bring down costs for SSD's. The price and capacities available are coming down at a disappointingly slow pace.
If it's only 25nm, how do you use your hand?
Oh! NAND. Gotcha.
APK quotes people (including myself) without context and should not be trusted. Just thought you should know.
Thats not the case if you use a high-fraternity flux capacitor. I've heard the prazatonic implementation of intergalactical space bizanium will allow you to propate the quadraceptic meld process down to 0.2nm.
This has nothing to do with Intel's CPU monopoly (which is only really a monopoly in a fairly narrow segment of the CPU market), it has to do with Intel putting a lot of money into process technology. Even when their designs were inferior to AMD's, they remained competitive because they could fab them on a better process and so get higher yields, higher clocks, and lower power consumption for the same chip than AMD.
Intel's SSD products work with anything with a SATA controller, be it ARM, x86, PowerPC, SPARC, or some custom architecture you just wrote to an FPGA. They are not tied to CPUs in any way. NOR flash often is. You quite often get some NOR flash attached to ARM chips for execute-in-place programs, such as the Symbian kernel and apps, freeing up some of main memory.
NAND flash can only be accessed as a block device, so you can't tie it to a CPU at all easily; it has to go through some kind of controller so the OS can pretend that it's a disk. I suppose you could slap a load of DRAM and a separate MMU and DMA controller on it and have something that would look like a big blob of RAM, but the performance characteristics would be horrible to work with.
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Integration and hardware costs keep the cheapest hard drives somewhere around $40 (for new stuff). Someone will be tempted to play in that space with a $20 SSD, at which point people will get out their fingers and determine the per GB cost of the $20 drive and be very unhappy with larger drives that cost much more than that.
Also, in 2007, they were ~$7.50 per GB:
http://www.engadget.com/2007/04/25/ssd-prices-in-freefall-wont-overtake-hard-disks-anytime-soon/
Vs less than $3 today (just google it). So the prices haven't come down quite as much as the article predicts, but there are 11 months left in the year, and I made that calculation using an intel drive (which probably carries a slight premium to the market).
Nerd rage is the funniest rage.
Fair warning, I didn't read through the whole article, but in general:
No, this won't be directly applicable to CPUs. Microprocessors and memory are two vastly different beasts, on the manufacturing side. Memories are arrays of of the same thing, over and over - neatly organized, same size devices, requiring the same power supply and same operating characteristics. Microprocessors have many different structures, different size transistors for different things, different power supplies, different signaling levels to turn on some transistors and not others. The relative simplicity - really, the relative uniformity - makes memories easier, because you don't have to worry (as much) about balancing the effects of the shrink and the method to shrink across several elements. What's good for some might be bad for others, so the fewer elements you have, the more leeway you have.
That's not to say that this won't have anything to do with CPU development, it's all very inter-related But you can't just start making microprocessors of this dimension because you have working memory.
Even when their designs were inferior to AMD's, they remained competitive because they could afford to paid off dell, HP, et al.
Fixed.
Sent from my PDP-11
Much more to the point, NAND can tolerate a very high defect rate in the individual cells, whereas a CPU can tolerate almost none (with some defects you can disable a core or some of the cache and still salvage the part). Further, NAND gates operate much much slower than CPU transistors and their operational results are checked against error correcting data. A CPU transistor doesn't have that luxury.
in the olden days, xx nm really meant feature size. With Intel and other fabs pressing mfg to half the size every 2 years, it seems mfg has gotten quite creative in their definition of feature size. Latest feature size is a fraction of the wavelength of the light used for patterning, and to achieve it, double and sometimes triple patterning is used. That is basically multiple exposures with slight offsets. The result migh be called 25nm but might really be 50nm, and edge sharpness when you are at 1/4lambda is so suspect that you really have to add some margins here and there, and some features dont really lend themselves to double and triple patterning, so you really have a mix including 50nm process for these.
Kind of like a marketing gimmic, just here it is engineering selling it as 25nm to their own marketing departmens.
don't cut it off www.mgmbill.org
I hate to correct you here, but equilibrium is dependent upon factors of e, therefore the propation must be the 4th Fibonacci value derivation of the meld process.
You're joking, right? I thought everybody knew that Fibonacci values were bilaterally stochiocentric and corrupted the Van der Waals stress index at the third integral. How are you going to poststratify the gnomon clatch that way? Gods you're such a n00b.
Do not mock my vision of impractical footwear
How are you going to poststratify the gnomon clatch that way?
I use a hammer for that.