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Samsung Develops Power-Sipping DDR4 Memory

Alex writes with this excerpt from TechSpot: "Samsung Electronics has announced that it completed development of the industry's first DDR4 DRAM module last month, using 30nm class process technology, and provided 1.2V 2GB DDR4 unbuffered dual in-line memory modules (UDIMM) to a controller maker for testing. The new DDR4 DRAM module can achieve data transfer rates of 2.133Gbps at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30nm-class process technology, with speeds of up to 1.6Gbps. In a notebook, the DDR4 module reduces power consumption by 40 percent compared to a 1.5V DDR3 module. The module makes use of Pseudo Open Drain (POD) technology, which allows DDR4 DRAM to consume just half the electric current of DDR3 when reading and writing data."

5 of 152 comments (clear)

  1. Good news by del_diablo · · Score: 5, Interesting

    Now, lets pair this with a ARM core and hope we get a reasonable hack that allows a wireless that does not eat power like the current ones.....
    Then lets enjoy our ARM-puter: Portable, powerful, and battery for more than a day of use.

  2. "Power Sipping" by Aboroth · · Score: 5, Insightful

    Does anyone else besides me hate that term?

  3. Re:How much power comparatively? by PatPending · · Score: 5, Funny

    Didn't you read the title of the summary? It doesn't "chew," it "sips."

    --
    What one fool can do, another can. (Ancient Simian Proverb)
  4. Meh by lennier1 · · Score: 4, Insightful

    I'd rather have them finally mass-produce 8 and 16 GB modules for the desktop market.

  5. POD explained by overshoot · · Score: 5, Informative
    In a classical open-drain connection, the active device pulls down and the bus termination pulls up. For a pure transmission line, this works just fine -- the current wave from the turn-off of the driver is effectively identical to the current wave from the turn on. In practice, open-drain uses more static current than a push-pull driver against a center termination and since the line isn't a pure transmission line (lumped capacitances, stubs) the rising edge is slower than the falling edge.

    POD addresses this by actively pulling up at the beginning of a rising edge, then releasing the pullup to avoid a bus contention later. This reduces the termination current (at some cost in impedance mismatch, but it's already a sloppy line) and improved switching symmetry.

    --
    Lacking <sarcasm> tags, /. substitutes moderation as "Troll."