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New Manufacturing Technology Enables Vertical 3D Transistors
MrSeb writes "Applied Materials has taken the wraps off a new etching system meant to turn vertically stacked, three-dimensional transistors from lab experiments into commercial reality. The new Centura Avatar solves multiple problems facing manufacturers who are interested in 3D NAND but find their current equipment not up to the task of actually building it. According to the folks at Applied Materials, trying to build 3D NAND structures in real life would be like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata — and that's before we discuss gate trenches or the staircases. While this machine specifically targets 3D NAND today, a number of the challenges to scaling flash memory apply to scaling CPU logic as well. As for when 3D chips will be available for commercial purchase, Applied Materials was vague on that point, but personally I would expect to see companies adopting the new etch equipment in the next few years."
How long until some delusional nerd thinks this means "3D printing" chips at home?
1. When will this be in consumer product use?
2. How will this change the price per GB?
The next six months will be crucial to the development of this technology.
Yes, yes! I really did not read TFA but come the fuck on. Intel's Ivy Bridge was announced a few years ago and the product has been available for months now.
Is this yet another example of slashdot admin's time travel or what?
"would be like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata..."
No problem dudes, let me fire up Minecraft and I'll show you how its done!
I foresee this going at about the pace that perpendicular recording did with hard drives. Remember how we heard about this whiz-bang great new idea years ago, and look how long it took to actually come to the practical market.
But now it's ubiquitous. So I suppose the same will happen with the chip. And I can see this dealing a crushing blow to the already hurting spinning disc hard drives with them being able to vastly increase flash storage density.
I work for the Department of Redundancy Department.
dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart
Please avoid these strange and esoteric units and use units that are familiar to us. The approved units are football fields for lengths, Olympic size swimming pools for volume and libraries of congress for data volume, Rhode Island or Delaware for area.
sed -e 's/Chuck Norris/Rajnikant/g' joke > fact
There's two semantic goofs in this submission, one in the title and the other in the first sentence, and neither was noticed or corrected by Soulskill. The phrase "vertical 3D transistors" is misleading, since a literal interpretation doesn't describe z-axis stacking and instead describes objects whose most significant dimension is oriented vertically; it would be more accurate to write "stacked 3D transistors". In the first sentence, the adjective phrase "vertically stacked" is certainly a pleonasm if there ever was one; the definition of "stacked" already describes a z-axis or "vertical" state. The use of the word "vertical" in both of those instances is ineffective semantics.
From one and a half year ago: http://newsroom.intel.com/docs/DOC-2032
Anywhere between 3 and 100... nice vague PR job there
“He’s not deformed, he’s just drunk!”
I don't believe this is actually the *first* fab process using vertical structures (having actually RTFA). I worked at Texas Instruments in the mid-80's and most of the ALS (Advanced Low power Schottky) devices were of vertical well construction (as opposed to planar process or lateral junction bipolar construction). Looks like the sizes are a lot smaller, and the ratio of depth to width is a lot higher (a lot more junctions stacked in one well).
Chaos maximizes locally around me.
With all the SSD money coming in instead of just SD cards, flash drives, and RAM, I bet the main companies will be able to fund this technology and implement it without even the need for external investors. That'll speed things along more than other projects. A lot of vaporware disappears because of a lack of investment money being available of course.
Maybe Intel will fast speed it through, and wipe the floor with everyone else.
This random article I found has good pictures. This new chamber will allow for precise etch control from layer to layer. It's already in place at customer sites for R&D. (No company usually announces these products without having some placements or at least earlier marketing.) No one really knows how soon 3D NAND is coming; it depends on exactly how low they can scale 2D NAND, which is limited by the number of electrons you can store in a floating gate. 3D NAND designs usually use a charge trapping dielectric layer instead of polysilicon to store charge, the layers are then stacked to allow multiple layers of storage. But to contact each layer separately, you will need to etch through each layer in a sort of staircase pattern, which requires really good control of the etch process.