TSMC and Global Foundries Plan Risky Process Jump As Intel Unveils 22nm SoC

MrSeb writes with news on the happenings with next generation fabrication processes. From the article: "... Intel's 22nm SoC unveil is important for a host of reasons. As process nodes shrink and more components move on-die, the characteristics of each new node have become particularly important. 22nm isn't a new node for Intel; it debuted the technology last year with Ivy Bridge, but SoCs are more complex than CPU designs and create their own set of challenges. Like its 22nm Ivy Bridge CPUs, the upcoming 22nm SoCs rely on Intel's Tri-Gate implementation of FinFET technology. According to Intel engineer Mark Bohr, the 3D transistor structure is the principle reason why the company's 22nm technology is as strong as it is. Earlier this year, we brought you news that Nvidia was deeply concerned about manufacturing economics and the relative strength of TSMC's sub-28nm planar roadmap. Morris Chang, TSMC's CEO, has since admitted that such concerns are valid, given that performance and power are only expected to increase by 20-25% as compared to 28nm. The challenge for both TSMC and GlobalFoundries is going to be how to match the performance of Intel's 22nm technology with their own 28nm products. 20nm looks like it won't be able to do so, which is why both companies are emphasizing their plans to move to 16nm/14nm ahead of schedule. There's some variation on which node comes next; both GlobalFoundries and Intel are talking up 14nm; TSMC is implying a quick jump to 16nm. Will it work? Unknown. TSMC and GlobalFoundries both have excellent engineers, but FinFET is a difficult technology to deploy. Ramping it up more quickly than expected while simultaneously bringing up a new process may be more difficult than either company anticipates."

Comments

SoC

[Wiggin]

In case anyone else was wondering, SoC stands for System on a Chip

Re:SoC

[camperdave]

SoCs are CPU+Memory+bridges+etc. Any superset is going to be more complicated than the sets it contains.

Re:SoC

[UnknowingFool]

For ARM, GPU is on the SoC level. Most chip makers prefer it that way as they can pair their choice of GPU: PowerVR, nVidia, etc. Intel has chosen to bundle their GPUs with the CPU for the last few Core i-Series.

Re:SoC

[slew]

There are many thing more complex with SoC vs just CPU-chips. Although CPUs are complicated beasts in their own rights, if you follow the recent trends, they stamp down 4 of the units on the chip with lots of cache and only a few different Input/Output pad connections (e.g., DRAM, DMI). On an SOC, you've got lots of different types of units (CPU's, GPUs, Video decoders, wireless MACs, USB controllers, etc), each having their own clock, power and I/O requirements, and most of the time some licensed designs from outside IP vendors (of varying quality and originating from different design and testing environments), which have to be all integrated on the same chip.

Today, operations like place and route, timing closure, power and noise crosstalk, clock generation, etc, are tough things to do. If you only have a few identical things (say like 4 cores and 2 caches on a chip), you can leverage a lot of things between these modules. On an SoC, you need to do these things on all units, but you can't really leverage much between modules because they are so different, so some of the work is simply more complex (not necessarily harder, but more work and irregular work, so it's easier to overlook things, e..g., high complexity). There are also tons, secondary issues (e.g, thermal/electrical power sharing between GPU/CPU, low-power standby-modes), that you don't necessarily find in a CPU-only design that also need to designed and analyzed (can't fix them after you tape out the SoC, where you might be able to fix them on a board in a discrete design).

On the electrical I/O front, designing and characterizing a few standard I/Os that only have to drive a few mm on fairly standardized circuit boards isn't the same as having lots of different I/Os that run at different frequencies and have varying drive voltage requirements and high density packaging that need to still have a routable board with good signal integrity in several different circuit board designs. Just because Intel could get a few standard low-swing I/Os running on their 22nm process didn't mean it was a cake walk for them to design I/Os that hooks to cables and run at higher voltages and have experience more severe ESD issues (don't want to zap you SoC when you walk across the carpet).

The fact that they got the stuff they need for SoCs working from a design integration and electrical I/O point of view on their advanced 22nm process is certainly a big advance for them worthy of trumpeting...

Marketing 14nm not, real 14nm

[erice]

If you read the announcements, you will weasel words like "14nm class". The bottom line is: these are not 14nm processes. It would be more accurate to call them 20nm with FinFets. Global Foundries process does reduce some parameters from their 20nm planer but there is nothing 14nm about it.

Re:Marketing 14nm not, real 14nm

[Anonymous Coward]

I don't care if it's "real" 14nm or fake. What counts is how fast the resulting chips are, and how many MIPS/Watt they achieve. At the end of the day, the whole stuff is insistinguishable from magic.

Re:Marketing 14nm not, real 14nm

[girlintraining]

...there is nothing 14nm about it.

Add more Gs to it. That's what the telcos did. They bring a 2G, you bring a 3G. They bring a 3G, you bring a 4G. That's the chic--marketing way! Then we took that whole gigabyte thing with harddrives and just rounded down. Asking companies to compete based on actual specifications instead of marketing bullshit is communist. If you support that kind of commie non-sense then you're the reason we're losing jobs to China. Blah blah blah... *barfs*

Re:Marketing 14nm not, real 14nm

[iggymanz]

quite true and I'm sad. I want the end of the silicon roadmap as soon as possible

Re:Marketing 14nm not, real 14nm

[tlhIngan]

If you read the announcements, you will weasel words like "14nm class". The bottom line is: these are not 14nm processes. It would be more accurate to call them 20nm with FinFets. Global Foundries process does reduce some parameters from their 20nm planer but there is nothing 14nm about it.

The irony also is that it's a SoC, so most of the transistors there are NOT going to be "14nm" or "22nm" or whatever. They're going to be larger.

Why? Several things decide the size of a transistor - first, the use of the transistor - if it's an output driving several inputs, it means the transistor has to scale up to switch reasonably quickly. Ditto if the transistor has to drive a "long line" across the chip as it has to overcome capacitances and have enough current drive to overcome inductances. Power consumption reduction is achieved by making transistors smaller (because the fundamental gate capacitances and switching currents will be subsequently smaller, but it also means it will run slower - a small transistor driving a big one will take time for the drive required to overcome the bigger one's capacitances and such). But if power isn't a concern, it can run faster as well because there's less parasitics so a stronger drive will switch more quickly (a big transistor driving a small one will cause the small one to switch much quicker). Then there's the "overdrive" capability - a lot of circuits rely on geometry and current handling. Like a 6T SRAM - it's basically a couple of switching transistors (read/write, word output) followed by two back-to-back inverters (a couple of transistors each). The forward inverter has bigger transistors than the feedback inverter - when you write into the cell, the bit line overdrives it so the feedback inverter is overpowered and the forward inverter switches. After two gate times (forward and back), the value is latched. But it also means the bit line transistors are huge - they have to drive a long line and overpower a feedback inverter.

The small transistors are pretty much reserved for memory - where density of transistors is important. Density of transistors in non-memory (i.e., "random logic") parts is very low - because the problem is wiring density, not transistor density - the wires are dictating how close the transistors can be. So even on the SoC, the only small transistors would be stuff like caches and such. Everything else will be bigger because of what they're driving.

Re:Where is the damn article??

[ifiwereasculptor]

Ah, not the new /. at all, just the old /. readers.

Remember 40nm at TSMC?

[DavidClarkeHR]

I couldn't possibly comment because they'd fire me.

But it is rather awesome.

Is that sarcasm? You can't comment means you won't add criticism or praise? I remember the HUGE cock-up that TSMC caused AMD when they went to the 5000 series GPUs. They had QC issues for all the rev.0 chips, and none of them would overclock. The 3 that I bought (sequentially) all needed super-cooling OR underclocking to perform consistently.

Maybe it's just me, but I'm extremely sceptical that TSMC will be able to pull this off properly.

Can TMSC really do it?

[edxwelch]

It took Intel 10 years to take FinFET from concept to production, yet TMSC are claiming they can do it in only 2 years. Is that even feasible? Even if it is, doesn't Intel have patents on the tech?

Re:Yeah but can it run...

[Tapewolf]

I'm a bit scared of all this die shrinkage.

We have lots of perfectly working gear around here older than most of our offspring...

As transistor count goes up and feature size down can we expect more of our gear to start to go haywire over a shorter length of time or is there something baked into process steps to counteract or actually improve reliability?

I'm not sure why this was modded down. Flash in particular has problems with smaller die sizes, and while lower longevity has certain economic benefits, environmentally it's a dead end.

The other thing is the 11-year solar cycle... if we develop some ultra-high density technology during the low ebb, we may find that half our electronics get frazzled during the solar maximum.

Re:Well in this case

[Bengie]

During a 3-5 year stretch during this recession, Intel was the ONLY company with fabs that kept R&D flat. Everyone else made drastic cuts. There is a lot of ground to cover.

Re:OK, where are the people ...

[ArcadeMan]

Screw the 3D printers, I'm going to mill my own SoC. All I need is a sub-micron, square end mill bit.

Re:Yeah but can it run...

[ArcadeMan]

I'm a bit scared of all this die shrinkage.

22nm die: I was in the pool! I was in the pool!

Re:I couldn't possibly comment

[TechyImmigrant]

Clearly I made the mistake of posting my throwaway comment that landed as the first post, so people responded to it.

So I will add more detail:

I don't develop process technology, but I get to design logic circuits on this technology and it is indeed rather awesome.
After 20 years of gradual and steady feature size reduction, the switch to 22nm and beyond appears feels like a step in improvement way beyond the normal gradual improvement. In that sense it is rather awesome, because things that were previously too expensive to contemplate now start to look cheap and easy.