TSMC and Global Foundries Plan Risky Process Jump As Intel Unveils 22nm SoC

MrSeb writes with news on the happenings with next generation fabrication processes. From the article: "... Intel's 22nm SoC unveil is important for a host of reasons. As process nodes shrink and more components move on-die, the characteristics of each new node have become particularly important. 22nm isn't a new node for Intel; it debuted the technology last year with Ivy Bridge, but SoCs are more complex than CPU designs and create their own set of challenges. Like its 22nm Ivy Bridge CPUs, the upcoming 22nm SoCs rely on Intel's Tri-Gate implementation of FinFET technology. According to Intel engineer Mark Bohr, the 3D transistor structure is the principle reason why the company's 22nm technology is as strong as it is. Earlier this year, we brought you news that Nvidia was deeply concerned about manufacturing economics and the relative strength of TSMC's sub-28nm planar roadmap. Morris Chang, TSMC's CEO, has since admitted that such concerns are valid, given that performance and power are only expected to increase by 20-25% as compared to 28nm. The challenge for both TSMC and GlobalFoundries is going to be how to match the performance of Intel's 22nm technology with their own 28nm products. 20nm looks like it won't be able to do so, which is why both companies are emphasizing their plans to move to 16nm/14nm ahead of schedule. There's some variation on which node comes next; both GlobalFoundries and Intel are talking up 14nm; TSMC is implying a quick jump to 16nm. Will it work? Unknown. TSMC and GlobalFoundries both have excellent engineers, but FinFET is a difficult technology to deploy. Ramping it up more quickly than expected while simultaneously bringing up a new process may be more difficult than either company anticipates."

Comments

SoC

[Wiggin]

In case anyone else was wondering, SoC stands for System on a Chip

Re:SoC

[slew]

There are many thing more complex with SoC vs just CPU-chips. Although CPUs are complicated beasts in their own rights, if you follow the recent trends, they stamp down 4 of the units on the chip with lots of cache and only a few different Input/Output pad connections (e.g., DRAM, DMI). On an SOC, you've got lots of different types of units (CPU's, GPUs, Video decoders, wireless MACs, USB controllers, etc), each having their own clock, power and I/O requirements, and most of the time some licensed designs from outside IP vendors (of varying quality and originating from different design and testing environments), which have to be all integrated on the same chip.

Today, operations like place and route, timing closure, power and noise crosstalk, clock generation, etc, are tough things to do. If you only have a few identical things (say like 4 cores and 2 caches on a chip), you can leverage a lot of things between these modules. On an SoC, you need to do these things on all units, but you can't really leverage much between modules because they are so different, so some of the work is simply more complex (not necessarily harder, but more work and irregular work, so it's easier to overlook things, e..g., high complexity). There are also tons, secondary issues (e.g, thermal/electrical power sharing between GPU/CPU, low-power standby-modes), that you don't necessarily find in a CPU-only design that also need to designed and analyzed (can't fix them after you tape out the SoC, where you might be able to fix them on a board in a discrete design).

On the electrical I/O front, designing and characterizing a few standard I/Os that only have to drive a few mm on fairly standardized circuit boards isn't the same as having lots of different I/Os that run at different frequencies and have varying drive voltage requirements and high density packaging that need to still have a routable board with good signal integrity in several different circuit board designs. Just because Intel could get a few standard low-swing I/Os running on their 22nm process didn't mean it was a cake walk for them to design I/Os that hooks to cables and run at higher voltages and have experience more severe ESD issues (don't want to zap you SoC when you walk across the carpet).

The fact that they got the stuff they need for SoCs working from a design integration and electrical I/O point of view on their advanced 22nm process is certainly a big advance for them worthy of trumpeting...

Marketing 14nm not, real 14nm

[erice]

If you read the announcements, you will weasel words like "14nm class". The bottom line is: these are not 14nm processes. It would be more accurate to call them 20nm with FinFets. Global Foundries process does reduce some parameters from their 20nm planer but there is nothing 14nm about it.

Re:Marketing 14nm not, real 14nm

[girlintraining]

...there is nothing 14nm about it.

Add more Gs to it. That's what the telcos did. They bring a 2G, you bring a 3G. They bring a 3G, you bring a 4G. That's the chic--marketing way! Then we took that whole gigabyte thing with harddrives and just rounded down. Asking companies to compete based on actual specifications instead of marketing bullshit is communist. If you support that kind of commie non-sense then you're the reason we're losing jobs to China. Blah blah blah... *barfs*

Re:Where is the damn article??

[ifiwereasculptor]

Ah, not the new /. at all, just the old /. readers.

Re:Yeah but can it run...

[Tapewolf]

I'm a bit scared of all this die shrinkage.

We have lots of perfectly working gear around here older than most of our offspring...

As transistor count goes up and feature size down can we expect more of our gear to start to go haywire over a shorter length of time or is there something baked into process steps to counteract or actually improve reliability?

I'm not sure why this was modded down. Flash in particular has problems with smaller die sizes, and while lower longevity has certain economic benefits, environmentally it's a dead end.

The other thing is the 11-year solar cycle... if we develop some ultra-high density technology during the low ebb, we may find that half our electronics get frazzled during the solar maximum.

Re:Well in this case

[Bengie]

During a 3-5 year stretch during this recession, Intel was the ONLY company with fabs that kept R&D flat. Everyone else made drastic cuts. There is a lot of ground to cover.