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Intel's Haswell-E Desktop CPU Debuts With Eight Cores, DDR4 Memory
crookedvulture writes: Intel has updated its high-end desktop platform with a new CPU-and-chipset combo. The Haswell-E processor has up to eight cores, 20MB of cache, and 40 lanes of PCI Express 3.0. It also sports a quad-channel memory controller primed for next-gen DDR4 modules. The companion X99 chipset adds a boatload of I/O, including 10 SATA ports, native USB 3.0 support, and provisions for M.2 and SATA Express storage devices. Thanks to the extra CPU cores, performance is much improved in multithreaded applications. Legacy comparisons, which include dozens of CPUs dating back to 2011, provide some interesting context for just how fast the new Core i7-5960X really is. Intel had to dial back the chip's clock speeds to accommodate the extra cores, though, and that concession can translate to slower gaming performance than Haswell CPUs with fewer, faster cores. Haswell-E looks like a clear win for applications that can exploit its prodigious CPU horsepower and I/O bandwidth, but it's clearly not the best CPU for everything.
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*drool*
'nuff said.
I'm still clunking along on a P4 3.8 GHz. I'd love a new box that fast!
I do not fail; I succeed at finding out what does not work.
until next year. 14nm shrink should be a huge boost in both efficiency and performance.
The x99 is an "enthusiast" platform and has pricing along those lines.
DDR4 is also extremely new. Expect it to get faster/better timing specs as time progresses.
The 5820K is packing 6 cores and an unlocked multiplier for less than $400. If you don't absolutely need the full 8-core 5960X, then the 5820K is going to be a very powerful part at a reasonable price for the level of performance it delivers.
AntiFA: An abbreviation for Anti First Amendment.
Lets hope so. DDR3 has always been a joke, since it gained speed over DDR2 when configured in 3 channel banks. Except it is almost never configured that way, and thus resulted in faster clocked DDR2. Hopefully DDR4 works appropriately when configured in a 4 DIMM bank.
But does it run Linux?
No but it runs Netbsd!
Though the lower-end model is only $300 for a 6-core 12-thread!
http://www.microcenter.com/pro...
if you can wait then you should always wait for new tech
No one is talking about the elephant in the room: RAM prices are so high that you'd have to spend $700 to hit 64GB RAM (the max the board supports). That is just outrageous.
These prices are going to lead to a severe drop in demand.
CAS latency hasn't been measured directly in nanoseconds for some time now. It is now measured in clock cycles. The shorter your clock cycles (the higher your frequency) the shorter in absolute time your CAS latency is for the same number. CAS 10 at 2133 is about the same as CAS 5 on 1066.
CAS latency on Wikipedia
Memory timing on Hardware Secrets
FAQ on RAM timings from Kingston
DDR is not about the number of channels. You could design a system with 8 channels DDR1 or single channel DDR4 if you want to. New generation DDR RAM is always about lower voltage and higher clock speed. Usually at the cost of higher latency (800 MHz DDR3 is a bit slower than DDR2)
Just to put "some time now" the time frame into perspective, the last mainstream PC memory form-factor to use asynchronous DRAM was 72 pin SIMMs.
When PCs went from 72 pin SIMMs to the first 168 pin DIMMs, in the mid-1990s, the interface changed to (non-DDR) synchronous clocking.
PJRC: Electronic Projects, 8051 Microcontroller Tools
I use -- and write -- image processing software. Correct use of multiple cores results in *significant* increases in performance, far more than single digits. I have a dual 4-core, 3 GHz mac pro, and I can control the threading of my algorithms on a per-core basis, and every core adds more speed when the algorithms are designed such that a region stays with one core and so remains in-cache for the duration of the hard work.
The key there is to keep main memory from becoming the bottleneck, which it immediately will do if you just sweep along through your data top to bottom (presuming your data is bigger than the cache, which is typoically the case with DSLRs today.) Now, if they ever get main memory to us that runs as fast as the actual CPU, that'll be a different matter, but we're not even close at this point in time.
So it really depends on what you're doing, and how *well* you're doing it. Understanding the limitations of memory and cache is critical to effective use of multicore resources. You're not going to find a lot of code that does that sort of thing outside of very large data processing, and many individuals don't do that kind of data processing at all, or only do it so rarely that speed is not the key issue, only results matter. But there are certainly common use cases where keeping a machine for ten years would use up valuable time in an unacceptable manner. As a user, I am constantly editing my own images with global effects, and so multiple fast cores make a real difference for me. A single core machine is crippled by comparison.
I've fallen off your lawn, and I can't get up.
Interesting essentially how little benefit they get.
The X99 mobo and platform is nice, I like a lot of what they're doing there, and all of the system components matter a lot to user experience. But unless you have a very specific requirement any user would be just as well served with a quad core or a octa core, if not better served with the devil's canyon quad core given the single threaded performance. That's probably a bad place for intel to be positioning these, as the target audience for these processors is looking for blazing fast and lots of cores. And it only delivers one of the two.
I think if I was buying a system this week or next (which... I am) I'd be a bit disappointed that I can't put a devil's canyon quad core on an X99 mobo, and then upgrade the CPU later if they manage to refresh the E series into something more attractive.
AMD, and IBM have both been talking about stacked designs for cache memory, Intel has been a big player in HBM/FCRAM development, and AMD, ARM, and others are throwing a lot of weight behind HSA, even Intel is bringing in some of the idea's of HSA at least as far as unified cpu/gpu virtual memory address spaces are concerned. The next 2-3 years is going to be transformative for computing, languages and software libraries will need to catch up with not just with macro threaded concurrency, but also with micro threading concepts. The convergence of "large enough" caches something like Iris Pro but with real cache memory instead of edram, HSA making igpu a first class citizen(think if opencl had access to the programs heap/stack, aka being able to call virtual functions, checking type information, accessing arbitrary objects not directly passed in the functions parameter list), and hopefully HBM/FCRAM will finely catch memory speed up at least for a year or 2(it'ill never last but here's hope'n lol).