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Thanks For the Memories: Touring the Awesome Random Access of Old (hackaday.com)

Posted by timothy on from the tanks-would-work-just-as-well dept.

szczys writes: The RAM we use today is truly amazing in all respects: performance, reliability, price; all have been optimized to the point you can consider memory a solved problem. Equally fascinating is the meandering path that we've taken over the last half century to get here. Drums, tubes, mercury delay lines, dekatrons, and core memory. They're still as interesting as the day electrons first ran through their circuits. Perhaps most amazing is the cost and complexity, both of which make you wonder how they ever manage to be used in production machines. But here's the clincher: despite being difficult and costly to manufacture, they were all very reliable.

89 comments

  1. aight by buck-yar · · Score: 0, Offtopic

    So they didn't post my article about Ardupilot becoming an entity, but post this garbage?

    What other sites are like slashdot out there?

    1. Re:aight by Anonymous Coward · · Score: 1

      Fucking drone bros trying to slashvertise

    2. Re:aight by Anonymous Coward · · Score: 0

      soylent news

    3. Re:aight by Anonymous Coward · · Score: 0

      Call the weaaahmbulance!

    4. Re: aight by dwywit · · Score: 0

      You're funny.

      --
      They sentenced me to twenty years of boredom
    5. Re:aight by Anonymous Coward · · Score: 0

      So they didn't post my article about Ardupilot becoming an entity, but post this garbage?

      What other sites are like slashdot out there?

      Luckily for us and all the universes, there's only one Timmay!

    6. Re:aight by Anonymous Coward · · Score: 0

      How many people are going to use your open source hardware autopilot? I'd wager less than 10. About the same number of people upset that OpenBSD retired their port to the VAX architecture.

    7. Re:aight by Anonymous Coward · · Score: 0

      They did WHAT????

    8. Re:aight by Anonymous Coward · · Score: 0

      More fucking Drone shit

      Don't you know that your drone-toys are just another stupid fad that will go away soon? Your 15 minutes is at least half over. I suggest you and the rest of your vapid friends go looking for the Next Big Thing to sperg over and dump your silly annoying flying toys in the e-waste bin where they belong.

    9. Re: aight by Anonymous Coward · · Score: 0

      I keep a gun in my jeans, I call them Hammer pants.

    10. Re:aight by Darinbob · · Score: 1

      It's ok, 4.2BSD still works fine.

    11. Re:aight by MattskEE · · Score: 1

      This is a great article in my opinion, definitely "News for Nerds" and definitely Slashdot-worthy.

  2. my windowa 8 box with 4 gig of ram.. by Anonymous Coward · · Score: 0

    still gives me a 'memory low must shut down' message when i run firefox....

  3. DRAM by johnsmithperson123 · · Score: 3, Insightful

    I suspect we may be nearing the end of DRAM, though only time will tell. DRAM is old and really a bottleneck these days, something is likely going to replace it. At the very least in the next few years the form factors will change from DIMMs to perhaps HBM stacked on-die and fiberoptic DIMMs. At least that would be my next guess, anyway.

    1. Re:DRAM by drinkypoo · · Score: 2, Interesting

      At the very least in the next few years the form factors will change from DIMMs to perhaps HBM stacked on-die and fiberoptic DIMMs.

      We don't need fiberoptic links for memory because it is not inconvenient to provide a very broad path between the CPU and the RAM. They would provide literally no benefit.

      --
      "You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
    2. Re:DRAM by phishybongwaters · · Score: 4, Interesting

      Yes and no, if you are thinking about your computer or single server sitting beside you. If you are thinking of next gen data centers and virtualized servers, being able to supply a bus to RAM over a fiber link is very interesting. Think of a server component or appliance you install into a rack, then fiber link to your Hosts to supply more ram. There is a limit to the amount of ram slots on a server, a physical limit. Fiber links would open up the ability to have external ram that doesn't actually need a slot. Fiberlinks take considerably less space. And if this was an option, I suspect you'd have a fiber trunk coming from the host. This could actually be genius.

    3. Re:DRAM by Anonymous Coward · · Score: 4, Interesting

      Optical interconnection is very efficient and good fidelity and low interference, but ease of manufacturing complex interconnection and creating multiple permanent connections is still lacking, compared to electric/metal. In addition to that, drivers/receivers are bulky and dissipate too much power. Before photonics can replace electronics, there'll have to be a revolution in miniaturisation and low power for fiber drivers/receivers, as well as analogue mass production technological processes to board etching and component soldering of today.

    4. Re: DRAM by johnsmithperson123 · · Score: 1

      I know. The main barrier to this is how fast you could clock the fiber (effectively). If you could push it even to a few gHz it would beat copper. The question, of course, being over whether or not your silicon-fiber converter could run that fast. If it's possible it could solve a lot of issues, especially since HyperTransport and similar copper-based tech is nearing the limit.

    5. Re:DRAM by serviscope_minor · · Score: 3, Informative

      Yes and no, if you are thinking about your computer or single server sitting beside you. If you are thinking of next gen data centers and virtualized servers, being able to supply a bus to RAM over a fiber link is very interesting.

      Infiniband essentially already does this: it's a high speed, low latency interconnect which provides remote memory access and works over copper or fiber. It's only moderately low latency though, since the speed of light is limited.

      Every meter gives 3 nanoseconds of latency, more like 4 because the signals are sub-luminal in speed. You won't have to have a long cable before you add a serious latency penalty compared to local RAM. That's never mind the protocol and networking overhead, which for infiniband (which is designed for low latency for supercomputers) is still 500ns, dwarfing the RAM latency.

      There have in fact been systems made to essentuially build virtual machines with distributed memory like this. The trouble is they suck beause the code is written assuming fast access to RAM.

      Big supercomputer codes which essentially have to deal with this all the time use MPI, so they can know about the high latency (i.e. 500nS) transfers and schedule them long in advance.

      --
      SJW n. One who posts facts.
    6. Re: DRAM by johnsmithperson123 · · Score: 1

      If I recall, though, Infiniband is still copper.

    7. Re:DRAM by Anonymous Coward · · Score: 0

      Nah latency is important for memory. You wouldn't want the memory to be more than a couple of inches away from your processor.

    8. Re: DRAM by Anonymous Coward · · Score: 0

      What part of:

      Every meter gives 3 nanoseconds of latency, more like 4 because the signals are sub-luminal in speed.

      did you not understand?

      Regardless, even at the speed of light it is absolutely ridiculous to suggest that this is any replacement for DIMM's. This is the equivalent of cluster computing, with fancy marketing thrown in. And long distances to third parties.

    9. Re: DRAM by serviscope_minor · · Score: 1

      If I recall, though, Infiniband is still copper.

      It apparently has both modes, but fiber is only really useful for long runs. It's speed over distance where it really wins, not raw speed over short runs.

      --
      SJW n. One who posts facts.
    10. Re:DRAM by Anonymous Coward · · Score: 0

      Problem is that at GHz clock speeds, light only gets to travel a few inches between clocks, once you've gotten your photons out of one rack mount chassis and into another one your back to DRAM style latency. Anything not in the same room and you'd be as well off to use some SSD's

    11. Re:DRAM by xanthos · · Score: 1

      Careful there. You are at risk of reinventing the mainframe.

      --
      Average Intelligence is a Scary Thing
    12. Re: DRAM by Anonymous Coward · · Score: 0

      Holy fuck. So you have an MBA? That's a lot of buzzwords there Woody.

    13. Re:DRAM by real+gumby · · Score: 1

      This is one of the key features of HP's much-hyped "machine": direct, on-chip optical interconnects.

      (Frankly HP's marketing continues to suck: when I read the hype about the "machine" I just yawned. But then I ran into a friend who had moved to HP to work on it and learned that it has some pretty cool features. I guess things like optical interconnect and massive shared address space just don't make interesting news stories.)

      Some stuff on their optical work: http://www.hpl.hp.com/techrepo...

    14. Re: DRAM by lgw · · Score: 1

      Copper is faster - 4ns/m vs 5ns/m for fiber optic. Copper has other difficulties with long runs, since it's very dependent on the impedance of the transmission line remaining consistent, susceptible to interference and so on, so fiber is just more practical for long runs. People seem to prefer fiber for short interconnects in the DC because it seems high tech, but copper is faster.

      --
      Socialism: a lie told by totalitarians and believed by fools.
    15. Re:DRAM by MattskEE · · Score: 1

      Advancing the manufacturability of photonic technology is one of the goals of the the federally funded AIM Photonics program: http://www.aimphotonics.com/

    16. Re: DRAM by Bengie · · Score: 1

      Fiber in DCs is also nice to isolate surges or ground differentials. Copper may be faster for signal prorogation, but the complexity of processing the signal at high bandwidth adds much more latency than the signal over short runs.

    17. Re:DRAM by eric_harris_76 · · Score: 1

      I'm sure this US government project will be every bit as significant as the Japanese government's Fifth Generation program.

      You know, from back in the days of Japan, Inc.

      --
      There's no time like the present. Well, the past used to be.
  4. Difficult? by Anonymous Coward · · Score: 1

    Core memory is difficult to manufacture, but flash drives are no big deal? Sure....

    1. Re:Difficult? by vtcodger · · Score: 3, Interesting

      Apparently back in the day, core memory actually was a bit difficult to manufacture. Back in the 1960s, they wired the cores by hand and that apparently required quite a bit of manual dexterity. The first digital computer I ever saw was SWAC at UCLA (https://en.wikipedia.org/wiki/SWAC_(computer)). 256 37 bit words of Cathode Ray Tube memory. I have no real idea how it worked, but I recall that on days when it chose to work, there were a bunch of CRTs displaying an 8x8 matrix of zeros and ones. The professor in charge of the thing told us in his rather thick European accent that they were trying to augment the CRT memory with core, but that so far his graduate student(s) hadn't been able to thread the core wires well enough.

      --
      You can't see ANYTHING from a car, You've got to get out of the goddamned contraption and walk...Edward Abbey
    2. Re:Difficult? by toonces33 · · Score: 2

      I actually have some core memory sitting in a box. I have no recollection now many bits, but it isn't all that many. When you (carefully) remove the cover, you see how small the individual elements are. The stories I heard back at the time were of Asian women with small fingers threading the wires through these things by hand.

    3. Re:Difficult? by GerryGilmore · · Score: 3, Interesting

      Yep, I can verify that. Worked for Data General and the original Nova series used all core memory. The "core stacks" arrived in Mass from Asia and were then mounted on the memory card itself. Took the cover off of a dead one one time and it looked like velcro until I got it under a magnifying lamp. Even then, I was amazed at the dexterity it must take!

    4. Re:Difficult? by NixieBunny · · Score: 2

      I have a 2" diameter jar with half a megabit of core memory, but it's not strung yet. They are extra-tiny cores. My coworker saved the core from a PDP-11 computer, I think it's 16k bytes. One board for the cores, one for the driver circuits.

      --
      The determined Real Programmer can write Fortran programs in any language.
    5. Re:Difficult? by Anonymous Coward · · Score: 0

      Wow, that was quite advanced for core memory. I know an old-timer with a 1 kB core memory sitting in the garage. It is a square, say about the size of two smartphones put side by side.

    6. Re:Difficult? by RogerWilco · · Score: 2

      There's a video in the linked article that shows how core memory is made, and it is indeed a finicky manual process manipulating things to small for even pliers.

      --
      RogerWilco the Adventurous Janitor
  5. RAM problem solved? by Anonymous Coward · · Score: 1

    Yes, the RAM we use today is amazing. But it is never fast enough, never big enough and never cheap enough. Never. RAM access is still the performance bottleneck in many applications.

  6. Look ahead by samuel.progin · · Score: 4, Interesting

    Saying that a problem is solved is risky. Remember that the physics was solved shortly before Einstein et all! The future might reshape our perception, with for instance RAM and ROM convergence: https://en.wikipedia.org/wiki/...

  7. Still not as reliable as szczys by Anonymous Coward · · Score: 0

    When one measures reliability, often the authority is disregarded.
    This proves that the two are no longer uncorrelated.
    Now that we can identify moronic measures, we can almost certainly disregard both the author and the product.

  8. Its Cosmic by Anonymous Coward · · Score: 2, Interesting

    One thing we have forgotten about is the impact (literally) of cosmic rays on memory cells. The old core planes were not very sensitive to the effect of an alpha particle from space zipping through the little donuts and changing values. But solid state RAM certainly was. In the old days, funny things would occasionally happen as a result of cells having their stored values flipped from 0 to 1 or back. These were rare random events that became more frequent as the amount of memory and its density grew. High reliability machines like servers used error correcting memory (ECC) that added a few extra bits so a change could be detected when the cell was read and hopefully recovered. The source of the problem is still there.. and so is ECC memory.

    1. Re:Its Cosmic by EmagGeek · · Score: 5, Informative

      Alpha Particles from space do not penetrate the building that the computer is in, nor the computer case, nor the plastic package of the memory devices themselves.

      Alpha particle bit errors are caused by alpha particle emissions within the memory cell itself, as there is a minute amount of radioactive material in all semiconductor devices, including memory.

      However, radiation-induced bit errors are seldom actually caused by package alpha particle emissions. The more likely space-related culprit is neutron flux. It has been found that DRAM bit error rates increase dramatically with altitude, and that solar events increase the rates further.

      Fun stuff.

    2. Re:Its Cosmic by Anonymous Coward · · Score: 0

      Not the semiconductor; the package.

    3. Re:Its Cosmic by kheldan · · Score: 2

      As I recall, if the memory itself was packaged in ceramic rather than plastic, there was potentially a higher error rate from that particular source, because of the greater chance of radioactive material in the ceramic used.

      --
      Are YOU using the TOOL, or is the TOOL using YOU? Think about it!
    4. Re:Its Cosmic by Anonymous Coward · · Score: 0

      One thing we have forgotten about is the impact (literally) of cosmic rays on memory cells.

      Who's forgotten about that? The article mentions that in the section about core memory:

      It is also very tolerant to radiation which is why the Space Shuttle computers used core memory until the 1990s.

      Those of us who actually work with space craft worry about this routinely. And not just for memory. CPUs and everything else needs to be rad hardened and even then faults will happen. Or worse. If you're some place with high radiation you simply have to accept that your mission will end when the electronics are destroyed.

  9. Solved Problem?!?!?? by Anonymous Coward · · Score: 1, Insightful

    Are you fucking kidding me? RAM is the SLOWEST part of the entire execution chain, and it's ORDERS OF MAGNITUDE slower than even the slowest CPU cache.

    Memory busses are horribly inefficient, slow, and subject to data corruption without taking extensive measures to prevent them (which slow them down even more).

    Even assuming we use the entire ~12MB of L3 cache as instruction cache (which is impossible really unless those instructions don't require any data access, which is utterly implausible), any modern CPU can blow through that in much less time than it takes a DDRx memory controller to set up a RAS.

    The one and only thing slower than memory access is disk access, and even there we are closing the gap. Memory has not gotten appreciably faster in a decade, unless of course you ask marketing people.

    This is literally the stupidest thing I've seen posted on Slashdot in a long time, since at least yesterday!

    1. Re:Solved Problem?!?!?? by BitZtream · · Score: 3, Informative

      slower than even the slowest CPU cache.

      CPU cache IS MEMORY, so how can it be slower than itself?

      And before I quote the rest of your trash and make you look stupid, lets point out the most important fact here:

      You can have RAM that runs as fast as CPU cache, you just can't afford it.. That CPU with 12MB of CPU cache is mostly expensive BECAUSE OF THE 12MB OF CACHE. and the difficulty in getting that much RAM to operate reliably at those speeds results in low yields, and increased consumer cost.

      Even assuming we use the entire ~12MB of L3 cache as instruction cache (which is impossible really unless those instructions don't require any data access, which is utterly implausible), any modern CPU can blow through that in much less time than it takes a DDRx memory controller to set up a RAS.

      Did you seriously imply that a Xeon CPU can blow throw 12MB of instruction cache in the amount of time it takes to do one complex instruction? That IS what you said. Which takes what? 40 clock cycles total, in the extreme worst case? (on anything with a 12MB cache which are going to all be high end/fast chips). So you're claiming that in 40 clock cycles it can empty a 12MB cache ... No. In 40 clock cycles ... it can load EXACTLY 40 registers with data from cache ASSUMING IT DOESN'T DO ANYTHING ELSE. So awesome, you just loaded 320 bytes of RAM into CPU registers ... and didn't use it for anything at all.

      Do a BSR or BSF on 64 bit number takes 16 clock cycles all by itself!

      The one and only thing slower than memory access is disk access, and even there we are closing the gap. Memory has not gotten appreciably faster in a decade, unless of course you ask marketing people.

      DDR3's base rate is 800MT/s. DDR4's base rate is 2133MT/s ... yea, 2.5x is not appreciably faster or anything.

      The one and only thing slower than memory access is disk access, and even there we are closing the gap.

      Awe thats cute, you think SSDs are somewhere near RAM speeds. Just because SSDs are ridiculously fast at some things compared to spinning rust doesn't make them magically fast. We've had disks on arrays capable of saturating CPU bandwidth for years too.

      This is literally the stupidest thing I've seen posted on Slashdot in a long time, since at least yesterday!

      If you're referring to your post, then yes, I agree. It is pretty fucking stupid.

      Do you know what DDR means? It means DOUBLE data rate. Twice as fast. (not really, but close enough for hand grenades). Do you have any idea what DDR2 did on top of that? And 3 ... and 4 ...

      --
      Persistent Volume manager for Kubernetes - https://github.com/dwimsey/openshift-pvmanager
    2. Re:Solved Problem?!?!?? by Anonymous Coward · · Score: 0

      compared to spinning rust

      I want to punch whoever came up with that stupid "term".

    3. Re:Solved Problem?!?!?? by Anonymous Coward · · Score: 0

      How about orbital sand if we assume glass platters?

    4. Re:Solved Problem?!?!?? by AmiMoJo · · Score: 1

      CPU cache IS MEMORY

      Yes, but it's not RAM. The rest of your post is based on that misunderstanding.

      Random Access Memory (RAM) can only access one memory address at once. If you tried to use it for CPU cache, you would have to store the address of each cached word (collection of bytes) along with the value, and then search through every address individually every time. It would be extremely slow, a massive performance down-grade.

      Cache memory is different. When accessing it the CPU presents an address, and the cache memory instantly compares it to every address that it has cached. That's the primary reason why it's so expensive - it needs a massive amount of hardware to do all those comparisons simultaneously. I'm simplifying here, most caches compromise on the amount of comparator hardware required by having multiple levels of cache with different properties and different complexities.

      Cache memory isn't just really fast RAM, it's an entirely different type of storage.

      --
      const int one = 65536; (Silvermoon, Texture.cs)
      SJW, n: "Someone I don't like, and by the way I'm a fuckwit" - AC
    5. Re:Solved Problem?!?!?? by radarskiy · · Score: 2

      "Random Access Memory (RAM) can only access one memory address at once. "

      Random Access Memory can access memory randomly. The term includes no prior restraint on the number of ports. Internal caches are (typically) specifically SRAM, where you will note the "RAM" portion of the acronym.

      "If you tried to use it for CPU cache, you would have to store the address of each cached word (collection of bytes) along with the value"

      Caches already store the address of each cached word. This is the Tag RAM. Although once you are in the CPU you are typically operation on a portion of the address since the CPU internally can only access a portion of the address space at once. This portion is the Tag.

    6. Re:Solved Problem?!?!?? by AmiMoJo · · Score: 1

      The term includes no prior restraint on the number of ports.

      True, but DRAM in particular doesn't actually allow simultaneous access from two ports. It multiplexes. SRAM can do two simultaneous accesses, but isn't widely used in PCs due to cost. Good point though, I did forget about dual port RAM.

      Caches already store the address of each cached word. This is the Tag RAM.

      Not in the modern sense of the word "CPU cache". Tag RAM is just normal RAM, so while fast it does have to be searched by polling every used address. So if you had a 256 word tag RAM, you would have to make 256 accesses to check every address in your cache. Rather inefficient, which is why it is only used on very old and simple caches of a few lines.

      What we generally call a CPU cache today uses content-addressable memory. As I described, an address is presented to the memory and it compares it to all the tagged addresses it holds simultaneously. Okay, pedantically it's sometimes not all, but... It's not RAM. It's not randomly addressable, it's content-addressable.

      --
      const int one = 65536; (Silvermoon, Texture.cs)
      SJW, n: "Someone I don't like, and by the way I'm a fuckwit" - AC
    7. Re:Solved Problem?!?!?? by Coren22 · · Score: 1

      Glass doesn't have magnetic domains. It still has iron, which is the main component of rust.

      --
      APK likes to ask for responses to the same things over and over. Maybe he just likes the responses?
    8. Re:Solved Problem?!?!?? by Anonymous Coward · · Score: 0

      Still... Memory speeds had not increased as much as cpu speed. Compared to the cpu speed the memory has lagged *far* behind.

      And technically you are correct (the best kind of correct, I know) saying cache memory is memory, but because you need to go over a bus and a memory controller accessing the main ram is orders of magnitude slower than accessing the cache (why would you have a cache anyway if that weren't true).

    9. Re:Solved Problem?!?!?? by dfsmith · · Score: 1

      How much iron is there in cobalt-chrome alloys sputtered onto an aluminum platter? There's more iron in screws than the recording media. Iron oxide hasn't been used since the last century (1980s). The only major iron-containing component of any drive made in the last 10 years is the stainless steel cover.

    10. Re:Solved Problem?!?!?? by radarskiy · · Score: 1

      " SRAM ... isn't widely used in PCs due to cost. "

      All on-die CPU caches are SRAM.

      " it does have to be searched by polling every used address"

      Entries in a tag ram are mapped in the same way the entries in the related caches are mapped. The Tag ram give you the complete address for the store cache line that is then compared to the desired address to determine if the desired address is actually in the cache.

      "a CPU cache today uses content-addressable memory"
      At most, selection of a line out of a set from an associative cache is content addressed. Choosing the set is still direct mapped, and not all caches are associative.

    11. Re:Solved Problem?!?!?? by Anonymous Coward · · Score: 0

      "CPU cache IS MEMORY, so how can it be slower than itself?"

      Yes, CPU cache is memory, but it is not DRAM. It's wildly different, and operates completely differently. Your fundamental misunderstanding of computer architecture is betrayed by this simple statement. The rest of your comment deserves no response as a result.

    12. Re:Solved Problem?!?!?? by Darinbob · · Score: 1

      You seem to be talking about fully associative caches. Most CPUs do not use this as general memory caches. Tag lookup is trivial, but then you have 1 to N ways/sets to look for. The 1 set "direct mapped" caches are very simple. A 4 way set associative cache though only has to check 4 possible entries, and that's not expensive. And 4 or 8 way set associative caches are extremely common. A fully associative cache just isn't practical unless the amount of memory is relatively small, thats's why on a PC where cost is not so important the only places you're likely to see a fully associative cache is for TLB memory (32 entries).

    13. Re:Solved Problem?!?!?? by Bengie · · Score: 1

      You can have RAM that runs as fast as CPU cache, you just can't afford it.

      Not really. Cache is only fast because of the huge number of traces. Unfortunately, you have to choose between one of two things for larger caches. n^2 increase in traces as your cache size increases or reduce the size of n at the expense collisions, which means your "memory" is now lossy. That also ignore the nasty increase of latency as cache gets larger. After a certain point, well within the range of current memory sizes, cache will have higher latency than DRAM.

    14. Re:Solved Problem?!?!?? by Agripa · · Score: 1

      The one and only thing slower than memory access is disk access, and even there we are closing the gap. Memory has not gotten appreciably faster in a decade, unless of course you ask marketing people.

      DDR3's base rate is 800MT/s. DDR4's base rate is 2133MT/s ... yea, 2.5x is not appreciably faster or anything.

      The latency has not significantly improved. They are not putting massive amounts of cache on these processors to improve bandwidth but to reduce the penalty do to latency.

      Bandwidth can be increased using wider organization, higher clock speeds, and more channels; none of these things lower latency. Synchronous DRAM has been increasing bandwidth by reading more bits in parallel internally and then transferring them through a relatively narrow interface at increasingly high clock rates. In practice every DDR generation has doubled the clock rate, doubled the internal line size, and doubled the number of pulses in the burst transfer.

    15. Re:Solved Problem?!?!?? by Agripa · · Score: 1

      The cache array minus the tag and content elements is just an array of SRAM optimized for use as a cache with features like multiple ports. Before all cache became integrated, external SRAM was used for cache and it became increasingly specialized for cache applications as time went on.

      Many processors with cache (or all of them?) including Intel X86 processors boot into a mode where the SRAM in the cache can be used in place of external memory until the external memory can be configured for access. Many processors intended for real time operation can lock cache lines so that they can be used as fast local memory with low and predictable latency and high bandwidth.

  10. Uhh whaaaa? by Dunbal · · Score: 3, Funny

    But here's the clincher: despite being difficult and costly to manufacture, they were all very reliable.

    That was kind of built into the design spec. The guy who build unreliable memory (you know, the one who came up with the Alzheimer Machine) - well he went bankrupt pretty quick right alongside the guy who invented a horseless carriage that only needed a horse half the time.

    --
    Seven puppies were harmed during the making of this post.
    1. Re:Uhh whaaaa? by BitZtream · · Score: 0

      szczys is like a 15 year old who doesn't really understand the world real well yet and when he makes these amazing discoveries that we've all known for years ... some how some idiot at slashdot ... who is entirely unqualified to be anywhere near a 'news for nerds' site posts it to the front page because they aren't nerds and don't actually know that this shit is rather common knowledge among ACTUAL nerds and geeks.

      If you look at his submission history, its something you would expect from your high school teenager.

      --
      Persistent Volume manager for Kubernetes - https://github.com/dwimsey/openshift-pvmanager
    2. Re:Uhh whaaaa? by hey! · · Score: 4, Interesting

      On the other hand the relationship between a system's reliability and the reliability of the system's components isn't one-to-one. You can build unreliable systems out of reliable components, and more surprisingly, you can build reliable systems out of unreliable components. That latter principle is the basis for the Internet, which provides end-to-end communication that is more reliable than any of the possible paths between those endpoints.

      Every component is unreliable to some degree; as it becomes increasingly reliable it moves from unusable, to something you can work around, to something whose potential failure you can ignore in many applications.

      --
      Post may contain irony: discontinue use if experiencing mood swings, nausea or elevated blood pressure.
    3. Re:Uhh whaaaa? by Dunbal · · Score: 1

      and more surprisingly, you can build reliable systems out of unreliable components. That latter principle is the basis for the Internet

      Closer to home it's also the basis for human bodies. I remember my the head of the Anatomy department at my school seemed to be obsessed with the notion that human bodies were perfect. Then again she was a religious nut. I never challenged her on this of course (there's no point arguing with a religious nut), but merely thought to myself "ok if we're so perfect then explain disease to me, and explain aging..."

      I also agree that having unreliable components helps to "build in" redundancy. The human body, for example, can take a surprising amount of punishment on a cellular or even an organ system level, before packing it in. But I would think that with computer memory, unless there's some firmware or software error correction built it, you pretty much need that bit that you set to 1 to stay as 1 until told otherwise.

      --
      Seven puppies were harmed during the making of this post.
    4. Re:Uhh whaaaa? by edtice1559 · · Score: 1

      I wish I had a supply of mod points.

    5. Re:Uhh whaaaa? by Darinbob · · Score: 1

      "Reliability" is a bit iffy. Many were prone to failure for various reasons. For example the drivers for the memory would be complex, be on separate cards from the memory, involve vacuum tubes, and so forth. The actual memory and it's ability to reliably store and retrieve the data may be good though.

      There's also the issue of that memory not having to store so many bits. If you've got 1 failure per billion bit accesses then it seems pretty solid if you've only got 1000 bits but it would be useless if you had one gigabyte.

      Plus each bit back then was huge in terms of physical size. With core memory you'd have each bit a few millimeters wide, and a small manufacturing defect leaving a scratch on a magnet won't affect it. But if each bit is a nanometer then you need much tighter manufacturing tolerances and your reliability goes way down.

  11. Disappointing Title - not an attack on RAM? by Anonymous Coward · · Score: 0

    The title is disappointing. I initially thought this was about an attack on reading raw RAM contents and seeing what interesting things you can find within there in the "deallocated" or "unused" portions of memory from terminated ancient processes of yore.

  12. The best statistic in the article by Applehu+Akbar · · Score: 1

    Most of the technologies TFA describes were experimental, but that mainframe mainstay, core memory, came down in cost during its run from $1/bit to one cent. Even at that price, a memory stick would cost $10 million per gigabyte and would require a room of its own. I love living in the future.

    1. Re:The best statistic in the article by iggymanz · · Score: 1

      You misunderstand, *ALL* memory systems in the article were used in commercial systems. can't call any of them "experimental" after that.

  13. Overhaul the whole architecture by ArchieBunker · · Score: 2

    Read up on what IBM did for their AS/400 architecture. Very brilliant work.

    --
    Only the State obtains its revenue by coercion. - Murray Rothbard
  14. not neutrons, it's cosmic rays by Anonymous Coward · · Score: 5, Informative

    The bit flips aren't due to neutrons, but to other high energy particles (cosmic rays).
    And modern memory design tolerates this quite well (on chip EDAC, for instance).

    But that's not the dominant source of errors any more. It's more things like electrical noise (signal integrity is another term). As you reduce the size of the device holding a single bit, you're starting to get down to where the thermal noise is a significant fraction of the "signal" (i.e. the presence or absence of charge in that bit storage).

  15. Drum Memory by T.E.D. · · Score: 2

    I've heard some really interesting stories about Drum memory.

    Since you had to wait for your desired read/write location to rotate under the head, and since this was back in the CISC era when the execution time of every instruction was known and published, developers would "optimize" their memory accesses by placing their data on the drum in the exact spot that each byte would be under the head when the instruction to read or write it was processed.

    Even more interestingly, at least one platform made use of this architecture by using an assembly language that effectively had a goto at the end of every instruction. That way you could scatter your code on the drum to perform the same optimization.

    I saw another story about early rotating-drum systems being put on USN ships. Supposedly the first time they tried to turn at sea the navigators discovered the hard way that the designers failed to account for the gyroscopic property of having a large rotating metal drum on board...

  16. Re:And all invented and manufactured by... by silentcoder · · Score: 1

    Actually - pretty much all of it is made from rare earths mined by slaves in Africa, old-fashioned whips-and-chains unpaid slaves.

    --
    Unicode killed the ASCII-art *
  17. My first computer, ever.. by kheldan · · Score: 1

    ..was built on perfboard, and had 256B (yes, not a typo: 256 bytes) of static RAM memory. The next incarnation of it had a whole 4096B (yes, again, not a typo: 4096 bytes) of static RAM. When you're writing everything in machine code, it's amazing how much you can get done. Even when I graduated up to a Z80-based computer running CP/M, and had a whole 56kB of program space to work with (on a 16-bit address bus; the other 8kB was the OS.. the entire OS, mind you!), you could accomplish an amazing amount of functionality, even when writing code in C (classical C; C++ hadn't been invented yet). Fun, fun, fun..

    --
    Are YOU using the TOOL, or is the TOOL using YOU? Think about it!
    1. Re:My first computer, ever.. by Tablizer · · Score: 2

      built on perfboard, and had 256B (yes, not a typo: 256 bytes) of static RAM memory...When you're writing everything in machine code, it's amazing how much you can get done.

      TFA: from the book "Build Your Own Working Digital Computer" in 1968. The main program storage was an oatmeal container covered in foil...

      One oatmeal container oughtta be enough for anyone. -Gill Bates

      --
      Table-ized A.I.
    2. Re:My first computer, ever.. by kheldan · · Score: 1

      Are you mocking me, or are you just pointing out something funny?

      --
      Are YOU using the TOOL, or is the TOOL using YOU? Think about it!
    3. Re:My first computer, ever.. by Tablizer · · Score: 1

      All in jest. Your statement reminded me of Bill's (alleged) statement. Technically he may have been somewhat right, but vendors find ways to bloat things up out of sloth or corner cutting or goofy standards, such as including an entire library or driver even if you only need 3% of its functionality.

      --
      Table-ized A.I.
  18. Do miss the days.. by WillRobinson · · Score: 1

    Miss the days of the 6502 and Z80 with 8K of 2102 ram. Could heat my sandwich while I wrote assembler code on the card...

  19. Got the Look by Tablizer · · Score: 1

    The Mercury Delay unit is certainly visually impressive. You can really impress and/or scare somebody with a gizmo like that on or near your desk.

    --
    Table-ized A.I.
  20. The story of Mel, a real programmer. by Anonymous Coward · · Score: 1

    https://www.cs.utah.edu/~elb/folklore/mel.html

    1. Re:The story of Mel, a real programmer. by T.E.D. · · Score: 1

      Thank you! That was in fact the first story I was thinking about. Couldn't find it in my offline files, and couldn't remember enough details to help Google find it for me.

  21. programming on stone tablets by k6mfw · · Score: 1

    Not really but an advertisement for programming software in 1980s magazine. Picture of a stone tablet and a hammer and chisel. Tablet had partial listing of "FOR, NEXT" statements with tagline, "still programming the old fashion way?" One thing certain stone tablets will last a millennia!

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    mfwright@batnet.com
    1. Re:programming on stone tablets by Anonymous Coward · · Score: 0

      did the chisel say VI or EMACS on it?