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DARPA Invests $100 Million In a Silicon Compiler (eetimes.com)
The Defense Advanced Research Projects Agency (DARPA) will invest $100 million into two research programs over the next four years to create the equivalent of a silicon compiler aimed at significantly lowering the barriers to design chips. "The two programs are just part of the Electronics Resurgence Initiative (ERI) expected to receive $1.5 billion over the next five years to drive the U.S. electronics industry forward," reports EE Times. "ERI will disclose details of its other programs at an event in Silicon Valley in late July." From the report: Congress recently added $150 million per year to ERI's funding. The initiative, managed by the Defense Advanced Research Projects Agency (DARPA), announced on Monday that the July event will also include workshops to brainstorm ideas for future research programs in five areas ranging from artificial intelligence to photonics. With $100 million in finding, the IDEAS and POSH programs represent "one of the biggest EDA research programs ever," said Andreas Olofsson, who manages the two programs.
Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs "will change the economics of the industry," enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.
Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs "will change the economics of the industry," enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.
It's about time that such a strategic industry gets revived.
That makes sense if you look at the commercial chip design market. The process is error prone and expensive.
It makes a hell of a lot less sense if you look at some other people busy in the space. Like how Chuck Moore does his chip designs with a "silicon compiler" written by a single person. Meaning that DARPA could have effective chip design tools for as little as a hundred thousand dollars, iff they manage to find the right person to build it for them. Software design is funny like that, and we haven't started to scratch the surface of removing unneccesary complexity, so we're still paying through the nose for most of the software. Usually it's amortised through so many factors and other users that we can pretend to not notice. For one-offs like this... it suddenly becomes glaringly painful just how wasteful software projects tend to be. On top of that, the military-industrial complex is the world's biggest money waster, so this hundred million seems reasonable compared to their other money wasting projects. But it's still wasteful. Even though this is explicitly aimed at reducing costs. I conclude that's just the pretense, and this is really about pork barrels. Funny, eh.
In an industry that already spends billions of dollars on design and manufacturing of chips, as per the example of $500 million for a single SoC, what are you going to do with a measly $100 million ?
Can't private industry do these things?
DARPA have different requirements for chips than the rest of us. For example, they might not want separate "systems management" circuits.
Nice? Sure.
Trustworthy? Not one bit.
This is actually a project I've read about in the past so I'll explain. What they are trying to do is make a automatic layout engine for silicon. In effect, it will take your VHDL and turn it into a completed layout that is ready for manufacturing. However, to avoid a massive layout times, they also want to be able to use premade layouts for subsystems. If you consider each subsystem to be a block of object code then the layout engine is a compiler that is connecting your "main.c" up to all the functions already compiled.
It's a really good concept but the laws of physics won't make it an easy task and much like handwritten assembly, it's unlikely to be competitive with manual layouts.
Anons need not reply. Questions end with a question mark.
start with the fact you can't trust the builders.
Sure, if there is competition, they will innovate. But only because profit growth is the *only* goal. /you/ likely actually had to work for). So the ideal for-profit operation is a bank heist. ... No, that would still be work. Better: Get somebody *else* to steal money for you. ... No, wait, I can top that: make it the law that everyone who doesn't give you free money without you having to work is a criminal instead of you (like copyright) . ... Or, the best of all: Just use a law made by somebody else, that says you can borrow $8 from somebody else, to legally simply make up $92, and use that to get somebody to make $108 out of it with actual work, which they have to pay "back" to you, and then you can keep it. (Aka banking.)
But that goal normally means *minimizing* effort/cost. The ideal for-profit operation sells you something utterly worthless for insane amounts of money (that
And the cherry on top: Each year, his work will be worth less because of "inflation". Aka you demanding to steal an even bigger share of what's there.
Damn, I went off track there ... :)
But still, this is important. I'll post it as AC.
1 million for RD
99 million for patent lawsuits.
MS did not give a shit about innovation, because there was no competition.
I've been trying to understand what this actually does and after reading the article I still don't understand it!
The name Silicon Compiler is confusing beyond belief; traditional compilers convert programming languages to assembly, so a Silicon Compiler seams like it would convert different assembly languages, so code would run no matter the architecture.
The article seems to mention new ways to wire the different architectures, making me think it's a computer aided architecture design using AI, but then mentioned open sourcing the architecture design.
So I come back to you: What the hell does this "Silicon Compiler" actually do?
How would these tools differ from the open-source project IceStorm?
Most the innovation does not come from manufacturing. Big risk is what pure research does; some of it seems completely pointless at the time it is being done-- the applications of the gained knowledge are unknown at the time; furthermore, many things are discovered by accident.
This is $$$ put into "future work" areas that companies have little incentive to explore; especially companies on the market who are always under pressure to cut R&D for greater returns for investors.
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Silicon Compilers and a few other companies tried it in the 80's. Government also tried as part of VHSIC in the 80's. Never got very far. Granted compute is way faster these days. The result was if you wanted a part that was fast, the reason you do custom, the compiled parts did not measure up to custom. If you wanted a ok part, you could use a gate array back then and so why do a compiled part with the extra mask steps (GA's only need back end metalization) Today you use an FPGA.
As a former lead ASIC designer, I can say this is one of the most ambitious projects likely ever undertaken in EDA. Companies like Cadence, Mentor and Synopsys have been working on these problems for literally decades now. Everyone wants an easy solution for push-button design, but it is hardly that simple. Consider the following:
- Synthesis from RTL-to-gate level
- Functional design rule checks
- Place and route, including clock routing, PLLs/DLLs, etc.
- Timing extraction and static timing analysis
- I/O/SSO and core power
- Internal signal integrity and re-layout
- Test insertion and test vector generation
- Formal verification
- Functional verification
- Packaging and ball-out/bonding, especially with core I/O
- Physical design rule checks / Netlist vs. layout checks
A suite of tools that does all of this costs into the millions of dollars today, and is really a subscription as there are always bugs and improvements to be made. It also assumes physical design rule decks from the silicon vendors that have gone extensive characterization on limits such as minimum feature widths and notch rules can yield to a sufficient level economically, and that the gate and hard IP/mixed IP libraries have been validated. Front end functional design often requires re-architecture due to considerations when physically implementing the chip. All of this, of course, presumes that we don't run into additional phenomena that were irrelevant at larger process nodes (e.g. at ~250nm/180nm, wire delay dominated gate delay, and at 90nm/65nm, RC signal integrity models gave way to RLC, plus power/clock gating, multi-gate finFETs vs. single-gate planar past 22nm, etc.).
A push-button tool would have to take all of this into consideration. But let's face it...as well-intended as this is, you probably need another couple of orders of magnitude of money thrown at this to even begin succeeding under the fundamental assumption you don't have additional phenomena like alternatives to manufacturing. And that's the fundamental catch that is not captured in the article: we are chasing an ever-changing animal called process technology advancement that has created issues for us over the last few decades and likely will continue until we reach the limit of physics as we can manipulated them.
Bottom line: love the idealism, but don't buy into this hype with this piddle of investment.
Now just imagine how big the problem space will be when we start doing genetic engineering. Building chips would be childsplay in comparison.
Even the 20+ year old compilers still trip over fairly simple code structures and get lost. So good luck to them working on one from the ground up. For our current design our sub-chip design group has at least 2 it messed up but we figured a way to recode it so it worked bugs and 2 it gets stuck and we can't figure out why bugs along with a handful of other smaller bug reports in on the compiler. Yes it is one of the big 2 DA companies.
https://en.wikipedia.org/wiki/...
For this new age, targeting to EPIC is better than to VLIW due to the performance's weakness of VLIW. EPIC gives higher IPC with lesser penalties.
It is an enhancement of pipelined, superscalar, and out-of-order (don't use speculative execution because it does heat much).
And i like a combination of Tomasulo and Scoreboard algorithms for the EPIC's needs.
LARGE separated caches L1, L2, L3 give better perfornance!.
Intel owns full access to their entire IP portfolio(and others to specific parts) but as far as I can tell hasn't used any of the tech(with the exception of the longrun tech).
Now, if only DARPA held the competition for developing strategies against patent trolls... The real problem is that too my good technologies (including in manufacturing the chips) are likely to draw a lawsuit over patents or trade secrets from a foreign entity anyway. I'm glad DARPA and co. are encouraging the development of this technology, but let's not put the carriage before the horse... Look at the current dominance of companies like Qualcomm with the best patent warchest. Even Samsung has to buy chips from Qualcomm to operate in the US market. If the US wants more chips to be made here, we need to give serious thought to who owns the ideas and how broken that system is.
They often get a lot of bang for the buck because they attract more investment from partners in both academic research and business. That is what the DARPA Grand Challenge projects are all about. Remember the autonomous vehicle race from California to Las Vegas? Or the emergency rescue robot competition? Things like that.
In fact, both of those were "failures". The goals were not met. The robots fell over. No team finished the Mojave race. The prizes were not awarded. But the government got more then it's money's worth. And everyone who participated learned a whole lot. For DARPA that was a good result.
So stop whining about the futility of the project just because you are too short sighted to understand what it is really about. There are plenty of very very smart motivated people who do get it, and they are going to produce some very interesting work. Go back to computer and watch someone else play a video game. It's all you're good for.
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