I agree that strained silicon is a common source of research - that was the point of my post: exactly what did IBM do that causes this to be a breakthrough.
Also, I was not talking about the material properties of SiGe - but of strained Si on a SiGe lattice which is exactly what this press release was about.
Going through each of the points that I mentioned as downsides of the technology:
1. Thermal conductivity: this is a property of the bulk material. Even if the SiGe material is epitaxially deposited on a bulk Si wafer, there will still be a substantial layer of SiGe between the transistors and the bulk material. In flip-chip BGA technology cooling of a chip is from the backside - through the substrate. The substantially lower thermal conductivity of the graded SiGe material used to created the strained silicon lattice in the channel is fairly large and will act to isolate the transistors from the backside cooling, which will induced localized self-heating near the transistor. The temperature of the transistor will rise due to this effect which will reduce the mobility of the device.
2. Junction leakage: the lower conduction band in strained Si will lead to reduced Vt within the channel. This reduced Vt will contribute to enhanced switching performance, but will increase Ioff - the source/drain current that flows when the device is supposed to be off. If the process is modified to increase this Vt, then the mobility will be reduced.
3. The dielectric constant of SiGe - which forms the subtrate under the source and drain is substantially higher than the dielectric constant of Si. The parasitic junction cap in the source and drain to the substrate will thus be higher - not substantially but noticeably.
I would be interested to know on what basis you disagree with these three points. I have followed this subject with interest through my career as a microprocessor design engineer and consider myself very familiar with the issues involved and so I am very curious about the details of what they did.
Which leads back to my question - how did IBM solve these issues - particularly the first one - and if they didn't, then what makes this a breakthrough?
My first question is that researchers at IBM's Research Lab have been working on this for IBM for literally years. I remember reading papers from IBM on this exact same subject back six or seven years ago. They've been fabricating devices back in strained Si/SiGe interfaces and has been presenting papers documenting the mobility improvement for some time now. So the thing that I find truly puzzling is what is the breakthrough? It's not that I don't think this is great, but I fail to see what they are doing now that they weren't doing before.
So what is strained silicon - essentially it's a way of using the lattice mismatch of silicon and SiGe (silicon germanium) to create tensile strain near the material interfaces. This strain reduces carrier scattering and thus improves mobility for both electrons and holes in the inversion layer of the transistor channel. So, in less engineering speak, the charge carriers in the transistor move around easier and thus faster which improves transistor performance. This mobility improvement can be as high as 70% faster than 'normal' silicon channels.
It's worth mentioning the downsides of this technique - which I notice have been ignored in all the articles that I have read. Thermal conductivity of strained SiGe is substantially lower than 'normal' silicon - like an order of magnitude less. So the devices will be much hotter. This 'self-heating' of the devices results in reduced mobility of the charge carriers due to increased carrier scattering - so essentially the devices are so much hotter than they greatly reduce the effect that was created in the first place. Another issue is the fact that junction leakage is much higher. And another is that the higher dielectic constant and lower band-gap of SiGe result in higher junction capacitances in the transistors.
The technology is interesting, but I don't see how they managed to address the issues that have held back the technology so far. It's a shame that they didn't mention potential issues and how they worked around them in the press release, but I guess we'll have to wait for the technical papers at this year's conferences.
Here's a summary of the article from the sciam.com website:
The Small Planets Erik Asphaug
New space probe images offer the first close-ups of asteroids, the minute worlds that carry clues to how theplanets formed. Surprisingly, many asteroids are more like gravel piles than solid rock.
I disagree that the only possibility for this shape is by streching the material while it cools. It could be made of two solid chunks pushed together by gravity and the gap between filled by the dust from the collision. The shape of Eros is not completely dissimilar from that of this recently imaged picture of Kleo, and the current consensus leans towards the idea that Eros is a rubble pile - not a solid-core asteroid.
The April issue of Scientific American has a great article on the subject.
The latest issue of Scientific America discuss this subject in their cover story: whether asteroids are solid-core or rubble piles. You can't miss it, it's the one with the black and white picture of an asteroid (Eros?) on the cover. They conclude that most are probably rubble piles based on a variety of evidence, particularly rotational speed.
IMO, the best reasons for an asteroid as a space station are protection from radiation and not having to haul the raw material out of a gravity well. I agree with the above poster that you probably wouldn't want to spin it up to create gravity.
Excellent post that covers many of the problems relating to multiprocessors.
But 5-15 years?
That's quite a spread... If I were a betting man, I would guess on the very low side.
You have eloquently pointed out many of the problems, but many of the presentations at last years microprocessor forum dealt with multithreading and multiprocessing cores (the Power4 is the one that sticks out most highly in my mind, but there were others that I can't recall right now). Granted most of these designs were several years away from release, but the number of presentations seemed to indicate that most of the industry believes that multithreading/multiprocessing cores are the future.
It's clear that we are approaching the point where cache performance has begun to saturate. The days where you could double the cache on a CPU and expect enough of an increase in performance to justify presenting this as a new product are coming to a close right now. The future appears to be multiprocessing - despite all the problems that you described.
Since high-end CPUs seem to trickle down in the mainstream faster than most predict, I would bet on the low side of that 5-15 year spread.
There can be no doubt and no debate that BJT transistors are much better at driving current than CMOS transistors. But the added cost both to manufacturing and to design, the complexity of the circuitry compared to pure CMOS (look at a rail-to-rail BJT inverters and then look at a static CMOS inverter - and if the BJT inverter has resistors then consider temperature stability and how much area these resistors will take), and the issues relating to power dissipation (and thus heat), and finally reliability issues make designing CMOS look very good in comparision.
Having actually worked on the BiCMOS design of the Pentium on the 854.3 process, I'd be really interested in any links to this research work. My experience as a designer was pretty negative, from reliability to signal integrity to power problems (local power droop)... as far as I was concerned Intel made a great decision when it switched from BiCMOS on the P54CS to pure CMOS on the P55C.
Definitely not in microprocessor design... Exponential's Bipolar design was a complete flop and Intel left BiCMOS back with the Pentium 854 process and has never looked back. It never went away in analog design, so how do you figure that it's coming back?
I always thought that rather than take the risk of sneaking it into Mordor, they should have gone the other direction and dumped it at sea. You could make a chain out of mithril (rust-proof), attach it to a big rock and dump it when you are several hundred miles west of the shore.
Yeah, the problem would have surfaced again in a few millenia when the ring figured out how to get itself caught in someone's net or something. But in the meantime it would have been life as usual back in MiddleEarth. Destroying the ring meant the end of a lot of things - so don't destroy it at all.
Intel and AMD haven't exactly been "racing towards having the first chip out on copper". Intel bowed out of the race well over a year ago when it said that it had no plans to use copper interconnect on it's 0.18um process and may consider it for 0.13um. AMD, on the other hand, has said that they will be shipping their 0.18um process with copper interconnect before the end of the Q2 (IIRC).
The megahertz race has been going on since Q4 last year and is still heating up, but the copper race never really happened since Intel doesn't feel that it needs Cu in 0.18um.
It's definitely 1.5GHz. But still this is a only 50% increase over what will presumably be shipping from Intel's competition before this summer. It's no different from jumping 50% from 500MHz to 750MHz - which is pretty much what happened from summer last year to Christmas. A 50% jump in clock frequency in six months is starting to become status quo in this one-upsmanship game between Intel and AMD.
It's not going to be released any time soon, so who cares what the stability is? The engineers have more than half a year to iron out the bugs, why does it matter if it can run Word at 1.5GHz right now?
This article assumes that processing power will continue to follow "Moore's Law", but even Gordan Moore himself admits that this is not likely to happen. Most semiconductor experts believe that the smallest possible transistor gate is approximately 0.06um - or 60nm. It is possible to create transistors smaller, but current leakage (current that flows through the transistor when the transistor is turned off) will become such a problem at 80nm and smaller, that many high-speed current circuit techniques will no longer work (dynamic logic, pseudo-NMOS, etc).
I make the assumption that the massively billion dollar a year semiconductor industry will find an alternative to silicon which will allow continued growth, but it's hard to imagine this happening without a multi-year hiccup in which no foward progress is made, and afterwards it is likely that forward progress will be slowed significantly from the current rapid progress.
I've heard about this law (and I read all of the sub-threads here clarifying it) regarding mail-order purchases, but what about direct purchases in a store?
Several years ago, I purchased a video card in a store in Silicon Valley. It looked like what I purchased, but in fact, had much higher spec memory than it the product that I meant to purchase (and thus was meant to have been sold at a much higher price). The store called me several days later, explained the mix up and asked me to return the item in exchange for the lower spec item that I meant to purchase. I did, of course, return it and received the slower cheaper version, but I often wondered if I needed to.
If you purchase something in a store, leave the store, and they find out that they sold you a more expensive item at a much lower price, are you obligated to return it if they request you to?
How do you think "the bus allows better multiprocessor"? With a P2P bus, you need to interface the processors through the chipset rather than having a direct connection to other SMP processors. This introduces latency into the SMP and thus slows SMP operations such as snoops which will have a negative impact on the overall SMP system performace. For 2-way or 4-way SMP, the shared bus of the Pentium II and Pentium III will perform much better than any P2P SMP bus implementation. As regards scaleability, a shared bus scales just as well as a P2P, you just interface the shared busses through the chipset - similar to what needs to be done on P2P.
Don't get me wrong, I tend to think P2P was the right choice for the Athlon. Most users are not using SMP, and AMD is not currently making a concerted effort to penetrate the server and workstation market (they say that they are, but there have been no announcements of deals, no major customers are shipping Althlon workstations, etc. I assume that when they make a serious effort to penetrate the high-end market we will start to see the results in the form of press releases and deals with major OEMs). When they get the P2P SMP chipset out we will probably see a bigger push - but this chipset will be a tricky design, and I personally don't think we will see it any time in the near future (next summer maybe, probably next autumn).
My original point was to say that a shared bus architecture allows essentially "plug-and-play" SMP up to the limit of the stubs on the shared bus at the expense of bandwidth, while P2P allows high-speed communication between two ports (in this case the chipset and the CPU). Any extension of a P2P into an SMP architecture will inevitably take a latency hit. The original poster contended that Intel is behind in the FSB war, while, in fact, I consider the two busses to be different and not directly comparable by just looking at bandwidth.
The AMD 200MHz FSB used on the Athlon is a point-to-point bus. The Intel 133MHz FSB used on the Pentium III is a shared bus. They each have their own advantages and disadvantages. Point-to-point busses are inherently faster, while shared busses enable easy SMP. It's easy to say that "Intel is only now getting around to it [a 200MHz FSB]" but in truth, AMD's bus is not as amenable to a quick SMP solution - where are the multi-processor Athlons? If this supposed 200MHz FSB for the Willamette is a 4-stub shared bus it will be quite an achievement since these are quite tricky to design.
I pulled the price off of HP's direct sale's web site. Most often these are slightly more expensive, but in this case, I guess HP is ripping off it's direct sales customers.
Go here:
http://www.hp.com/jornada/products/680/overview. html
And click "Buy Online" to see the $900 price that I mentioned.
$680 is much better, but it's still too much to spend on a glorified organizer. But each to their own.
No arguements that a mini-laptop like a Jornada 690 is easier to type on. Of course, a real laptop is even easier in my opinion, and has more flexibility. When I need to take notes at a meeting, then I bring my laptop, but when I'm running around during the day, I bring my Palm 5000. I treat my Palm like it's a organizer and the only notes that I make on it are brief, but for real work, I use my laptop.
A Palmtop is smaller than a mini-laptop - this has all the disadvantages that a small size has... small screen that's hard to read, no keyboard, little or not expansion, etc. But, it is smaller. If you are like me and will only carry something around if it can fit in your pocket, then the Jornada is simply too big. Also a Palm is cheaper. Those Jornada 680's start at roughly $900. This is about 4X the price of a Palm IIIe, and approx. 1.5X the price of a Palm VII.
Still, there's no doubt that you are correct, Palms are for some, and not for others. I tell anyone who asks about my Palm, to buy one from a store with a good return policy.
No, Intel is the only x86 CPU manufacturer currently using a fuse-based ID'ing sysyem (the much maligned unique CPUID scheme). Since they are the only ones who actually burn the CPU speed onto the on-die fuses, the program is only going to work with their CPU's - and only the PIII line of those..
Eventually, however, I feel certain that all manufacturers will end up doing something similar. And, no doubt, someone will make an OpenSource version available, when there are enough people with CPU's who can use the program to motivate someone to write one.
This would be pretty foolproof, but in nearly all cases you would have to destroy the processor just to read the tab ID.
With the older PPGA parts, you would need to etch through the PPGA package, which would destroy the thermal integrity of the package reducing the part's reliability.
With BGA processors, I believe you would have to break the wire bonds, and I'm pretty sure that you wouldn't be able to rebond them afterwards.
Certainly the new flip-chip Pentium III (Coppermine) parts would be completely destroyed in the ID'ing process. Since the die is upside-down and directly bonds to the package... If you were to try and separate the die and the package (a tricky task in itself), there's no way you could put it back together when you were done.
I really think the best way to go is the way that Intel is doing it - burn out internal fuses within the chip after the packaging stage and then use a program to read out the values.
This would be pretty foolproof, but in nearly all cases you would have to destroy the processor just to read the tab ID.
With the older PPGA parts, you would need to etch through the PPGA package, which would destroy the thermal integrity of the package reducing the part's reliability.
With BGA processors, I believe you would have to break the wire bonds, and I'm pretty sure that you wouldn't be able to rebond them afterwards.
Certainly the new flip-chip Pentium III (Coppermine) parts would be completely destroyed in the ID'ing process. Since the die is upside-down and directly bonds to the package... If you were to try and separate the die and the package (a tricky task in itself), there's no way you could put it back together when you were done.
I really think the best way to go is the way that Intel is doing it - burn out internal fuses within the chip after the packaging stage and then use a program to read out the values.
Slashdot Mirror
I agree that strained silicon is a common source of research - that was the point of my post: exactly what did IBM do that causes this to be a breakthrough.
Also, I was not talking about the material properties of SiGe - but of strained Si on a SiGe lattice which is exactly what this press release was about.
Going through each of the points that I mentioned as downsides of the technology:
1. Thermal conductivity: this is a property of the bulk material. Even if the SiGe material is epitaxially deposited on a bulk Si wafer, there will still be a substantial layer of SiGe between the transistors and the bulk material. In flip-chip BGA technology cooling of a chip is from the backside - through the substrate. The substantially lower thermal conductivity of the graded SiGe material used to created the strained silicon lattice in the channel is fairly large and will act to isolate the transistors from the backside cooling, which will induced localized self-heating near the transistor. The temperature of the transistor will rise due to this effect which will reduce the mobility of the device.
2. Junction leakage: the lower conduction band in strained Si will lead to reduced Vt within the channel. This reduced Vt will contribute to enhanced switching performance, but will increase Ioff - the source/drain current that flows when the device is supposed to be off. If the process is modified to increase this Vt, then the mobility will be reduced.
3. The dielectric constant of SiGe - which forms the subtrate under the source and drain is substantially higher than the dielectric constant of Si. The parasitic junction cap in the source and drain to the substrate will thus be higher - not substantially but noticeably.
I would be interested to know on what basis you disagree with these three points. I have followed this subject with interest through my career as a microprocessor design engineer and consider myself very familiar with the issues involved and so I am very curious about the details of what they did.
Which leads back to my question - how did IBM solve these issues - particularly the first one - and if they didn't, then what makes this a breakthrough?
My first question is that researchers at IBM's Research Lab have been working on this for IBM for literally years. I remember reading papers from IBM on this exact same subject back six or seven years ago. They've been fabricating devices back in strained Si/SiGe interfaces and has been presenting papers documenting the mobility improvement for some time now. So the thing that I find truly puzzling is what is the breakthrough? It's not that I don't think this is great, but I fail to see what they are doing now that they weren't doing before.
So what is strained silicon - essentially it's a way of using the lattice mismatch of silicon and SiGe (silicon germanium) to create tensile strain near the material interfaces. This strain reduces carrier scattering and thus improves mobility for both electrons and holes in the inversion layer of the transistor channel. So, in less engineering speak, the charge carriers in the transistor move around easier and thus faster which improves transistor performance. This mobility improvement can be as high as 70% faster than 'normal' silicon channels.
It's worth mentioning the downsides of this technique - which I notice have been ignored in all the articles that I have read. Thermal conductivity of strained SiGe is substantially lower than 'normal' silicon - like an order of magnitude less. So the devices will be much hotter. This 'self-heating' of the devices results in reduced mobility of the charge carriers due to increased carrier scattering - so essentially the devices are so much hotter than they greatly reduce the effect that was created in the first place. Another issue is the fact that junction leakage is much higher. And another is that the higher dielectic constant and lower band-gap of SiGe result in higher junction capacitances in the transistors.
The technology is interesting, but I don't see how they managed to address the issues that have held back the technology so far. It's a shame that they didn't mention potential issues and how they worked around them in the press release, but I guess we'll have to wait for the technical papers at this year's conferences.
* Not Speaking for Intel Corp. *
Oops. May issue (the current one), not April.
Here's a summary of the article from the sciam.com website:
The Small Planets
Erik Asphaug
New space probe images offer the first close-ups of asteroids, the minute worlds that carry clues to how theplanets formed. Surprisingly, many asteroids are more like gravel piles than solid rock.
I disagree that the only possibility for this shape is by streching the material while it cools. It could be made of two solid chunks pushed together by gravity and the gap between filled by the dust from the collision. The shape of Eros is not completely dissimilar from that of this recently imaged picture of Kleo, and the current consensus leans towards the idea that Eros is a rubble pile - not a solid-core asteroid.
The April issue of Scientific American has a great article on the subject.
The latest issue of Scientific America discuss this subject in their cover story: whether asteroids are solid-core or rubble piles. You can't miss it, it's the one with the black and white picture of an asteroid (Eros?) on the cover. They conclude that most are probably rubble piles based on a variety of evidence, particularly rotational speed.
IMO, the best reasons for an asteroid as a space station are protection from radiation and not having to haul the raw material out of a gravity well. I agree with the above poster that you probably wouldn't want to spin it up to create gravity.
Thanks for the links... I'll check them out.
Excellent post that covers many of the problems relating to multiprocessors.
But 5-15 years?
That's quite a spread... If I were a betting man, I would guess on the very low side.
You have eloquently pointed out many of the problems, but many of the presentations at last years microprocessor forum dealt with multithreading and multiprocessing cores (the Power4 is the one that sticks out most highly in my mind, but there were others that I can't recall right now). Granted most of these designs were several years away from release, but the number of presentations seemed to indicate that most of the industry believes that multithreading/multiprocessing cores are the future.
It's clear that we are approaching the point where cache performance has begun to saturate. The days where you could double the cache on a CPU and expect enough of an increase in performance to justify presenting this as a new product are coming to a close right now. The future appears to be multiprocessing - despite all the problems that you described.
Since high-end CPUs seem to trickle down in the mainstream faster than most predict, I would bet on the low side of that 5-15 year spread.
There can be no doubt and no debate that BJT transistors are much better at driving current than CMOS transistors. But the added cost both to manufacturing and to design, the complexity of the circuitry compared to pure CMOS (look at a rail-to-rail BJT inverters and then look at a static CMOS inverter - and if the BJT inverter has resistors then consider temperature stability and how much area these resistors will take), and the issues relating to power dissipation (and thus heat), and finally reliability issues make designing CMOS look very good in comparision.
Having actually worked on the BiCMOS design of the Pentium on the 854.3 process, I'd be really interested in any links to this research work. My experience as a designer was pretty negative, from reliability to signal integrity to power problems (local power droop)... as far as I was concerned Intel made a great decision when it switched from BiCMOS on the P54CS to pure CMOS on the P55C.
Bipolar is coming back? How do you figure?
Definitely not in microprocessor design... Exponential's Bipolar design was a complete flop and Intel left BiCMOS back with the Pentium 854 process and has never looked back. It never went away in analog design, so how do you figure that it's coming back?
How exactly do you figure that GaAs requires less effort than Si?
I always thought that rather than take the risk of sneaking it into Mordor, they should have gone the other direction and dumped it at sea. You could make a chain out of mithril (rust-proof), attach it to a big rock and dump it when you are several hundred miles west of the shore.
Yeah, the problem would have surfaced again in a few millenia when the ring figured out how to get itself caught in someone's net or something. But in the meantime it would have been life as usual back in MiddleEarth. Destroying the ring meant the end of a lot of things - so don't destroy it at all.
It was something that I've thought about before.
Intel and AMD haven't exactly been "racing towards having the first chip out on copper". Intel bowed out of the race well over a year ago when it said that it had no plans to use copper interconnect on it's 0.18um process and may consider it for 0.13um. AMD, on the other hand, has said that they will be shipping their 0.18um process with copper interconnect before the end of the Q2 (IIRC).
The megahertz race has been going on since Q4 last year and is still heating up, but the copper race never really happened since Intel doesn't feel that it needs Cu in 0.18um.
* Speaking only for myself *
It's definitely 1.5GHz. But still this is a only 50% increase over what will presumably be shipping from Intel's competition before this summer. It's no different from jumping 50% from 500MHz to 750MHz - which is pretty much what happened from summer last year to Christmas. A 50% jump in clock frequency in six months is starting to become status quo in this one-upsmanship game between Intel and AMD.
It's not going to be released any time soon, so who cares what the stability is? The engineers have more than half a year to iron out the bugs, why does it matter if it can run Word at 1.5GHz right now?
> I just love that futuristic computer stuff;
> D&D-style virtual gaming worlds, yeah!
Did you ever read the Dream Park series of books? They are essentially D&D-style virtual gaming world books.
They are by Larry Niven and Steve Barnes
Dream Park
The Barsoon Project
The California Voodoo Game
The first is my favorite, although I quite enjoyed all of them.
Excellent point!
This article assumes that processing power will continue to follow "Moore's Law", but even Gordan Moore himself admits that this is not likely to happen. Most semiconductor experts believe that the smallest possible transistor gate is approximately 0.06um - or 60nm. It is possible to create transistors smaller, but current leakage (current that flows through the transistor when the transistor is turned off) will become such a problem at 80nm and smaller, that many high-speed current circuit techniques will no longer work (dynamic logic, pseudo-NMOS, etc).
I make the assumption that the massively billion dollar a year semiconductor industry will find an alternative to silicon which will allow continued growth, but it's hard to imagine this happening without a multi-year hiccup in which no foward progress is made, and afterwards it is likely that forward progress will be slowed significantly from the current rapid progress.
I've heard about this law (and I read all of the sub-threads here clarifying it) regarding mail-order purchases, but what about direct purchases in a store?
Several years ago, I purchased a video card in a store in Silicon Valley. It looked like what I purchased, but in fact, had much higher spec memory than it the product that I meant to purchase (and thus was meant to have been sold at a much higher price). The store called me several days later, explained the mix up and asked me to return the item in exchange for the lower spec item that I meant to purchase. I did, of course, return it and received the slower cheaper version, but I often wondered if I needed to.
If you purchase something in a store, leave the store, and they find out that they sold you a more expensive item at a much lower price, are you obligated to return it if they request you to?
How do you think "the bus allows better multiprocessor"? With a P2P bus, you need to interface the processors through the chipset rather than having a direct connection to other SMP processors. This introduces latency into the SMP and thus slows SMP operations such as snoops which will have a negative impact on the overall SMP system performace. For 2-way or 4-way SMP, the shared bus of the Pentium II and Pentium III will perform much better than any P2P SMP bus implementation. As regards scaleability, a shared bus scales just as well as a P2P, you just interface the shared busses through the chipset - similar to what needs to be done on P2P.
Don't get me wrong, I tend to think P2P was the right choice for the Athlon. Most users are not using SMP, and AMD is not currently making a concerted effort to penetrate the server and workstation market (they say that they are, but there have been no announcements of deals, no major customers are shipping Althlon workstations, etc. I assume that when they make a serious effort to penetrate the high-end market we will start to see the results in the form of press releases and deals with major OEMs). When they get the P2P SMP chipset out we will probably see a bigger push - but this chipset will be a tricky design, and I personally don't think we will see it any time in the near future (next summer maybe, probably next autumn).
My original point was to say that a shared bus architecture allows essentially "plug-and-play" SMP up to the limit of the stubs on the shared bus at the expense of bandwidth, while P2P allows high-speed communication between two ports (in this case the chipset and the CPU). Any extension of a P2P into an SMP architecture will inevitably take a latency hit. The original poster contended that Intel is behind in the FSB war, while, in fact, I consider the two busses to be different and not directly comparable by just looking at bandwidth.
The AMD 200MHz FSB used on the Athlon is a point-to-point bus. The Intel 133MHz FSB used on the Pentium III is a shared bus. They each have their own advantages and disadvantages. Point-to-point busses are inherently faster, while shared busses enable easy SMP. It's easy to say that "Intel is only now getting around to it [a 200MHz FSB]" but in truth, AMD's bus is not as amenable to a quick SMP solution - where are the multi-processor Athlons? If this supposed 200MHz FSB for the Willamette is a 4-stub shared bus it will be quite an achievement since these are quite tricky to design.
I pulled the price off of HP's direct sale's web site. Most often these are slightly more expensive, but in this case, I guess HP is ripping off it's direct sales customers.
Go here:
http://www.hp.com/jornada/products/680/overview
And click "Buy Online" to see the $900 price that I mentioned.
$680 is much better, but it's still too much to spend on a glorified organizer. But each to their own.
No arguements that a mini-laptop like a Jornada 690 is easier to type on. Of course, a real laptop is even easier in my opinion, and has more flexibility. When I need to take notes at a meeting, then I bring my laptop, but when I'm running around during the day, I bring my Palm 5000. I treat my Palm like it's a organizer and the only notes that I make on it are brief, but for real work, I use my laptop.
A Palmtop is smaller than a mini-laptop - this has all the disadvantages that a small size has... small screen that's hard to read, no keyboard, little or not expansion, etc. But, it is smaller. If you are like me and will only carry something around if it can fit in your pocket, then the Jornada is simply too big. Also a Palm is cheaper. Those Jornada 680's start at roughly $900. This is about 4X the price of a Palm IIIe, and approx. 1.5X the price of a Palm VII.
Still, there's no doubt that you are correct, Palms are for some, and not for others. I tell anyone who asks about my Palm, to buy one from a store with a good return policy.
No, Intel is the only x86 CPU manufacturer currently using a fuse-based ID'ing sysyem (the much maligned unique CPUID scheme). Since they are the only ones who actually burn the CPU speed onto the on-die fuses, the program is only going to work with their CPU's - and only the PIII line of those..
Eventually, however, I feel certain that all manufacturers will end up doing something similar. And, no doubt, someone will make an OpenSource version available, when there are enough people with CPU's who can use the program to motivate someone to write one.
This would be pretty foolproof, but in nearly all cases you would have to destroy the processor just to read the tab ID.
With the older PPGA parts, you would need to etch through the PPGA package, which would destroy the thermal integrity of the package reducing the part's reliability.
With BGA processors, I believe you would have to break the wire bonds, and I'm pretty sure that you wouldn't be able to rebond them afterwards.
Certainly the new flip-chip Pentium III (Coppermine) parts would be completely destroyed in the ID'ing process. Since the die is upside-down and directly bonds to the package... If you were to try and separate the die and the package (a tricky task in itself), there's no way you could put it back together when you were done.
I really think the best way to go is the way that Intel is doing it - burn out internal fuses within the chip after the packaging stage and then use a program to read out the values.
This would be pretty foolproof, but in nearly all cases you would have to destroy the processor just to read the tab ID.
With the older PPGA parts, you would need to etch through the PPGA package, which would destroy the thermal integrity of the package reducing the part's reliability.
With BGA processors, I believe you would have to break the wire bonds, and I'm pretty sure that you wouldn't be able to rebond them afterwards.
Certainly the new flip-chip Pentium III (Coppermine) parts would be completely destroyed in the ID'ing process. Since the die is upside-down and directly bonds to the package... If you were to try and separate the die and the package (a tricky task in itself), there's no way you could put it back together when you were done.
I really think the best way to go is the way that Intel is doing it - burn out internal fuses within the chip after the packaging stage and then use a program to read out the values.