Slashdot Mirror
Silicon Will Get CPUs To .07 Micron
ruiner writes: "This post at EE Times discusses that it now appears that silicon dioxide can be used as an insulator down to a process of .07 micron for processors. This will buy processor manufacturers a few more years to develop solutions for smaller processes. "
Too bad all these processes only allow companies w/billions of dollars in the bank to play.
That's all good and well, but are we really that interested in watching Intel and AMD push the same tech up a few more mega(or giga)hertz? I'm all for milking the technology we have, but its about time they move on to something a little more exciting. The next step is 10Ghz, not 1.1Ghz. We are fast approaching a time when 200 more mhz doesn't mean a thing.
SM
It's really sad that people have to keep delaying the inevitable wall in processing power. I say scientists should just face it now and forget about working on .07 Micron microprocessors.
Oh boy! another how-low-can-you-go estimate from Silicon Valley. Next week it will be .007 microns.
We're here to give you an OS, not a religion.
What I'd really like to see is a helluva powerful consumer device released before its commercial counterpart. Not just helluva powerful, but something that would be like comparing a GeForce 256 DDR to a CGA card.
"Assume the worst about people, and you'll generally be correct"
> The next step is 10Ghz, not 1.1Ghz
:: 150 MHz : 100 MHz. (I think I got that notation right).
What an excellent idea! Why didn't *my* company think of it first! Forget that that piddly 1 GHz crap, why don't we just jump straight to 10? I'll get right on it...
Are you really trying to tell me that you were content with your 100 MHz Pentium Classic right up until a month or so ago when that 1 GHz chips came out? All of those small jumps in the middle there didn't mean a thing, I suppose.
While it's true that the steps that companies increment their clock in should be increasing (they should now be releasing in 50-100 MHz steps, not 33 MHz steps), the percentages should scale. 1.5 GHz : 1 GHz
Now, I *do* think that the race to 1 GHz was kind of silly, but hey! It was marketing. Faster is better, but clock isn't everything. Intel hasn't released a new core since 1996, and you can really feel it. Coppermine and others are slight improvements, but they really need to get their new architecture (IA-64) out the door. Athlon is still eating their lunch.
just a disgruntled computer architect,
--Lenny
Faster chips are great but x86 is getting tired and the I/O on a PC is really limiting the usefullness of the chips we're capable of making now. We need a platform capable of useing what we have now.
When someone yells "Stop" or goes limp, or taps out, the fight is over.
Electrical signals travel at the speed of light. Therefore, the smaller you can make a circuit, the faster a signal will get from one end of it to the other. And of course you can pack more of them into a given area, leading to smaller die size, which equates to more units per wafer, higher yields, and lower prices.
At this point we're getting to the limits of what can be done on a silicon substrate. The problem here is that with circuits smaller than 0.07 micron, you are in danger of splitting silicon atoms if you pump any energy at all through the circuit. Yes, you read that right -- splitting silicon atoms, resulting (theoretically) in a release of energy equivalent to the Hiroshima bomb. This, as you may have guessed by now, is the real reason the US government considers high-powered CPUs to be "munitions". Just imagine what could happen if a bunch of Islamic terrorists got hold of a few thousand such CPUs and set themselves up as a mail-order PC company.
This is not, by the way, a problem unique to ICs. The real reason for the classification of data compression products as "munitions" is related to this too. You see, if data is compressed too much, the atoms comprising the individual bits can actually begin to participate in atomic fusion, leading (for a 32 kb block of data) to a release of energy equivalent to the original H-bombs of the 1950s. There are some papers here to document all this.
Just goes to show... the government doesn't always tell you the real reasons for the decisions they make, but that doesn't mean those reasons aren't justified.
And ever they shall continue to speed up, grow smaller, and generate more heat. I'm still waiting for them to end this old idea of using silicon and move to something that can be used easier and faster. Technology can make the "bio" chips, etc, but the question is, do they delay because the new tech is still new, or because intel/amd wants to squeeze a few more bucks by creating more? Which comes to another question, how far along are we with these other technologies, and are they truely as fast/cool as we're made to believe.
"When will this FP stuff stop?" "After the great growing..." "The great growing?" "Yea, when people grow up."
Speed is all very well and good, but don't forget that having chips run with less voltage will let them run at least somewhat cooler. This is great, but I guess it also means that I won't be able to heat my home with my computer while I'm playing Quake III.
This is interesting. We often hear about how new technology is going to completely and totally change everything overnight. Yet it seems to me that this rarely if ever happens. Even the internet has taken a few years to become mainstream and change the way we live. Granted, some technological advances change the playing field immediately, for example, quantum computing will wreak havoc on the Cryptography world. But it seems that often no matter how advanced the new technology may be, it takes time for it to fully impact society.
Goody. If the rate of CPU growth slows, it'll force people to realized speed gains by actually writing more efficient code. Eat that, Wintel!
Can your IM do this?
This is stretching the limits of physics. A 70 nm layer is only about 200-300 Si=O bonds thick. We're almost in the area where quantum effects become an overriding concern. I can't be bothered to work out the probability of an electron with a given voltage tunnelling through a layer this thin, but I suspect that we are in the area where voltage regulation and temperature control become *very* important. Put another way, these babies won't be candidates for aggressive overclocking.
What this really means is that we *may* have a little longer to go before we have to start using 'exotic' oxides. This is good news. One of the great things about SiO2 is that the manufacturing properties are well understood (although, at this size, lithography is going to be, er, interesting.
And they say there's a chance that they can take it even further. Gordon Moore will be pleased. His law looks good for the forseeable future.
Chip makers seem to only be concerned about whether or not the gates will live for 10 years? While most 10-year-old chips are so old that they're not even keychains anymore, it seems odd that there's an almost guaranteed failure several years down the road. Most people (at least in the US) get a new computer at least once every ten years, but in less affluent countries, this may not be the case. However, it seems that the chip makers (read evil corporations) are forcing this upon them.
I figure that once companies realize the limit, they'll collude and only release faster processors in small increments in "competition" with each other to leech as much money as they can. The alternative is that the first one to reach the limit sells to everyone to get the money before the other guy (Intel vs AMD), but then everyone is out of business because the market is satisfied until freaky quantum or holographic or whatever technology is developed.
How close is anyone to that stuff?
Instant Crisis
I actually do that. I use my computer to heat my bedroom. I go in and turn it on a little while before I want to use it if my room is a little cool. The room heats right up. I've often joked about my twenty-five hundred dollar space heater. How many people do this? Do I smell a new poll?
PS. Sorry if this message is duplicated. I'm having trouble submitting. This T3 just doesnt cut it sometimes
/*--Why can't I find the QNX OS on any warez sites?
* (above comment useless as of 4-26-2000)
*/
Can Slashdot pul-eeze not use the marketing buzzphrase "solution" ??? I'm sorry I hate this meaningless management word and loathe to see it in my favorite tech spot. The wise Hemos could have just written "develop smaller processors" and meant the same thing.
Sorry, I started thinking "solution" was overused when Rite Aid started printing it on its receipts. "Your total store solution" or somesuch rot. . .
Sounds like a .05m channel length to me. 1.5 nm Oxide thickness is mindblowing, considering I'm working with 70 nm right now. It's great to see silicon die decreasing in size. Too bad it doesn't relate to CPUs at all, at least not at such an early stage in the research. To get reproducible results on a large scale, entire processes will have to be reworked, this will take at least five years to even become anywhere near viable for a CPU. Oxide will get ICs to .07m, but it will take a while for the CPU usability of this process to reach maturity. We've had .25 micron for over ten years. It's only been in use for the past three.
Lithography is going to take a while for this stuff to catch up, too. The traditional Novolac/Diazonapthoquinone(DNQ) resist won't stand up at such a small feature size. It should be interesting to see if PolyHydroxyStyrene(PHS) can even hold up well at such a small feature size. 157nm Lithography is a ways off for industry. 193nm is nearly standard now, and it's an _extremely_ easy process to wreck.
Here's the previous "story" on CPU exploding virii
you are in danger of splitting silicon atoms if you pump any energy at all through the circuit. Yes, you read that right -- splitting silicon atoms, resulting (theoretically) in a release of energy equivalent to the Hiroshima bomb
So here's a quick way to end the world...
while (1);
I think most people misunderstand what's going on here.
The story is about the SiO2 insulator thickness. This oxide sits under the gate of the transistor which is used to control the flow between the source and drain.
This is 0.07um OXIDE THICKNESS, which is NOT the same as the gate length. The gate length is the usual parameter quoted when referring to a process (i.e. 0.25um, 0.18um, etc).
The problem is that if the gate oxide is too thin, you really screw up the transistor. All sorts of nasty reliability problems with hot carrier damange and what not. (Not to mention device performance).
But you can't have super-thick oxides relative to the gate width. There would be millions of tiny thin, but tall patterns which you have to expose, wash and deposit properly and it just doesn't work.
Hey , I may be wrong but if it was possible to split an atom with a circut board do you really think they would be using tons of super high explosives and huge missiles to catapult these things half way around the world? no.
These smaller processes are great...assuming anybody can figure out how to use them. The problem is, as processes get smaller, the actual chip stays the same size (or sometimes gets bigger). The problem with this is as processes get smaller, so do the wires on the chip. A wire of the same length as in a previous chip would be slower in the new chip because of the reduced driver sizes, thinner wires (increased resistance), and the relatively unchanging capacitance. (The capacitance per unit length stays about the same at smaller sizes because of fringing effects.) This can make device performance very low, especially if you have wires running from one end of the chip to the other, not to mention more susceptible to noise. There are ways to combat these problems (like inserting inverters periodcally along long wires to reduce noise and improve speed--Intel actually has a requirement for this, although it does chew up more power), but I don't think anybody has found a way to get the full performance out of what we currently have.
However, I must say that getting rid of the x86 architechture will certainly help....
I used to use a 6200 series TENCOR unit to count dirt (Yes I was a dirt counter, what of it) on silicon wafers after processing and it could see dirt smaller than that...so if the laser can distinguish dirt at that size perhaps the beam width is that size or smaller. Maybe they can start burning the tracts instead of using the photolithography etching technique. I think people are trying to stretch the envelope of one tech without rethinking other techniques...of course they only have billions of dollars invested in equipment that does it that way. Plus who would want to move the ion implanter out of the building...its only the size of a bus, in a building with 8 foot doorways. Maybe they dont change because no one wants to move that crap. They should just buy a few cases of beer and call some (sucker) friends over!
Where are the keys to my whore?
Advances like this first get used on 'real' computers - serious SMP servers like IBM's SP series of RS6000s, Suns high-end servers (Starfire), Compaq's WildFire Alpha boxes (drool) and, soon, servers based on AMD Sledgehammer and Intel Merced (Itanium) / Willamette chips.
Machines like this are used for *serious* numbercrunching. They predict the weather, model the economy, help design planes and spacecraft and find oil. These are tasks for which there is still a serious demand for MIPS.
Because of the astounding cost of developing these technologies, it takes years for them to trickle through to the desktop.
I admit that when decent processors get to the desktop, they are wasted. I did some low-level monitoring of my mother's PIII 450 recently. She runs Win98 and MS Word. The processor spends 99.2% of it's time idle, and 60% of it's active time it's waiting for cache misses. The cache miss problem isn't going away any time soon, because memory is still not getting faster at a high enough rate. The only realistic cure is for compiler writers to continue developing *very* clever optimisers. This is happening, but optimisations like this are deep magic.
I/O in modern servers using proprietary technology is awesome. Check out the IBM SP servers for more info. (Can't find the link - I have it on CD). Unfortunately, PCs are hampered by 'legacy' technologies like PCI. There is at least one serious attempt to address this - the Next Generation I/O project
Moderate this comment up.
that makes no sense, what do you think the 20th century of computing 'belonged' to? *SOMEONE* had to invent the vaccuumn tube, *SOMEONE* invented the transistor. and i dont think Lee de Forest or Shockley and his group were geologists!
- "Hear that?! The percolations are imminent! Cease your ingress!"
No, this is transistor size. The oxide thickness they are talking about is 15 angstroms, which is far smaller than 0.07 microns. Current oxide thicknesses for modern processes are on the order of 100 angstroms or less (which is 0.01 microns or 10 nm).
Especially if the programmer messes things up by trying to hand-optimize!
Having the programmer use goto statements and hand-unroll loops usually makes things worse. It is far, far better to have the programmer concentrate on the high-level algorithm design.
Small-scale hand-optimization will do squat if your algorithm is exponential.
The compiler can do a whole lot if the programmer lets it do its job. That includes making careful use of C++ inlinig and templates!
--
Couple this new technology with the tiny hard drive technology mentioned on Slashdot a week or two back and we could eventually see Supercomputer wrist watches! Or for that matter many other devices. We may just see the next really big technological advance in our time. But we must always remember, the government takes roughly 30% of ever single paycheck earned in this entire country(U.S.) And on top of that they take about 6% on most retail sales. And there are countless other taxes. There are millions and millions of people working and paying taxes, My point they have an amazing amount of money and plenty of agendas. They must have absolutely amazing technology. I mean , they have thousands of the very best scientist and practically unlimited funds. One wonders about what they have already had for years.... and more importantly what they are or are planning on doing with it. But anyway I'm excited to see where all this goes... If anyone here has any further information about anything like this already in the works(conspiracy theorys, or people already planning on useing alot of these new experimental technologies together)please reply =)
Wake me when they deliver some really exciting news about signifigantly faster bus speeds and RAM...or greatly improved cache.
Well that's all well and good if that's what makes you happy. I'm not sure where you live, but I'm in America and we speak English here. American English is a combination of many languages along with MANY valid words we just made up ourselves. I personally don't much care about the latin language. If you do, that's fine.
/*--Why can't I find the QNX OS on any warez sites?
* (above comment useless as of 4-26-2000)
*/
tcd004
They've been saying we'll reach the end of the useful life of silicon for quite a while now. And each time they get close, they figure out how to bum it down by a few microns. I betcha when they get close to .07, they'll figure out how to bum it down again...
I'm trying to teach myself to set people on fire with my mind... Is it hot in here?
That's your penis? I thought I was eating a piece of spaghetti!
Looks like smooth sailing to me!
Lacking <sarcasm> tags,
Actually, you proved my point. The reason the plural of virus is viruses, is because it's the only thing that makes sense in English. Viruses isn't a Latin word at all. The point is that the made-up "Latin" alternatives don't make sense. The Oxford English Unabridged lists "viruses" as the plural.
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Celebrate the finer things in life
Secondly, companies aren't going to flog off any more computers, just because the processor is smaller. It would make much more sense, IMHO, to use the scale improvements to build multi-processor CPUs. (If the next generation of Intels or AMDs packed 16 ix64's into a single unit the size of current processors, with all necessary SMP stuff thrown in, you'd have a truly powerful computer.)
Last, but not least, why use all these improvements on the processor? It's not been the bottleneck for years! If you designed a wafer-scale RAM chip at 0.07 microns, you'd be looking at computer memories in the region of 512+ TERAbytes! Can you imagine how responsive KDE would be with that?
It's a small world and it smells funny; I'd buy another if it wasn't for the money; Take back what I paid (SoM)
Gives new meaning to the term "dirt-cheap computers"...
It's not a latin word? What have you been smoking? My latin dictionary (don't have it here right this sec) says that 'virus' means 'poison'.
The plural of 'virus' is 'viri'.
OK, a silicon transistor as small as 0.07 um (that's the drain-source distance AFAIK) will work, but that doesn't solve everything. I've seen somewhere between .02 and .03 as being the limit for silicon (a previous Slashdot story talked about a .03 um transistor realized in a lab). The real problems are more practical.
.07 process? You cannot modify the current lithography process to do that. It would require far UV, for which no transparent materials are known. The alternatives go from X-Ray (IBM) to electron beam (Lucent), but none of these alternative is close to being production ready.
.07 um CPU the size of a PIII would contain ~200,000,000 transistors. Since it would probably run a coupe GHz, The heat will likely be close to a kilowatt - impossible to cool with just a fan. Plus it would also cost ~$30/month just to leave your computer running 7/24. Breaking the Linux uptime record wound thus cost about $1000 in electricity.
First, how do you build a CPU with a
The second practical problem: cooling! A
Opus: the Swiss army knife of audio codec
will I be able to download porn any faster? (an indirect simpsons reference)
"Tread softly because you tread on my dreams"
5. Breakup of Microsoft Predicted
4. Death of x86 Architecture Predicted
3. Death of FORTRAN Predicted
2. Year of the Network Predicted (okay, so they finally got one right)
and finally, the #1 headline we've seen too many times in the last 20 years...
1. Death of Moore's Law Predicted!
--j
I'm a nature photographer.
HAH!! Finally,has the concept come full circle.In the olden days(before Windows),code had to be as efficent as possible.The younger programmers are just discovering that efficent coding works faster?? Efficent code is ugly,but looks aren't everything.Functionality is part of the solution as well. The only reason CPU speeds has went as far up as it has is because of the sloppy coding for Windows making a speedup necessary in order to operate at a decent speed. Why do you think a short-to-the-point solution is called quick & dirty? Call me the old man from the mountains,but Windows has gotten slower and sloppier after each version is "Upgraded!!",and I would rather have an operation system that is efficent,not pretty.Cosmetics can be added later.
Geek Hillbilly
Virus is a Latin word. Viruses is not. The root is virus, Latin for poison, yes. But the plural is not viri. Check out this link for more information. Not every word ending in -us has -i in the plural. Virus is a defective noun. Even some Latin dictionaries have that wrong.
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Celebrate the finer things in life
The x86 architecture is not the only architecture to use silicon. Every CPU out there today uses silicon, so something like this is not only for x86. So an announcement like this affects pretty much all computers, not just x86 PCs.
Chris Hagar
"The price of freedom is eternal vigilance." - Thomas Jefferson
This argument played out a couple weeks ago on another story...
Result: Everyone left still thinking that they were right
1) English is a dynamic language. What comes into common usage becomes language. Therefore, Virii/Viri is/are word/s.
2) It was a latin base, so therefore Viri/Virii is the proper plural.
3) It may have been a latin base, but it's an english word, and the dictionary says it's viruses.
4) You all suck, shut up and go away.
I think that pretty much summarizes the argument.
I won't take sides, but the longer this goes on, the more I agree with #4...
"It's tough to be bilingual when you get hit in the head."
Solid state photonics is coming, and there's nothing you can do about it.
Solid state photonics will still have its feature size limited by the wavelength of the light used within its devices. _Current_ integrated circuit chips use feature sizes that are much smaller - by the time photonics matures, it will already be left in the dust as far as density is concerned.
Use smaller wavelengths of light? Not unless you want to destroy your material by photoionization.
Your next logical argument is to point out that most proposed photonic devices are three-dimensional. My logical counterargument is to point out that you can build three-dimensional electrical devices too. It's just currently cheaper to shrink 2D fabrication processes.
Your next probable point is to make noise about propagation delay in electrical circuits. It turns out that these aren't the limiting issue in conventional ICs - heat dissipation is.
Your next likely point is to say that a photonic circuit would have less heat dissipation. My response is that I'll believe it when I see it. Absorption happens, and whatever diode lasers are pumping this device won't be perfectly efficient either.
Lastly, I'd like to point out that most of the effort that goes into designing integrated circuits goes into designing the logic, not the fabrication processes. Computer engineers would still be employed in your hypothetical universe. Electrical engineers design motherboards and specialized analog ICs, both of which would still exist, so they wouldn't be out of work either.
Summary: Photonics is not the magic wand you hold it out to be.
However, once you get down to a certain size. Something called quantum tunneling becomes a real problem...the sort of stuff that defies conventional physics.
Chris Hagar
"The price of freedom is eternal vigilance." - Thomas Jefferson
This is the single worst comment in the Linux kernel, and I don't even have to look at the rest of them to know it.
Fast code does not have to be messy. In C, goto should be used for very few things. One example is breaking out of a deeply nested loop.
In any event, the lack of registers on the x86 is really the main problem anyway.
As for profiling, it may be a lost art, but we do quite a bit of it here. It's helped us speed things up tremendously.
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What'll Intel's code name for that series be?
.007 micron process.
I can see it now:
Intel just announced its new Bond, Chip Bond series of processors using the
The Chip Bond processor line will start with Goldeneye at 150 GHz, giving you a great deal of Room, With a View to expanding up to 300GHz by next September. They will simultaneously release their new low-end processor, the Goldfinger, which will be targeted at the budget conscious market. The latest addition to the Xeon series, Octopussy, will have 8 MB of full-speed cache...
Can't wait to see the commercials.
In post-9/11 America, the CIA interrogates YOU!
Well, a lot of embedded writers use profilers, though even in that arena there seems to be somewhat of a drop-off.
GCC still has profiling support, and last time I looked there were some options in MSVC++ (though that was a couple versions ago...)
Another good one is:
/* Works good, don't know why */
"It's tough to be bilingual when you get hit in the head."
Talk about mis-moderation! This post is entirely incorrect. Yes, they are talking about transistor size. Currently they are producing chips with an oxide thickness of 2 nm, or 0.002 um, so no, this article would not be news if they were talking about being able to fabricate chips with 0.07 um oxides! Let's pay attention people!
wire of the same length as in a previous chip would be slower in the new chip because of the reduced driver sizes, thinner wires (increased resistance), and the relatively unchanging capacitance. (The capacitance per unit length stays about the same at smaller sizes because of fringing effects.)
Capacitance is still (AFAIK) dominated by the diffusion capacitance of transistor sources/drains connected to the wire. Second contributor, IIRC, was gate capacitance. Both of these go down with feature size.
You might point out that gate and drain area will only go down in one dimension, as I'll be sticking more devices on the bus, but they'll still go down.
Wire resistance similarly isn't a huge contributor AFAIK. In all of the sets of parameters that I've seen, even a long bus wire would have resistance lower than the effective resistance of a MOSFET in saturation mode.
Lastly, while your drivers get smaller, the W/L ratio of the gates remains the same. This means that, should you be inclined to melt down your circuit, you could still pass the same amount of current through a smaller MOSFET.
Now, as far as using intelligence is concerned... Most of the cynicism I've seen expressed both towards coding and towards IC design has been put forward by people who aren't doing coding or IC design (in general; I don't know what your personal qualifications are). The fact remains that while boneheaded code gets written and while boneheaded ICs are most likely designed, there are still companies that do it right. These gain market share, grow complacent, and fall to the next group that does it right, continuing the grand cycle.
My point being that you aren't likely to get order-of-magnitude performance improvements by "using intelligence". The people you're competing against already are.
As far as the ultimate limits of communication on smaller, faster chips are concerned, I doubt this will become a serious problem. Designers will simply focus more on pipelining and asynchronus operation of modules to relax system-wide signal timing constraints.
/* You are not expected to understand this */
This is the single worst comment in the Linux kernel, and I don't even have to look at the rest of them to know it.
Fast code does not have to be messy.
Actually, if I remember the story correctly, that was a comment in the context-switching code, and so has little bearing on the current optimization threads. The writer didn't feel like explaining how context switching worked on the architecture in question.
I admit I know very little about IC's but my understanding is that chips are essentially flat or 2-D. Am I wrong about this?
(assuming I'm not)
What are the problems with building chips in 3-D? Are there heat dissipation issues that make this unrealistic at the current time?
Would this avenue create potentially faster chips (or cubes) by locating different parts closer to the rest?
I guess I'm just thinking how cool it would be to see the next AMD chip shaped like a borg cube sitting inside my box.
-Veldrane
-jcl
Perhaps it would then be better to begin pushing for more efficient programming usage of multi-processors on a single system? From what I know which isn't a lot, we could make more use of parallel processing than most systems currently allow for, or am I completely wrong?
It turns out that, for several reasons, multiprocessors aren't likely to dominate desktops for a few years yet.
The first reason is that systems with multiple _discrete_ processors are more expensive. You need to pay for multiple processor modules, and the motherboard needs a more complex chipset. Joe Average Gamer is better off spending the same amount of money getting a top-of-the-line video card, and a new single processor six months later. Joe Average Non-Gamer doesn't need a multiprocessor for email and office apps.
The second reason is that writing good parallel code is much more difficult than writing good sequential code. Race conditions, interprocess communication, and so forth add plenty of complexity, and compiler tools won't save you - parallelism is designed in at a higher level than compilers deal with.
The third reason is that interprocessor communications bandwidth and memory coherency overhead are *big* problems for multi-processor systems, and they keep on getting bigger as more processors are added. Something like a Starfire, for instance, isn't a large set of processors and memory with a bus tacked on - it's the Bus Network of the Gods with processors and memory tacked on as an afterthought. It has to be, to handle supercomputer communications loads. This means that a lot of the money you spend on a parallel system *won't* be on processing power. If, on the other hand, you're willing to wait another design generation, you can get a comparable processor for a much lower price.
The fourth reason is that while we could indeed integrate many old cores on a new die, we get better performance by doing other things. Adding more cache, for instance, or adding fast, complicated FP units that would have taken too much silicon to add before. Making a bigger translation lookaside buffer (important with a 64-bit address space). Improving branch prediction (a big source of stalls). Adding deeply pipelined load/store units (another big source of stalls). Or adding whatever other performance-enhancing widgets are invented over the next five years. Multple cores are an interesting idea, but at _present_ aren't the most effective way of increasing performance.
All of these factors mean that parallel processing isn't used except by those who really, *really* need it (dual-processor doesn't count).
Now, the caveat.
Once cache performance saturates - and it eventually will - we'll have a lot of silicon to play with when moving to higher linewidths. At the same time, we'll also have to break chips into asynchronus pieces to solve the clock skew problem. We may also be reaching limits to superscaling (scheduling is an NP-complete problem, and approximations reach diminishing returns eventually). At this point, it starts to make sense to put multiple cores in a chip, along with the coherency logic and communications pathways needed.
However, I don't see your desktop machine running a processor like that for 5-15 years, for the reasons mentioned above.
OT, but...
Funny, but if you're going to be off-topic, try not to take your material from someone else without giving credit. I've seen a very similar copy of this about "dark suckers" and how dark travels faster than light.
ObFlame: This is known as plagiarism (also called the "Jon Katz wants to sell a book technique").
It was a joke.
This space left intentionally blank.
So, how fast will Si chips get?
I used to do some work with GaAs in semiconductor lasers, and I have no idea where you get the idea that GaAs is less effort. For semiconductor lasers, it is less effort, but for device fab, the major problem is the lack of a native oxide. What this means in laymans terms is that you can process silicon, let it oxidize(rust), use a photomask to lay down a pattern, etch away the oxide in the pattern, and start over again. There is no such native oxide for GaAs which means that you have to somehow invent a non-native oxide such as GaAlAs which is a real pain in the ass. As for GaAs being faster, this is also only partially true. I can't remember exactly, but I believe that at low frequencys, GaAs has a higher electron mobility, but this effect drops off at higher frequencies to the point where GaAs and Si are similar in speed. The net result is that GaAs has a limited range of applications for which it is acutally better, and it always costs more. It's true that the cost is decreasing rapidly for GaAs, it is decreasing just as fast or faster for Si.
There can be no doubt and no debate that BJT transistors are much better at driving current than CMOS transistors. But the added cost both to manufacturing and to design, the complexity of the circuitry compared to pure CMOS (look at a rail-to-rail BJT inverters and then look at a static CMOS inverter - and if the BJT inverter has resistors then consider temperature stability and how much area these resistors will take), and the issues relating to power dissipation (and thus heat), and finally reliability issues make designing CMOS look very good in comparision.
Having actually worked on the BiCMOS design of the Pentium on the 854.3 process, I'd be really interested in any links to this research work. My experience as a designer was pretty negative, from reliability to signal integrity to power problems (local power droop)... as far as I was concerned Intel made a great decision when it switched from BiCMOS on the P54CS to pure CMOS on the P55C.
I think most people misunderstand what's going on here. The story is about the SiO2 insulator thickness. This oxide sits under the gate of the transistor which is used to control the flow between the source and drain. This is 0.07um OXIDE THICKNESS, which is NOT the same as the gate length. The gate length is the usual parameter quoted when referring to a process (i.e. 0.25um, 0.18um, etc).
.25, .18 m is the feature size. the gate/channel length is lambda which is half of this. Please, for your own sake, understand the topic at hand before posting.
Usually, it helps to understand the topic you're discussing. I grew a 700 angstrom (.07 m) oxide last week on my PFET wafers. If you were correct (which you're not) this article would be over fifteen years late in the coming. Also "wash and deposit" are not terms used in industry. We use "develope, etch and diffusion" since you forgot a step, too. The size which is referred to by
Ummm... .07 micron. That means in 5 more years Ultra Sparc IV can debut real late at .07 micron running low clock speeds!
Seriously tho, they need to figure out a better way to make cpu's soon. They can only keep messing around with silicon for so long before we hit a bottleneck. And that would be very, VERY, bad for my Quake framrates.
If you're talking about a previous poster (some months back I think), then you're right. However, that poster also plagiarised. I tracked down the initial source but couldn't find the actual name of the source, so "Source: unknown (but existent)" probably wouldn't be too useful.
Actually, the scientifically proven limit of silicon technology is much smaller than this. I remember a couple months ago, someone proved that the minimum thickness of the insulator was 4 atoms. Of course, mass-producing on that scale would require lasers with such a short wavelength that the energy delivered by that high-frequency beam would wreak all kinds of havoc on the chip, so a manufacturing process that small is only possible under extremely limited conditions, which will not likely be overcome any time before the next major breakthrough in computing technology.
Personally, I'm more interested in the molecular scale quantum computing technology. I believe it was Los Alamos that put 3 quantum transistors on a single proline molecule. You know, proline, one of them amino acids. We might even be able to grow our computer chips from a DNA or RNA template in the distant future. That is something that could go a lot farther.
WARNING: there is a trojan on your
Bipolar designs are great, but getting the lithium dose right is a royal pain. Ever try to convince a bipolar chip that it needs its meds?
It's a small world and it smells funny; I'd buy another if it wasn't for the money; Take back what I paid (SoM)
If this is the gate width, what the heck do the doping levels look like? My training is a little (ok, lot) outdated, but they must be only using a handful of impurities per gate. How about dopant mobility at these levels. I would love to know how they are doing the masking and implantation. Neat stuff.
I have heard that below a process of ~.14 one has a problem with a resistance breakdown. Anyone know how these problems are being remedied?
Speeding never killed anyone. Stopping did.
Some Asian company, name I forgot, announced shipping 512Kb RAM chips at 0.12 micron this year. :-(
Thats only about two generations from the "limit"
Roughly the inverse square of the width change, .07 will be
although there are other factors such as voltage.
So if 0.18 is doing 1 GHz, then
6 GHz.