Pencam - much smaller, lighter, and easier
on
Kite Aerial Photography
·
· Score: 4, Interesting
I attach a small, cheap, 1.3MP digital Pencam to my R/C planes for aerial shots. Aiptek makes a 1.3MP "pencam" that weighs about 50grams. (without batteries) that works pretty well. The pictures out of the CMOS sensor and the cheap lens aren't as nice as conventional photographs - even from disposable cameras - but you can take a lot of them, and the really bad ones don't cost anything to develop.
The camera is ~US$60-70 at Walmart and Circuit City.
Actually, the editor that you are chiding has a valid point in my opinion. Leakage is headed towards the point where it won't matter how many transistors you can pattern in lithography ino a given area if they leak so much that you can never be sure when they turned off. FinFET's are one technique to enable transistors to actually work as MOS transistors when the industry heads below 50nm process technologies. Without some solution to the leakage problem, Moore's law is in some danger of becoming invalid.
The TEM picture is not too clear, but try this site at Intel for a picture. Search down for the term "finFET" near the bottom.
The SEM picture shows the "fins" being in the source and drain region. I always though the "fin" was the gate as shown in the TEM cross-sectional picture. In this picture, what I thought was the "fin" is kinda hard to see. It's above the thing labelled "si island" in figure 26. Perhaps I'm mistaken. Or perhaps the authors of the document at Intel are mistaken.
The "fin" in finFET is not an acronym. It refers to the shape of the device which resembles the fin of a fish or tailfin of an airplane. You need to look at the device cross-sectioned to see where the name comes from.
One probable reason that the industry is looking closely at finFETs is that the original invention of them at UC Berkeley was not patented originally. Note that there are several patents on fabrication methods for manufacturing them now, but the original invention was not patented.
From an article about the early work on this at Berkeley:
Hu said the FinFET prototype was successfully fabricated last July and appeared to perform well. He said no patent had been taken out on the device. "We made the decision not to patent," Hu said. "We want the widest possible usage. We hope this becomes a mainstream transistor structure in the future."
As a VLSI design engineer working in the industry, I can see that finFET's are becoming a serious technology contender in the 50nm process timeframe.
I noticed a significant drop in call volume within several times of saying the "magic phrase". It definitely does work. I watched the number of calls per night drop from 3-4 down to 1-2. They didn't completely go away, but the difference was noticeable.
Fortunately I live in Colorado where we recently passed a law against any unsolicited calls at all once you place your name on a no-call list run by a Colorado non-profit. It was free and easy and the only people who call me now are politicians and charities.
My wife and I always go to the movies (and dinner dates, and theaters, and concerts) with our cellphone set to vibrate simply so that if things go horribly wrong at home with the baby sitter and our children, we can be reached. Just because my wife and I are having a date out doesn't mean that everyone back at home (children and/or babysitter) need to have a miserable evening.
Only once did the babysitter call during the theater. I got up, walked out, and took the call and told the babysitter that my daughter's teddy bear was probably under the couch (it was) and waited until they found it. Without a cell phone our daughter who was two and half would have been miserable. And there's no reason when we are a mere cellphone call away to help.
Honestly, if they blocked our cellphone we wouldn't go there. We'd find something else to do on our rare dates and wait until it came out on video. I'm sensitive to the noise issue during public performances, and I would no more take a call during a movie than I would talk loudly to my wife during the same movie. But we need the phone if only to have the peace of mind that everything is ok at home.
The review at Anandtech (http://www.anandtech.com) uses the latest demo from Unreal Tournament 2003 as one of the core benchmarks. It didn't make much of a difference. In the review, the Parhelia scored about as well as Radeon 8500LE.
In the review Anand attributed it to three things. Quoting from Anand's review:
1) Low GPU Clock (220MHz vs. 250 - 300MHz)
2) Sub optimized drivers
3) A lack of serious occlusion culling technology
Whatever the reasons, the Parhelia didn't score well on one of more anticipated and graphically intensive games that will be released in the near future.
If you follow the link you posted you'll notice that resellerratings.com are no longer there. They were a great service to the Internet community and it's a shame that they are gone.
ResellerRatings.com stopped working recently and it looks like there's no longer any access to their database. It's a real shame because this was a great way to gather data on resellers.
For components, I usually shop Newegg.com or Mwave.com and I buy everything at the same time from either one.
But for memory I recommend Crucial.Com. Memory is one thing that you definitely do not want to buy the cheapest that you can find. Cheap memory is can be flaky memory which then leads to a flaky system. At Crucial prices are usually competitive, the service is very good, shipping is nearly always free, and they are very good on handling returns. Like others, I recommend getting all of the other components together from one vendor, but I would buy the memory separately from Crucial.Com unless the price difference is substantial.
As far as whether or not you save money by building your own... about the best aspect of it is that you can leave out the parts that you don't want. If you are running Linux, you don't have to buy a copy of Windows that you will never use. If you have pretty good speakers already, you don't have to buy another pair that will end up on the shelf gathering dust. Dell let's you customize a little, but building it yourself you can customize it completely and save money by not buying what you won't use/don't need.
(and no, I don't work for Crucial... I just like the place)
Power consumption on chips will most likely continue to rise into the future. Process technology shinks (025um -> 0.18um, for example) have long been used to lower power, but transistors have now gotten so small that they are essentially conducting even while they are supposed to be turned off. In addition, everyone tries to cram more transistors onto a chip to improve performance which uses more power. Finally, pipelining improves performance by allowing higher frequencies, but faster clocks use more power. The end result is that chips will continue to get hotter into the future. Patrick Gelsinger from Intel gave a keynote at the ISSCC 2001 conference showing graphs in this rise in power and said that power will be one of the biggest challenges faces designers going forward.
In mobile apps, the majority of consumers pay little attention to battery life beyond looking for a minimum theshold (an hour and a half). In addition, since there is no defined way to test for power that is enforced between manufacturers, there is no easy way to compare battery life using the manufacturer's specifications. Performance sells CPUs in the mobile space - not power savings. At least not yet.
As long as performance continues to be the key selling point of CPU's, the power situation isn't likely to get better - and, at best, can only hope to stand constant. Performance and power savings are generally opposed in CPU designs similar to the way fuel economy and high-performance engines generally are opposites. Even if power becomes the key selling point, the future still doesn't look bright for power dissipation on chips. Current leakage in supposedly "off" transistors will continue to rise in future process technologies.
I would have voted for Storm of Swords as well except that it's always been my impression that the Nebula favors science fiction and the Hugo favors fantasy. Not that this is always true but it seems like this break between the two awards is the norm.
As far as the fact that the main characters have a shorter existence than those red-shirted Star Trek guys, I personally find it refreshing. Having said this, a friend were talking over lunch last week and were trying to figure out if anyone will still be left alive when Winter is supposed to arrive in later volumes.
The first thing that I noticed when I looked at the link is that there's an fairly easily visible image of some kind of hooded figure that looks eerily like "death" (in the classical image) along the right hand side of the picture.
If you look at the "head of the horse's", travel down the right side of the "neck", there's a gap where you can see through the image. Am I the only one who sees an image like the masked villian in Scream (the movie)? It was the first thing that I noticed and I was suprised that no one else mentioned it since it seems very clear to me.
I just throught that I'd mention it since I didn't see anyone else saying this and I start to question whether I'm just seeing inkblot images where other people are seeing butterflies.:)
Otherwise the pictures are truly amazing. What an amazing universe we live in, and how little can we see from our little section of it.
If you use the (admittedly stretched) analogy of the internet as a broadcast medium, then you should be able to look at how current laws governing radio and television broadcasts are handled.
What are the laws like covering broadcasts and how are they enforced? With the right medium (satellite, etc.) you should be able to reach many parts of the world where various broadcasts are deemed illegal. For example, pornography and some countries in the Middle East. How are these handled? I would have thought political broadcasts by one country might be deemed illegal in other countries with differing views.
Hmm... there are a couple of typos. I really should preview things better before I post them.
One that sticks out at me is my comment about discussing gate dielectrics in "another post in this thread". This is due to my having reposted this from my original post over at the BBS at Anandtech.Com. If you are looking for the comment on dielectrics, go to the Highly Technical BBS at forums.anandtech.com and search for "dielectric".
There is a mroe technical article over at EETimes.Com here:
http://www.eetimes.com/story/OEG20011126S0031
The following is based on my prior research into SOI and the EETimes.Com article that I cited, and not on any knowledge of what Intel is actually planning on doing. I have not read the IEDM presentation and have no inside knowledge of the details of Intel's SOI plans. I am not speaking for Intel (despite working there) and I may be wrong on the details. My purpose in posting is to give some details on the background of SOI.
There are three parts to this: this uses fully depleted SOI vs. the current partially depleted insulators, this uses a high-K dielectric (zirconium oxide, according to the EETimes) vs. traditional dielectrics, and this uses thicker source and drain terminals to offset the increased resistance from fully depleted SOI.
Conventional silicon wafers use essentially a large, somewhat thick circular chunk of silicon as the starting platform that transistors are then created on top of. SOI is "Silicon On Insulator" and refers to a type of silicon wafer in which there is a somewhat thick chunk of silicon that forms the bulk of the wafer, on top of this there's a relatively thin insulator (referred to as the bulk oxide) and then on top of this a new layer of silicon is deposited (referred to as an epitaxial silicon layer, or epi layer). The transistors are created on top of this epi layer.
The only physical difference between fully depleted and partially depleted SOI is the thickness of the layers. Partially depleted uses a relatively thick layer of insulator followed by a relatively thick silicon layer. Fully depleted uses much thinner layers. The names come from the fact that the depletion region on fully depleted SOI reaches down all the way to the bulk oxide whereas in the partially depleted SOI, the depletion region ends and there is still some non-depleted silicon between the bottom of the transistor and the bulk oxide. To explain exactly what depleted silicon is would take some diagrams and some time. Suffice to say (and this is not debated in the industry, it is a fact): fully depeted SOI is better than partially depleted.
So why do people use partially depleted? It's a matter of complexity. Fully depleted SOI requires extremely tight manufacturing margins. You need to have very precise thicknesses to achieve the advantages that fully depleted can offer over partially, and this precision results in much higher cost. People (like myself) say that SOI is expensive, but this is in reference to partially depleted SOI which is the most common in use nowadays, fully depleted is quite a bit more expensive than even this. There is also concern that wafer manufacturers may have problems supplying high-quality, fully-depleted, completely planar (flat) SOI wafers in high volumes.
Switching to SOI reduces a form of leakage called subthreshold current (or Ioff) that occurs when a transistor is supposedly turned off. Fully depleted reduces this leakage even more than partially depleted. If you think of transistor current as being water that flows out of a water faucet depending on a signal (in this case the tap/handle of the faucet), subthreshold leakage is the equivalent of a leaky faucet that runs even when it's supposed to be off. It also has other benefits (it's faster, packing density is improved, etc.).
The other primary form of leakage is something called gate oxide leakage that is current that tunnels through the increasingly thin region that separates the gate from the channel of the transistor. If we go back to the faucet metaphor, it would be like the faucet sucking water out of your hand while your hand is on the tap.:) Gate leakage is a function of oxide thickness, and I discuss this in another post of mine in this thread. The thicker the oxide, the less likely it is that electrons can tunnel through the gate. But if you increase the oxide thickness while leaving everything else the same, you lose performance since the capacitance of the gate is reduced. So what you want is a way to maintain a value of gate capacitance while increasing the thickness of the gate. The easiest way to do this is to switch to a material in the gate that has a higher dielectric constant. So, the high-K dielectric tackles the other part of leakage by allowing higher thicknesses of dielectric while maintaining a given level of performance.
The third "new thing" offsets a disadvantage of fully depleted SOI - higher channel resistance. By increasing the thickness of the contacts of the source and drain you can reduce the resistance going into the transistor and can partially offset the increased channel resistance.
Intel's Pentium 4 which is currently running at 1.8GHz is fabricated on a 0.18 micron 6-layer aluminium process too. Neither AMD nor Intel are selling 2GHz processors currently and no one is using 0.12 micron. There's an industry shift towards 0.13 micron, but it's not well established and currently only some Pentium III CPUs are using it.
Intrinsic claims to be able to synthesize quad-phase dynamic logic, and this is interesting, but this is something that is present in CPU's already, and it certainly has it's downsides. If you have no latches, verification is very hard. Timing compution is difficult since many tools are optimized for 1-clock static, not 4-phase dynamic. Also, dynamic will be harder to implement in lower process levels due to the higher leakage current (Ioff). This will force up the size of keepers on the interstitial nodes, which will offset the speed advantage while dramatically increasing power.
Slashdot Mirror
I attach a small, cheap, 1.3MP digital Pencam to my R/C planes for aerial shots. Aiptek makes a 1.3MP "pencam" that weighs about 50grams. (without batteries) that works pretty well. The pictures out of the CMOS sensor and the cheap lens aren't as nice as conventional photographs - even from disposable cameras - but you can take a lot of them, and the really bad ones don't cost anything to develop.
The camera is ~US$60-70 at Walmart and Circuit City.
The official Pencam web site
And a picture taken with my pencam from my R/C plane
From the article:
"The Hondas and the giant wagon, however, went without chutes, gaining speeds of up to 140 mph depending upon angle of attack. "
140mph? Is that right? It seems awfully slow to me. I would have thought that the terminal velocity of a car would have been much higher than that.
Actually, the editor that you are chiding has a valid point in my opinion. Leakage is headed towards the point where it won't matter how many transistors you can pattern in lithography ino a given area if they leak so much that you can never be sure when they turned off. FinFET's are one technique to enable transistors to actually work as MOS transistors when the industry heads below 50nm process technologies. Without some solution to the leakage problem, Moore's law is in some danger of becoming invalid.
The TEM picture is not too clear, but try this site at Intel for a picture. Search down for the term "finFET" near the bottom.
The SEM picture shows the "fins" being in the source and drain region. I always though the "fin" was the gate as shown in the TEM cross-sectional picture. In this picture, what I thought was the "fin" is kinda hard to see. It's above the thing labelled "si island" in figure 26. Perhaps I'm mistaken. Or perhaps the authors of the document at Intel are mistaken.
The "fin" in finFET is not an acronym. It refers to the shape of the device which resembles the fin of a fish or tailfin of an airplane. You need to look at the device cross-sectioned to see where the name comes from.
Definition from the Semiconductor Glossary.
One probable reason that the industry is looking closely at finFETs is that the original invention of them at UC Berkeley was not patented originally. Note that there are several patents on fabrication methods for manufacturing them now, but the original invention was not patented.
From an article about the early work on this at Berkeley:
Hu said the FinFET prototype was successfully fabricated last July and appeared to perform well. He said no patent had been taken out on the device. "We made the decision not to patent," Hu said. "We want the widest possible usage. We hope this becomes a mainstream transistor structure in the future."
As a VLSI design engineer working in the industry, I can see that finFET's are becoming a serious technology contender in the 50nm process timeframe.
As a follow-up to my own post, here's the website of the Colorado No-Call list:
http://www.coloradonocall.com/index.cfm
It's free and it was completely effectively in stopping unsolicited phone calls (except, as noted, political calls and charities).
I noticed a significant drop in call volume within several times of saying the "magic phrase". It definitely does work. I watched the number of calls per night drop from 3-4 down to 1-2. They didn't completely go away, but the difference was noticeable.
Fortunately I live in Colorado where we recently passed a law against any unsolicited calls at all once you place your name on a no-call list run by a Colorado non-profit. It was free and easy and the only people who call me now are politicians and charities.
Still, the "magic phrase" works.
My wife and I always go to the movies (and dinner dates, and theaters, and concerts) with our cellphone set to vibrate simply so that if things go horribly wrong at home with the baby sitter and our children, we can be reached. Just because my wife and I are having a date out doesn't mean that everyone back at home (children and/or babysitter) need to have a miserable evening.
Only once did the babysitter call during the theater. I got up, walked out, and took the call and told the babysitter that my daughter's teddy bear was probably under the couch (it was) and waited until they found it. Without a cell phone our daughter who was two and half would have been miserable. And there's no reason when we are a mere cellphone call away to help.
Honestly, if they blocked our cellphone we wouldn't go there. We'd find something else to do on our rare dates and wait until it came out on video. I'm sensitive to the noise issue during public performances, and I would no more take a call during a movie than I would talk loudly to my wife during the same movie. But we need the phone if only to have the peace of mind that everything is ok at home.
The review at Anandtech (http://www.anandtech.com) uses the latest demo from Unreal Tournament 2003 as one of the core benchmarks. It didn't make much of a difference. In the review, the Parhelia scored about as well as Radeon 8500LE.
In the review Anand attributed it to three things. Quoting from Anand's review:
1) Low GPU Clock (220MHz vs. 250 - 300MHz)
2) Sub optimized drivers
3) A lack of serious occlusion culling technology
Whatever the reasons, the Parhelia didn't score well on one of more anticipated and graphically intensive games that will be released in the near future.
I had the site with the page that they were shutting down in my browser's cache. You are correct. I apologize for the confusion.
I clicked on the link and it must have been in my cache. Everyone who posted that I was wrong is correct. My apologies for the confusion.
If you follow the link you posted you'll notice that resellerratings.com are no longer there. They were a great service to the Internet community and it's a shame that they are gone.
ResellerRatings.com stopped working recently and it looks like there's no longer any access to their database. It's a real shame because this was a great way to gather data on resellers.
For components, I usually shop Newegg.com or Mwave.com and I buy everything at the same time from either one.
But for memory I recommend Crucial.Com. Memory is one thing that you definitely do not want to buy the cheapest that you can find. Cheap memory is can be flaky memory which then leads to a flaky system. At Crucial prices are usually competitive, the service is very good, shipping is nearly always free, and they are very good on handling returns. Like others, I recommend getting all of the other components together from one vendor, but I would buy the memory separately from Crucial.Com unless the price difference is substantial.
As far as whether or not you save money by building your own... about the best aspect of it is that you can leave out the parts that you don't want. If you are running Linux, you don't have to buy a copy of Windows that you will never use. If you have pretty good speakers already, you don't have to buy another pair that will end up on the shelf gathering dust. Dell let's you customize a little, but building it yourself you can customize it completely and save money by not buying what you won't use/don't need.
(and no, I don't work for Crucial... I just like the place)
Power consumption on chips will most likely continue to rise into the future. Process technology shinks (025um -> 0.18um, for example) have long been used to lower power, but transistors have now gotten so small that they are essentially conducting even while they are supposed to be turned off. In addition, everyone tries to cram more transistors onto a chip to improve performance which uses more power. Finally, pipelining improves performance by allowing higher frequencies, but faster clocks use more power. The end result is that chips will continue to get hotter into the future. Patrick Gelsinger from Intel gave a keynote at the ISSCC 2001 conference showing graphs in this rise in power and said that power will be one of the biggest challenges faces designers going forward.
In mobile apps, the majority of consumers pay little attention to battery life beyond looking for a minimum theshold (an hour and a half). In addition, since there is no defined way to test for power that is enforced between manufacturers, there is no easy way to compare battery life using the manufacturer's specifications. Performance sells CPUs in the mobile space - not power savings. At least not yet.
As long as performance continues to be the key selling point of CPU's, the power situation isn't likely to get better - and, at best, can only hope to stand constant. Performance and power savings are generally opposed in CPU designs similar to the way fuel economy and high-performance engines generally are opposites. Even if power becomes the key selling point, the future still doesn't look bright for power dissipation on chips. Current leakage in supposedly "off" transistors will continue to rise in future process technologies.
* Not speaking for Intel Corp. *
I would have voted for Storm of Swords as well except that it's always been my impression that the Nebula favors science fiction and the Hugo favors fantasy. Not that this is always true but it seems like this break between the two awards is the norm.
As far as the fact that the main characters have a shorter existence than those red-shirted Star Trek guys, I personally find it refreshing. Having said this, a friend were talking over lunch last week and were trying to figure out if anyone will still be left alive when Winter is supposed to arrive in later volumes.
Hmmm... now that I've posted, I notice that someone else did mention it. Oh well, at least I know that I'm not the only one who sees it. :)
The first thing that I noticed when I looked at the link is that there's an fairly easily visible image of some kind of hooded figure that looks eerily like "death" (in the classical image) along the right hand side of the picture.
:)
If you look at the "head of the horse's", travel down the right side of the "neck", there's a gap where you can see through the image. Am I the only one who sees an image like the masked villian in Scream (the movie)? It was the first thing that I noticed and I was suprised that no one else mentioned it since it seems very clear to me.
I just throught that I'd mention it since I didn't see anyone else saying this and I start to question whether I'm just seeing inkblot images where other people are seeing butterflies.
Otherwise the pictures are truly amazing. What an amazing universe we live in, and how little can we see from our little section of it.
If you use the (admittedly stretched) analogy of the internet as a broadcast medium, then you should be able to look at how current laws governing radio and television broadcasts are handled.
What are the laws like covering broadcasts and how are they enforced? With the right medium (satellite, etc.) you should be able to reach many parts of the world where various broadcasts are deemed illegal. For example, pornography and some countries in the Middle East. How are these handled? I would have thought political broadcasts by one country might be deemed illegal in other countries with differing views.
How exactly is it a troll? What did I say that's incorrect? Please elaborate on what you think is mistaken and we can discuss it.
Hmm... there are a couple of typos. I really should preview things better before I post them.
One that sticks out at me is my comment about discussing gate dielectrics in "another post in this thread". This is due to my having reposted this from my original post over at the BBS at Anandtech.Com. If you are looking for the comment on dielectrics, go to the Highly Technical BBS at forums.anandtech.com and search for "dielectric".
There is a mroe technical article over at EETimes.Com here:
:) Gate leakage is a function of oxide thickness, and I discuss this in another post of mine in this thread. The thicker the oxide, the less likely it is that electrons can tunnel through the gate. But if you increase the oxide thickness while leaving everything else the same, you lose performance since the capacitance of the gate is reduced. So what you want is a way to maintain a value of gate capacitance while increasing the thickness of the gate. The easiest way to do this is to switch to a material in the gate that has a higher dielectric constant. So, the high-K dielectric tackles the other part of leakage by allowing higher thicknesses of dielectric while maintaining a given level of performance.
http://www.eetimes.com/story/OEG20011126S0031
The following is based on my prior research into SOI and the EETimes.Com article that I cited, and not on any knowledge of what Intel is actually planning on doing. I have not read the IEDM presentation and have no inside knowledge of the details of Intel's SOI plans. I am not speaking for Intel (despite working there) and I may be wrong on the details. My purpose in posting is to give some details on the background of SOI.
There are three parts to this: this uses fully depleted SOI vs. the current partially depleted insulators, this uses a high-K dielectric (zirconium oxide, according to the EETimes) vs. traditional dielectrics, and this uses thicker source and drain terminals to offset the increased resistance from fully depleted SOI.
Conventional silicon wafers use essentially a large, somewhat thick circular chunk of silicon as the starting platform that transistors are then created on top of. SOI is "Silicon On Insulator" and refers to a type of silicon wafer in which there is a somewhat thick chunk of silicon that forms the bulk of the wafer, on top of this there's a relatively thin insulator (referred to as the bulk oxide) and then on top of this a new layer of silicon is deposited (referred to as an epitaxial silicon layer, or epi layer). The transistors are created on top of this epi layer.
The only physical difference between fully depleted and partially depleted SOI is the thickness of the layers. Partially depleted uses a relatively thick layer of insulator followed by a relatively thick silicon layer. Fully depleted uses much thinner layers. The names come from the fact that the depletion region on fully depleted SOI reaches down all the way to the bulk oxide whereas in the partially depleted SOI, the depletion region ends and there is still some non-depleted silicon between the bottom of the transistor and the bulk oxide. To explain exactly what depleted silicon is would take some diagrams and some time. Suffice to say (and this is not debated in the industry, it is a fact): fully depeted SOI is better than partially depleted.
So why do people use partially depleted? It's a matter of complexity. Fully depleted SOI requires extremely tight manufacturing margins. You need to have very precise thicknesses to achieve the advantages that fully depleted can offer over partially, and this precision results in much higher cost. People (like myself) say that SOI is expensive, but this is in reference to partially depleted SOI which is the most common in use nowadays, fully depleted is quite a bit more expensive than even this. There is also concern that wafer manufacturers may have problems supplying high-quality, fully-depleted, completely planar (flat) SOI wafers in high volumes.
Switching to SOI reduces a form of leakage called subthreshold current (or Ioff) that occurs when a transistor is supposedly turned off. Fully depleted reduces this leakage even more than partially depleted. If you think of transistor current as being water that flows out of a water faucet depending on a signal (in this case the tap/handle of the faucet), subthreshold leakage is the equivalent of a leaky faucet that runs even when it's supposed to be off. It also has other benefits (it's faster, packing density is improved, etc.).
The other primary form of leakage is something called gate oxide leakage that is current that tunnels through the increasingly thin region that separates the gate from the channel of the transistor. If we go back to the faucet metaphor, it would be like the faucet sucking water out of your hand while your hand is on the tap.
The third "new thing" offsets a disadvantage of fully depleted SOI - higher channel resistance. By increasing the thickness of the contacts of the source and drain you can reduce the resistance going into the transistor and can partially offset the increased channel resistance.
You are right. This post describes the Itanium, not the PA-8800. It's kinda scary that it got mod'd up to a 5.
Intel's Pentium 4 which is currently running at 1.8GHz is fabricated on a 0.18 micron 6-layer aluminium process too. Neither AMD nor Intel are selling 2GHz processors currently and no one is using 0.12 micron. There's an industry shift towards 0.13 micron, but it's not well established and currently only some Pentium III CPUs are using it. Intrinsic claims to be able to synthesize quad-phase dynamic logic, and this is interesting, but this is something that is present in CPU's already, and it certainly has it's downsides. If you have no latches, verification is very hard. Timing compution is difficult since many tools are optimized for 1-clock static, not 4-phase dynamic. Also, dynamic will be harder to implement in lower process levels due to the higher leakage current (Ioff). This will force up the size of keepers on the interstitial nodes, which will offset the speed advantage while dramatically increasing power.