The reason why computer chips have kept to Moore's Law is that the whole area of research has constantly attracted huge funding from very big companies
I don't think this is entirely true. Especially in Europe the solar cell industry is significantly subsided by the government. Germany alone has probably around 20 solar cell manufacturers, many of which are not operating on an economical basis.
that developing these technologies would have gone against the interests of some very major players: the oil and coal companies
Curiously enough several oil companies have been investing into solar cells since before the green hype started.
During the last decade there was only a very mediocre decline. Scaling up solar cell production in the last few years actually brought prices up again due to silicon shortage.
However the price of solar cells is expected to decline sharper during the next years
1) Many new solar grade silicon fabs are coming up, hopefully driving down the cost of solar grade silicon
2) Thin film solar cells which can be produced at lower cost (but at the expense of efficiency and reliability) are gaining more and more market share and are improving.
As many other people pointed out, the scaling of solar cells is inherently different from that of microelectronics. In integrated circuits you are actually able to reduce the size and increase the density of your circuits.
For solar cells the material consumption per watt is pretty simple:
Vol [cmÂ/W] = thickness [cm] / efficiency [W/cmÂ]
Efficiencies for mass products are currently stuck somewhere between 15% and 20%. There are limited ways to work around this (concentrator cells, multijunction). This figure of merit is not expected to scale.
Reducing the material thickness is obviously the only option. Since the material thickness depends on physical properties (direct/indirect band gap) there are hard limits as well.
It boils down to the fact there there is no technical scaling model or road map to improve solar cell similar to integrated circuits. The main lever is simply in manufacturing intelligence and cost.
Personally I think the most interesting ramifications of this are that we will see (short lived) phase where companies can survive based on superior manufacturing technologies. Over time these differentiators will becomes less significant and cost is only defined by environmental factors such as cost of energy, raw material and labour.
This is why the solar cell industry will not be a pleasant place to work in in ten years, as interesting as it looks now. Outsourcing and consolidation will be swift and brutal. Even today companies are looking into places such as Malaysia, Mexico, Mongolia (!).
Oh, really? I must have misunderstood the article.
>All jokes about smart toilet paper aside, this is big-league stuff
No, this is not big league stuff, this looks more like a Science toy. Nice idea and good for a publication, but no immediate real world application.
Unless they manage to thin down the insulator to a thickness of 250 nm (thats 1/1000 of a typical paper sheet) or less it is pretty useless due to insufficient channel modulation - even for thin film transistors.
OLEDS have made surprising progress recently in term of efficiency. They are especially interesting because they offer completely new form factors like 'lighting tiles'.
CBRAM, PRAM and RRAM are generally based on two terminal devices that are written at a high current and read at a low current.
For all of those there are two ways of arranging them into an array: A passive matrix with diodes or an active matrix with transistors. The former is slightly simpler to make but suffers from scalability issues.
The reason why HP made a passive matrix is simply because they don't own a fab capable of producing dense memory. This is nothing but a research toy. Their prototype does not even include diodes, meaning that it won't work in a full matrix.
It is important to realize that HPs "memristor" is actually a fairly conventional oxide based RRAM device. Many other groups have reported similar devices in the past.
I doubt it. Maybe they mentioned the Pentium as an example to explain an in-order superscalar architecture as opposed to more modern CPUS.
-There is a lot of overheard in the P54C to execute complex CISC operations that are completely useless for graphic acceleration.
-The P54C was manufactured in a 0.6micron BiCMOS process. Shrinking this to 0.045micron CMOS (more than 100x smaller!) would require a serious redesign up to the RTL level. Circuit design had evolve with process technology.
How many large distributions still support sucurity updates for old kernel versions? Sure, the lonely hacker at home can mod and update old kernel versions ad nauseam, but for a company that is no real option.
SAMs deposited from vapour phase used as dielectrics for organic thin films transistors. Not exactly a novel idea, but possibly some iterative progress.
Still, this can never be used to manufacture anything resembling a modern CPU. RFID tags, as mentioned in the article, may be an application.
The research focus of the group suggests that "SANDS" is an organic dielectric for thin film transitors - with either organic or transparent inorganic semiconductor channel. This kinds of transistors are still very much in research stage and have only found very limited commercial applications. The most probably use would be in displays.
We are talking about devices which are >3 orders of magnitude large and slower than those used in modern CPUs. The press release alludes to "intel CPUs", which could not be further off and is grossly misleading. This is a completely different application.
This press release is a again a prime example of how popular science has been dumbed down until it avails to nothing. There is not a single word about the true technical nature of this "discovery" - for anybody who is versed in the field this press release is utterly useless. I believe it is important to communicate science to the general public, but I really fail to understand why this automatically entails the total absence of an accurate technical description?
One could probably argue that insiders may have heard about "SAND" (Stupid Acronym for Nonexistent Device?) through usual technical channels. But this is not the case here as the scientific impact seems to be rather limited.
How about just having a third party review that compares products according to certain customer applications without using words and phrases suchs as "war", "rallying against", "Rather than", "legitimate comparison", "spin doctors opt for bunkum and hogwash","sensational headlines", "don't have any substance", "blatant lack of integrity displayed"?
Oh, did I just quote the entire article? Surprising how little substance remains after cutting out the polemic.
Nothing against a well founded unbiased comparison of different products. But your article already starts off stating that it is purposefully against one of the options. Why should this be any better than the Microsoft press department gibberish?
There is really no similary to FeRAM. FeRAM is based on capacitors with switchable polarization. The "mimristor" (also known as resistive memory element) is a resistor with switchable resistivity.
I liked your homepage, you seem to be really interested in Nanotechnology and the likes. You need to understand more of the underlying science though, that will help you to understand how things fall into place. It is too easy to get fascinated with a bunch of hype technologies and popular science attached to it. All of it comes with a long history of development that is required to understand the merits and how things work. Most of this is hidden to the casual passer by. I guess university is going to do that for you.
If you really want to build a semiconductor/"Nanotechnology" device at home I would suggest to look into solar cells. There is a type of cuprous oxide/electrolyte cell that can be very easily manufactured. (eg here http://scitoys.com/scitoys/scitoys/echem/echem2.html) Also look for graetzel cells.
And you're right about AMD being way behind getting to the 45-nm process; but you're missing that it costs them even more, because they have to buy it from IBM, or rent space in TSMC or Chartered's contract fabs. Intel has no middle-man to pay.
Luckily it is not that trivial. AMD does not "buy" the technology, they are part of a consortium that shares the development cost. There surely is a hefty overhead involved, but in the end it is cheaper for them than going alone.
Btw, the same is true for IBM. IBM is a very minor player in the semiconductor business. Without the technology alliance(s) they could not survive.
Re:One potential future advantage of AMD's technol
on
Is AMD Dead Yet?
·
· Score: 1
There are other ways to improve cache density without SOI. I am sure Intel has something up their sleeve. On the other hand the die area is already dominated by cache. Using higher density memory may enable cost saving, but introducing more cache does only lead to relatively mediocre performance benefit - if any extra cost is involved that may quickly become a losing game.
ZRAM is actually more similar to DRAM than to SRAM. Additional logic overhead for refreshing is required.
Intel published work on FinFET ZRAM, which can be implemented without SOI, a while ago.
Re:Don't think so.
on
Is AMD Dead Yet?
·
· Score: 5, Interesting
In the past, AMD had an architecture advantage over Intel and Intel had a slight process technology advantage.
Now the situation is different:
-Since the introduction of the Core 2 Duo Intel has the better architecture (minus memory controller though). -Intel is smoking the rest of the industry with 45nm high-k/metal gate in therms of process technology. Compared to what has been published by IBM about their hkmg technology IBM/AMD has a long way to go to catch up.
And let me say this: Intels technology is extremely clever, they did one fundamentally different thing (gate first) against conventional wisdom which took them onto an entirely different path. Getting the fundamental flaws out of this approach enables a flurry of additional optimizations that IBM/AMD will not be able to apply in their technology. (full metal gates, not using any exotic materials for the gate)
The only disadvantage for intel could be higher cost/lower yield associated with the hkmg process. However they have the benefit of scale (in therms of volume) on their side. In addition they went go through the painful hkmg transition two years earlier and hence things will be much easier for them at the 32nm node. IBM/AMD will be in even more trouble than they are now. I predict that Intel will have a very quick 32nm ramp around the time IBM/AMD managed to get their 45nm hkmg process to manufacturable yield.
Slashdot Mirror
The reason why computer chips have kept to Moore's Law is that the whole area of research has constantly attracted huge funding from very big companies
I don't think this is entirely true. Especially in Europe the solar cell industry is significantly subsided by the government. Germany alone has probably around 20 solar cell manufacturers, many of which are not operating on an economical basis.
that developing these technologies would have gone against the interests of some very major players: the oil and coal companies
Curiously enough several oil companies have been investing into solar cells since before the green hype started.
Lets have a look at actual data:
http://solarbuzz.com/
During the last decade there was only a very mediocre decline. Scaling up solar cell production in the last few years actually brought prices up again due to silicon shortage.
However the price of solar cells is expected to decline sharper during the next years
1) Many new solar grade silicon fabs are coming up, hopefully driving down the cost of solar grade silicon
2) Thin film solar cells which can be produced at lower cost (but at the expense of efficiency and reliability) are gaining more and more market share and are improving.
As many other people pointed out, the scaling of solar cells is inherently different from that of microelectronics. In integrated circuits you are actually able to reduce the size and increase the density of your circuits.
For solar cells the material consumption per watt is pretty simple:
Vol [cmÂ/W] = thickness [cm] / efficiency [W/cmÂ]
Efficiencies for mass products are currently stuck somewhere between 15% and 20%. There are limited ways to work around this (concentrator cells, multijunction). This figure of merit is not expected to scale.
Reducing the material thickness is obviously the only option. Since the material thickness depends on physical properties (direct/indirect band gap) there are hard limits as well.
It boils down to the fact there there is no technical scaling model or road map to improve solar cell similar to integrated circuits. The main lever is simply in manufacturing intelligence and cost.
Personally I think the most interesting ramifications of this are that we will see (short lived) phase where companies can survive based on superior manufacturing technologies. Over time these differentiators will becomes less significant and cost is only defined by environmental factors such as cost of energy, raw material and labour.
This is why the solar cell industry will not be a pleasant place to work in in ten years, as interesting as it looks now. Outsourcing and consolidation will be swift and brutal. Even today companies are looking into places such as Malaysia, Mexico, Mongolia (!).
>convertible submarine
http://blog.cardomain.com/blog/2008/03/geneva-motor-sh.html
You are really not trying hard enough.
>the waterproof sundial
Useful in a fountain or pool
>the tricycle with four-wheel drive
Tough one... The fourth wheel is above the front wheel so the trike can flip upside down without losing traction?
>as the insulator for the FET.
Oh, really? I must have misunderstood the article.
>All jokes about smart toilet paper aside, this is big-league stuff
No, this is not big league stuff, this looks more like a Science toy. Nice idea and good for a publication, but no immediate real world application.
Unless they manage to thin down the insulator to a thickness of 250 nm (thats 1/1000 of a typical paper sheet) or less it is pretty useless due to insufficient channel modulation - even for thin film transistors.
The first transistors on paper have been published in 2005:
http://www.freepatentsonline.com/7387872.html
There is also a paper by the same authors, which I can not find right now.
OLEDS have made surprising progress recently in term of efficiency. They are especially interesting because they offer completely new form factors like 'lighting tiles'.
http://www.eetimes.com/showArticle.jhtml?articleID=209100587
Sorry, but that is bullshit.
CBRAM, PRAM and RRAM are generally based on two terminal devices that are written at a high current and read at a low current.
For all of those there are two ways of arranging them into an array: A passive matrix with diodes or an active matrix with transistors. The former is slightly simpler to make but suffers from scalability issues.
The reason why HP made a passive matrix is simply because they don't own a fab capable of producing dense memory. This is nothing but a research toy. Their prototype does not even include diodes, meaning that it won't work in a full matrix.
It is important to realize that HPs "memristor" is actually a fairly conventional oxide based RRAM device. Many other groups have reported similar devices in the past.
I doubt it. Maybe they mentioned the Pentium as an example to explain an in-order superscalar architecture as opposed to more modern CPUS.
-There is a lot of overheard in the P54C to execute complex CISC operations that are completely useless for graphic acceleration.
-The P54C was manufactured in a 0.6micron BiCMOS process. Shrinking this to 0.045micron CMOS (more than 100x smaller!) would require a serious redesign up to the RTL level. Circuit design had evolve with process technology.
-a lot more...
How many large distributions still support sucurity updates for old kernel versions? Sure, the lonely hacker at home can mod and update old kernel versions ad nauseam, but for a company that is no real option.
Ok, I should have RTFA instead of the press release.
http://pubs.acs.org/cgi-bin/abstract.cgi/jacsat/2008/130/i24/abs/ja801309g.html
SAMs deposited from vapour phase used as dielectrics for organic thin films transistors. Not exactly a novel idea, but possibly some iterative progress.
Still, this can never be used to manufacture anything resembling a modern CPU. RFID tags, as mentioned in the article, may be an application.
Some googling revealed the groups publication history. I still fail to spot the relevant publication.
http://chemgroups.northwestern.edu/marks/pubs.html
The research focus of the group suggests that "SANDS" is an organic dielectric for thin film transitors - with either organic or transparent inorganic semiconductor channel. This kinds of transistors are still very much in research stage and have only found very limited commercial applications. The most probably use would be in displays.
We are talking about devices which are >3 orders of magnitude large and slower than those used in modern CPUs. The press release alludes to "intel CPUs", which could not be further off and is grossly misleading. This is a completely different application.
This press release is a again a prime example of how popular science has been dumbed down until it avails to nothing. There is not a single word about the true technical nature of this "discovery" - for anybody who is versed in the field this press release is utterly useless. I believe it is important to communicate science to the general public, but I really fail to understand why this automatically entails the total absence of an accurate technical description?
One could probably argue that insiders may have heard about "SAND" (Stupid Acronym for Nonexistent Device?) through usual technical channels. But this is not the case here as the scientific impact seems to be rather limited.
How about just having a third party review that compares products according to certain customer applications without using words and phrases suchs as "war", "rallying against", "Rather than", "legitimate comparison", "spin doctors opt for bunkum and hogwash" ,"sensational headlines", "don't have any substance", "blatant lack of integrity displayed"?
Oh, did I just quote the entire article? Surprising how little substance remains after cutting out the polemic.
Nothing against a well founded unbiased comparison of different products. But your article already starts off stating that it is purposefully against one of the options. Why should this be any better than the Microsoft press department gibberish?
looks pretty darn similar to FeRAM.
There is really no similary to FeRAM. FeRAM is based on capacitors with switchable polarization. The "mimristor" (also known as resistive memory element) is a resistor with switchable resistivity.
Maybe there is some truth to it. Does anybody remember where the 9/11 terrorists came from? (hint: many of them studied at a technical university)
I liked your homepage, you seem to be really interested in Nanotechnology and the likes. You need to understand more of the underlying science though, that will help you to understand how things fall into place. It is too easy to get fascinated with a bunch of hype technologies and popular science attached to it. All of it comes with a long history of development that is required to understand the merits and how things work. Most of this is hidden to the casual passer by. I guess university is going to do that for you.
If you really want to build a semiconductor/"Nanotechnology" device at home I would suggest to look into solar cells. There is a type of cuprous oxide/electrolyte cell that can be very easily manufactured. (eg here http://scitoys.com/scitoys/scitoys/echem/echem2.html) Also look for graetzel cells.
And you're right about AMD being way behind getting to the 45-nm process; but you're missing that it costs them even more, because they have to buy it from IBM, or rent space in TSMC or Chartered's contract fabs. Intel has no middle-man to pay.
Luckily it is not that trivial. AMD does not "buy" the technology, they are part of a consortium that shares the development cost. There surely is a hefty overhead involved, but in the end it is cheaper for them than going alone.
Btw, the same is true for IBM. IBM is a very minor player in the semiconductor business. Without the technology alliance(s) they could not survive.
There are other ways to improve cache density without SOI. I am sure Intel has something up their sleeve. On the other hand the die area is already dominated by cache. Using higher density memory may enable cost saving, but introducing more cache does only lead to relatively mediocre performance benefit - if any extra cost is involved that may quickly become a losing game.
ZRAM is actually more similar to DRAM than to SRAM. Additional logic overhead for refreshing is required.
Intel published work on FinFET ZRAM, which can be implemented without SOI, a while ago.
In the past, AMD had an architecture advantage over Intel and Intel had a slight process technology advantage.
Now the situation is different:
-Since the introduction of the Core 2 Duo Intel has the better architecture (minus memory controller though).
-Intel is smoking the rest of the industry with 45nm high-k/metal gate in therms of process technology. Compared to what has been published by IBM about their hkmg technology IBM/AMD has a long way to go to catch up.
And let me say this: Intels technology is extremely clever, they did one fundamentally different thing (gate first) against conventional wisdom which took them onto an entirely different path. Getting the fundamental flaws out of this approach enables a flurry of additional optimizations that IBM/AMD will not be able to apply in their technology. (full metal gates, not using any exotic materials for the gate)
The only disadvantage for intel could be higher cost/lower yield associated with the hkmg process. However they have the benefit of scale (in therms of volume) on their side. In addition they went go through the painful hkmg transition two years earlier and hence things will be much easier for them at the 32nm node. IBM/AMD will be in even more trouble than they are now. I predict that Intel will have a very quick 32nm ramp around the time IBM/AMD managed to get their 45nm hkmg process to manufacturable yield.
470nm is huge. In the semiconductor industry structures within single digit nm range are routinely surveyed using SEM and TEM.
And the alternative would be...?
Hehe, great one. Gotta remember that.
True, I should use the preview button more often.