Well, I do, but i've had the point drummed into me by my father (a Hollander btw, as am I by birth) who had it drummed into him by his uncle (not a Hollander;) ). It's not a matter of caring, it's of ignorance that needs to be corrected. Referring to the the Netherlands as Holland, and hence leading to things like hearing "We're here at Assen in Holland" is akin to saying "We're here at {Cardiff, Glasgow, Belfast,etc} in England". It's incorrect and it's ignorant and there are some outside of Holland who would be insulted by it.
In other countries they think of the Netherlands as Holland.
They didn't though, the dutch created the misconception. Particularly from 60s on, when international tourism started to grow, and tourists would arrive in Rotterdam or Schiphol and be welcomed to Holland by posters, etc. The dutch themselves obviously know the difference but never bothered explaining it to the foreigners, and hence allowed the usage to gradually become corrupted.
Only people from the province seem to experience this fetishistic need to say they live somewhere else.
It's a matter of misrepresentation. It's incorrect to use the term "Holland" to refer to the state, especially if talking to a non-dutch person who doesn't know the difference.
Its rather pathetic, really.
Ignorance can be more pathetic.
Oh, and Philips moved to Amsterdam years ago...
Their pride-and-joy, and huge, Philips Research R&D facilities are in Eindhoven. Head office is now in Amsterdam (but who cares where the PHBs are located;) ).
FWIW, The country is not called Holland, it is called the Netherlands. Holland refers to a region within the Netherlands (the region of the provinces of North and South Holland). The electronics giant Philips is not based in Holland (they're in Eindhoven, Noord Brabant), the dutch TT grand prix race at Assen is not held in Holland (despite what Mr P5NIS and friend commentating on the BBC might think: "We're here at Assen in Holland"), Assen is in Drenthe, etc. The dutch beer Grolsch is not from Holland, it's brewed in Enschede, Overijssel and Groenlo in Gelderland. Heineken is made in North Brabant as well as in (south) Holland. etc.
No it doesn't. In civil proceedings judgement is made on balance of probability based on the arguments made. Ie, whichever side's arguments are the more probable as being correct are the side in whose favour judgement will be made. Innocent until proven guilty beyond reasonable doubt applies to the defendants in criminal proceedings only (at least in jurisdictions which descend or drew from british common law at least, eg what is now the US, Canada, Ireland, Australia, much of Africa, etc.., damn brits have ruled most of the world at one stage or the other.)
"its use of" as in "the article's use of", "the article" being the outstanding noun. "its" is correct. "is it use of" makes no sense. Then again, my english grammar sucks;)
I mean, NFS has issues with security (relying on numeric user id's sent by the client is a nightmare).
Try NFSv4, ownerships are described by name, not by ID. (And RPSSEC implementation is mandatory, yay!).
Locking is problematic. Different versions have severe compatibility issues.
I think both of those views are possibly based on dated experience, ie from NFSv2 days. Locking just works out of the box on a modern Linux distro or decent Unix these days, and all serious vendors/implementors of NFSv3 and now 4 have gone through the NFS bake-offs/connectathons. Though, yes there are still a few crap NFS implementations out there.
Perhaps it's just the Brit jargon, but I just barely can understand what they're talking about in the article
What kind of Brit jargon exactly? I didn't read any in the article, unless it's use of "big" words such as indignant, municipality, unfathomable,volition and so on, confused you.
Look at MotoGP motorcycle racing....Not just once a lap, but sometimes in successive corners.
Amen. Actual real racing. Especially now that Rossi is on Yamaha and hence the other "mere" mortals on HRC now have a machine advantage. It's just fascinating to watch the Honda's use the honda-lane on the straights and then watch Rossi claw it back on the twisty backs, sometimes lap after lap. At the last MotoGP for a couple of laps in a row Rossi was listed in second place, even though he spent most of each lap in the lead, because Tamada on the RCV211 could out accel Rossi from the last corner to the finish line. Rossi actually got him on the brakes at the first corner on occassion - Tamada led for only a few hundred metres on that lap!
Less then 500lbs with 220HP
Far less. The HRC RCV211s are 145Kg (~320lbs), excluding fuel, which is limited to 24l (22l next year) and hence no more than 20kg max at beginning of race. Even with the rider onboard, who'll be somewhere between 50 and 70kg (eg Barros;) ) max you're looking at no more than 145+20+70 = 235kg or 517lbs.
And 220HP is what the RCV211V was allegedly *at least* making when it was first introduced several years ago. I'm guessing it's at least 230HP by now, if not more. The lap times have fallen dramatically each year for the 4 strokes, where the 2 strokes before them had reached an effective plateau, which most likely is due to the manufacturers developing the new 4 strokes further and further and getting more HP.
Bikes also have that kind of deceleration & acceleration.
Acceleration: yes, indeed the bikes possibly may even out accelerate F1 cars. Deceleration, no way - F1 cars pull huge G's on the brakes, bikes just do not have the grip to do the same and even if they did, they still wouldnt be able to without flipping unless they were designed to have much lower CoG (which'd be pointless given the lack of grip).
however, on that same note, slashdot is still unusable on my PDA. why? because it only fits on 640x480 or bigger.
Try the dillo browser, does a pretty good on PDA sized screens. Presuming you have linux and X on your PDA of course (eg familiar and GPE on ipaq class machines).
I was under the impression that SMP (symmetric multi-processing) refers to a design where each processor has equivalent access to system resources
Right, it implies a general symmetry in processing capacity.
this isn't true in a NUMA design.
It is, sort of. At least if you restrict your definition of IO to RAM. In general, in a NUMA machine, for every CPU the proportional difference in locality of RAM will be the same, ie it is still symmetric. If you want to define IO generally, then even the 2-way Opterons are not SMP - as i stated earlier the Tyan 2885 has PCI and AGP IO both going via CPU0, CPU1 only has HT links to CPU0 and RAM.
What will be interesting is 8-way. That conceivably could look something like:
Ie, if each CPU had 3 external HT links (as i gather the Opteron 8xx's have) one conceivably could have a system where a set of core CPUs (ie 1,2,5 and 6) had fully-meshed links, forming a 'crossbar' with a set of 'peripheral' CPUs (0,3,4,7) then having the spare links for IO beside their 2 links to other CPUs. And each 8xx K8 (I gather) additionally has 2 HT links to 2 on-die dual-channel memory controllers. See:
That architecture is pretty much what DEC were touting as the state of the art in the very late 90s and began selling at the beginning of this century in their Wildfire product (the big GSxxx massively SMP machines, 32 CPUs+). Except Wildfire was/is based on the EV6 bus, also point-to-point (which Athlon uses), but requiring dedicated EV6 hub controllers to stitch the CPUs and various IO together. HyperTransport is the logical generalised progression of that, which perhaps isnt really surprising considering AMD managed to acquire quite a few former Alpha engineers who really did not care to go work for paranoia-as-mantra intel when DEC got their rather odd settlement from intel for patent violations, including Rich Witek, lead architect for the initial Alpha AXP CPUs, who is now an AMD fellow.
So, is it SMP? I dont know, if you want to really pick nits, then I guess it doesnt quite meet the classical definition, but it is the logical progression of SMP, and the resources while not being completely symmetric in terms of locality are still uniform in terms of accessibility, which i think at least meets the spirit of the definition.
I have NEVER upgraded to a faster CPU by swapping it out and keeping the same motherboard
I've done this a few times actually. Years ago I upgraded my machine from a P133 to a K6 200 and only recently I upgraded it again with a K6-II 450MHz someone had spare. And the other day I upgraded my current desktop's 600MHz Athlon to an 800MHz which again someone didnt want.
Self-correction: Apparently it might be just _one_ memory controller per die, which may or may not itself be dual channel (I gather from other posts). Also, obviously each CPU potentially has additional HT links to connect to things like PCI bus controllers, AGP controllers, etc. (the basic block diagramme for the Tyan S2885 dual K8 board shows the AMD-8151 AGP controller and the AMD-8131 PCI-X controller wired to CPU0).
apparently because of reduced bus conflicts with their individual memory spaces.
Ah but with multi-core chips they can transduce their flux capacitors with the onboard trans-mogrification controllers. Seriously "reduced bus conflicts with their memory space", what does that mean?? That's gibberish.
P4, presumably, like the P6 GTL+ host bus is a shared bus (like most buses are). Only CPU can use the bus at any one time. If the bus does x GB/s, that's only to one CPU at any given time - effectively it is shared. Further, P6 and P4 do not have integrated memory controllers, and must access RAM via the (shared) GTL+ bus, if it is not in cache. Eg, a 4 CPU machine looks like:
P = CPU MC = Memory Controller (part of the "northbridge" chip, also provides PCI host bus controller, etc.)
P P P P
| | | | --------- GTL+ bus
|
MC--RAM
Also GTL+ is limited to 4 CPUs and one controller. To get 8 CPUs some controller vendors have invented a GTL+ 'bridge' to stitch 2 GTL+ buses together, but that just makes things worse really from a scaleability POV I'd imagine.
The K8 on the other hand uses a point-to-point (PtP) serialish, packet based transport, HyperTransport to interconnect CPUs and has onboard memory controller(s) (connected internally via HyperTransport links). A 4 CPU K8 machine looks like:
Each of the lines out of a K is a HyperTransport link. Each MC is integrated into the die itself. (you'll have to imagine interconnects and right-hand top/bottom MC's lining up with the K symbols, cause/.'s filter is chomping whitespace in some strange way on me).
Each CPU has 4 HT links, two to other CPUs, two to its (integrated on die) memory controller. For dual CPU setups, each CPU needs only link to another CPU obviously. Indeed the difference between 2xx, 4xx and 8xx AMD Opteron CPUs is the number of HyperTransport links. Indeed in large multi-CPU (ie 8+) SMP setups one need not attach a memory controller to each CPU, one might choose to have a central "cross-bar" of fully-meshed K8s who then connect to peripheral K8s which have memory controllers and hence RAM. Tis all down to the board designers I guess. And a bit of a fun computer science problem too in terms of designing optimal 'networks' of interconnected nodes with the best compromise of maximum node to node distance for lowest number of required interconnects.
The K8 is actually a ccNUMA (cache coherent, Non-Uniform Memory Architecture) machine, in SMP configurations. Ie, different memory is at different distances to different CPUs, or to put it another way, some memory is local, other memory is distant, some memory may be more distant than other memory. Eg, for the top-left CPU to access RAM on it's "local" MC is obviously potentially far quicker, in terms of latency, than to access "distant" RAM on another node, and to access memory on an adjacent K8's memory controller will have lower latency than to access memory allocated in the bottom-right CPUs RAM. A good OS aware of the issues can try ensure to keep processes on the CPUs to which that processes memory is "local" and hence maximise performance, but it's quite a juggling act (Linux has some NUMA support).
What AMD will do for multi-core we dont know. For certain the individual cores will be connected by HyperTransport. Most likely AMD will give each core their own dedicated memory controller, which would simply make a multi-core SMP be exact same in terms of architecture as the current dual K8 architecture (ie 2xx opteron), and hence no different in terms of bandwidth contention than for existing SMP Opterons.
It will make large SMP machines a lot easier to build though. Eg
Arent BT one of the largest telco's in the world? They merged with some US telco a good few years ago didnt they? MCI or somesuch, i cant remember.
And have bought various other smaller telco's around the world. Eg, British Telecom are the only other telco providing local-loop in Ireland other than the former state-owned monopoly, Errorcon^WEircom, by virtue of having bought Esat (former irish telco, now owned by BT obviously. Called EsatBT - but no doubt name will change fully over to BT in time).
If your computer has frozen to the point where the keyboard lights won't respond then it's likely to be a hardware failure not windows.
Utter baloney. It can easily be a driver problem. Eg, interrupt handler that gets wedged or inefficient drivers that like to disable interrupts for critical paths.
Well, surely there must be some network benchmarking programme you can try your theory out with? Eg, even just ttcp.
take what i'm saying with a grain of salt and at least acknoledge it
I acknowledge that you might possibly see differences in performance. However, those differences would undoubtadly be due to differences either in the ASICs or else some details of your motherboard(s) (eg dual-bus, etc.). Eg, try replacing a motherboard with a _good_ built-in PCI network ASIC with a low-end PCI network card.
If you happen to know why this is, then let me know
There is no reason why. Whatever you're seeing, if you are seeing it at all, is *not* due to built-in aspect. If you're seeing differences it most likely because your motherboard's built-in NICs are low-end (and they'd be just as low-end if they were on a PCI card and in a slot) or perhaps bad drivers for those NICs.
But, again, an ASIC on a PCI bus is an ASIC on a PCI bus regardless of whether it's soldered right onto the PCI bus traces on a motherboard, or on a card in a PCI slot. Makes 0 difference. Whatever you're seeing is due to some other factor. So try remove this superstitious idea from your head and figure out the _real_ common denominator to the performance issue you see (if you even really see one).
Do you have an quantitative basis for this? I'm sorry, but this sounds to me like the placebo effect "you can see programs opening faster", "Games also seem to respond a little better", etc. Most telling: "but i could be imagining that a little more". I'm sorry, but unless all the built-in ASICs are utter crap and you're replacing them with good ones in slots, you're simply imagining things I suspect.
that I have found to be tru at several different lcations.
Describe the computers? There is nothing inherently different about a PCI ASIC soldered to the motherboard and one soldered to a card plugged into a PCI slot. Describe these computers, what motherboards? Maybe they all used crap network ASICs? But those ASICs would be just as crap if attached to a PCI card.
Re:Simple
on
The 3Com Saga
·
· Score: 2, Informative
Typically an onboard chip/network card will use more proccesor and memory resources then a regular add in card
This is absolute bull. Whether a PCI ASIC is built-in to motherboard or on an add-in card makes 0 difference to performance.
Slashdot Mirror
Do you honestly think anyone cares?
;) ). It's not a matter of caring, it's of ignorance that needs to be corrected. Referring to the the Netherlands as Holland, and hence leading to things like hearing "We're here at Assen in Holland" is akin to saying "We're here at {Cardiff, Glasgow, Belfast,etc} in England". It's incorrect and it's ignorant and there are some outside of Holland who would be insulted by it.
;) ).
Well, I do, but i've had the point drummed into me by my father (a Hollander btw, as am I by birth) who had it drummed into him by his uncle (not a Hollander
In other countries they think of the Netherlands as Holland.
They didn't though, the dutch created the misconception. Particularly from 60s on, when international tourism started to grow, and tourists would arrive in Rotterdam or Schiphol and be welcomed to Holland by posters, etc. The dutch themselves obviously know the difference but never bothered explaining it to the foreigners, and hence allowed the usage to gradually become corrupted.
Only people from the province seem to experience this fetishistic need to say they live somewhere else.
It's a matter of misrepresentation. It's incorrect to use the term "Holland" to refer to the state, especially if talking to a non-dutch person who doesn't know the difference.
Its rather pathetic, really.
Ignorance can be more pathetic.
Oh, and Philips moved to Amsterdam years ago...
Their pride-and-joy, and huge, Philips Research R&D facilities are in Eindhoven. Head office is now in Amsterdam (but who cares where the PHBs are located
Oh, and it's le Pays Bas in French and der Niederlanden in german, Ie "the low countries".
You are wrong, the Netherlands is called el Países Bajos in Spanish.
FWIW, The country is not called Holland, it is called the Netherlands. Holland refers to a region within the Netherlands (the region of the provinces of North and South Holland). The electronics giant Philips is not based in Holland (they're in Eindhoven, Noord Brabant), the dutch TT grand prix race at Assen is not held in Holland (despite what Mr P5NIS and friend commentating on the BBC might think: "We're here at Assen in Holland"), Assen is in Drenthe, etc. The dutch beer Grolsch is not from Holland, it's brewed in Enschede, Overijssel and Groenlo in Gelderland. Heineken is made in North Brabant as well as in (south) Holland. etc.
If someone can conduct a man in the middle attack, they obviously also have control of DNS replies. So the URL will be the same.
No it doesn't. In civil proceedings judgement is made on balance of probability based on the arguments made. Ie, whichever side's arguments are the more probable as being correct are the side in whose favour judgement will be made. Innocent until proven guilty beyond reasonable doubt applies to the defendants in criminal proceedings only (at least in jurisdictions which descend or drew from british common law at least, eg what is now the US, Canada, Ireland, Australia, much of Africa, etc.., damn brits have ruled most of the world at one stage or the other.)
"its use of" as in "the article's use of", "the article" being the outstanding noun. "its" is correct. "is it use of" makes no sense. Then again, my english grammar sucks ;)
And to self-correct my self-correction, that should of course have read "That should of course have read", not "That should have course ...".
self-correction: That should have course have read "unless its use of ...", not "it's".
I mean, NFS has issues with security (relying on numeric user id's sent by the client is a nightmare).
Try NFSv4, ownerships are described by name, not by ID. (And RPSSEC implementation is mandatory, yay!).
Locking is problematic. Different versions have severe compatibility issues.
I think both of those views are possibly based on dated experience, ie from NFSv2 days. Locking just works out of the box on a modern Linux distro or decent Unix these days, and all serious vendors/implementors of NFSv3 and now 4 have gone through the NFS bake-offs/connectathons. Though, yes there are still a few crap NFS implementations out there.
Perhaps it's just the Brit jargon, but I just barely can understand what they're talking about in the article
What kind of Brit jargon exactly? I didn't read any in the article, unless it's use of "big" words such as indignant, municipality, unfathomable,volition and so on, confused you.
Look at MotoGP motorcycle racing. ...Not just once a lap, but sometimes in successive corners.
;) ) max you're looking at no more than 145+20+70 = 235kg or 517lbs.
Amen. Actual real racing. Especially now that Rossi is on Yamaha and hence the other "mere" mortals on HRC now have a machine advantage. It's just fascinating to watch the Honda's use the honda-lane on the straights and then watch Rossi claw it back on the twisty backs, sometimes lap after lap. At the last MotoGP for a couple of laps in a row Rossi was listed in second place, even though he spent most of each lap in the lead, because Tamada on the RCV211 could out accel Rossi from the last corner to the finish line. Rossi actually got him on the brakes at the first corner on occassion - Tamada led for only a few hundred metres on that lap!
Less then 500lbs with 220HP
Far less. The HRC RCV211s are 145Kg (~320lbs), excluding fuel, which is limited to 24l (22l next year) and hence no more than 20kg max at beginning of race. Even with the rider onboard, who'll be somewhere between 50 and 70kg (eg Barros
And 220HP is what the RCV211V was allegedly *at least* making when it was first introduced several years ago. I'm guessing it's at least 230HP by now, if not more. The lap times have fallen dramatically each year for the 4 strokes, where the 2 strokes before them had reached an effective plateau, which most likely is due to the manufacturers developing the new 4 strokes further and further and getting more HP.
Bikes also have that kind of deceleration & acceleration.
Acceleration: yes, indeed the bikes possibly may even out accelerate F1 cars. Deceleration, no way - F1 cars pull huge G's on the brakes, bikes just do not have the grip to do the same and even if they did, they still wouldnt be able to without flipping unless they were designed to have much lower CoG (which'd be pointless given the lack of grip).
however, on that same note, slashdot is still unusable on my PDA. why? because it only fits on 640x480 or bigger.
Try the dillo browser, does a pretty good on PDA sized screens. Presuming you have linux and X on your PDA of course (eg familiar and GPE on ipaq class machines).
--paulj
Right, it implies a general symmetry in processing capacity.
this isn't true in a NUMA design.
It is, sort of. At least if you restrict your definition of IO to RAM. In general, in a NUMA machine, for every CPU the proportional difference in locality of RAM will be the same, ie it is still symmetric. If you want to define IO generally, then even the 2-way Opterons are not SMP - as i stated earlier the Tyan 2885 has PCI and AGP IO both going via CPU0, CPU1 only has HT links to CPU0 and RAM.
What will be interesting is 8-way. That conceivably could look something like:Ie, if each CPU had 3 external HT links (as i gather the Opteron 8xx's have) one conceivably could have a system where a set of core CPUs (ie 1,2,5 and 6) had fully-meshed links, forming a 'crossbar' with a set of 'peripheral' CPUs (0,3,4,7) then having the spare links for IO beside their 2 links to other CPUs. And each 8xx K8 (I gather) additionally has 2 HT links to 2 on-die dual-channel memory controllers. See:
http://www.xbitlabs.com/images/news/2004-04/opter
That architecture is pretty much what DEC were touting as the state of the art in the very late 90s and began selling at the beginning of this century in their Wildfire product (the big GSxxx massively SMP machines, 32 CPUs+). Except Wildfire was/is based on the EV6 bus, also point-to-point (which Athlon uses), but requiring dedicated EV6 hub controllers to stitch the CPUs and various IO together. HyperTransport is the logical generalised progression of that, which perhaps isnt really surprising considering AMD managed to acquire quite a few former Alpha engineers who really did not care to go work for paranoia-as-mantra intel when DEC got their rather odd settlement from intel for patent violations, including Rich Witek, lead architect for the initial Alpha AXP CPUs, who is now an AMD fellow.
So, is it SMP? I dont know, if you want to really pick nits, then I guess it doesnt quite meet the classical definition, but it is the logical progression of SMP, and the resources while not being completely symmetric in terms of locality are still uniform in terms of accessibility, which i think at least meets the spirit of the definition.
I have NEVER upgraded to a faster CPU by swapping it out and keeping the same motherboard
;)
I've done this a few times actually. Years ago I upgraded my machine from a P133 to a K6 200 and only recently I upgraded it again with a K6-II 450MHz someone had spare. And the other day I upgraded my current desktop's 600MHz Athlon to an 800MHz which again someone didnt want.
So you're obviously talking crap!
Self-correction: Apparently it might be just _one_ memory controller per die, which may or may not itself be dual channel (I gather from other posts). Also, obviously each CPU potentially has additional HT links to connect to things like PCI bus controllers, AGP controllers, etc. (the basic block diagramme for the Tyan S2885 dual K8 board shows the AMD-8151 AGP controller and the AMD-8131 PCI-X controller wired to CPU0).
The third (or fourth) link is internal, to the memory controller(s).
eg, a 2xx opteron has 2 external HT links, 4xx has 4, etc.
Ah but with multi-core chips they can transduce their flux capacitors with the onboard trans-mogrification controllers. Seriously "reduced bus conflicts with their memory space", what does that mean?? That's gibberish.
P4, presumably, like the P6 GTL+ host bus is a shared bus (like most buses are). Only CPU can use the bus at any one time. If the bus does x GB/s, that's only to one CPU at any given time - effectively it is shared. Further, P6 and P4 do not have integrated memory controllers, and must access RAM via the (shared) GTL+ bus, if it is not in cache. Eg, a 4 CPU machine looks like:
Also GTL+ is limited to 4 CPUs and one controller. To get 8 CPUs some controller vendors have invented a GTL+ 'bridge' to stitch 2 GTL+ buses together, but that just makes things worse really from a scaleability POV I'd imagine.
The K8 on the other hand uses a point-to-point (PtP) serialish, packet based transport, HyperTransport to interconnect CPUs and has onboard memory controller(s) (connected internally via HyperTransport links). A 4 CPU K8 machine looks like:
Each of the lines out of a K is a HyperTransport link. Each MC is integrated into the die itself. (you'll have to imagine interconnects and right-hand top/bottom MC's lining up with the K symbols, cause /.'s filter is chomping whitespace in some strange way on me).
Each CPU has 4 HT links, two to other CPUs, two to its (integrated on die) memory controller. For dual CPU setups, each CPU needs only link to another CPU obviously. Indeed the difference between 2xx, 4xx and 8xx AMD Opteron CPUs is the number of HyperTransport links. Indeed in large multi-CPU (ie 8+) SMP setups one need not attach a memory controller to each CPU, one might choose to have a central "cross-bar" of fully-meshed K8s who then connect to peripheral K8s which have memory controllers and hence RAM. Tis all down to the board designers I guess. And a bit of a fun computer science problem too in terms of designing optimal 'networks' of interconnected nodes with the best compromise of maximum node to node distance for lowest number of required interconnects.
The K8 is actually a ccNUMA (cache coherent, Non-Uniform Memory Architecture) machine, in SMP configurations. Ie, different memory is at different distances to different CPUs, or to put it another way, some memory is local, other memory is distant, some memory may be more distant than other memory. Eg, for the top-left CPU to access RAM on it's "local" MC is obviously potentially far quicker, in terms of latency, than to access "distant" RAM on another node, and to access memory on an adjacent K8's memory controller will have lower latency than to access memory allocated in the bottom-right CPUs RAM. A good OS aware of the issues can try ensure to keep processes on the CPUs to which that processes memory is "local" and hence maximise performance, but it's quite a juggling act (Linux has some NUMA support).
What AMD will do for multi-core we dont know. For certain the individual cores will be connected by HyperTransport. Most likely AMD will give each core their own dedicated memory controller, which would simply make a multi-core SMP be exact same in terms of architecture as the current dual K8 architecture (ie 2xx opteron), and hence no different in terms of bandwidth contention than for existing SMP Opterons.
It will make large SMP machines a lot easier to build though. Eg
Arent BT one of the largest telco's in the world? They merged with some US telco a good few years ago didnt they? MCI or somesuch, i cant remember.
And have bought various other smaller telco's around the world. Eg, British Telecom are the only other telco providing local-loop in Ireland other than the former state-owned monopoly, Errorcon^WEircom, by virtue of having bought Esat (former irish telco, now owned by BT obviously. Called EsatBT - but no doubt name will change fully over to BT in time).
If your computer has frozen to the point where the keyboard lights won't respond then it's likely to be a hardware failure not windows.
Utter baloney. It can easily be a driver problem. Eg, interrupt handler that gets wedged or inefficient drivers that like to disable interrupts for critical paths.
i didn't run any scientific study,
Well, surely there must be some network benchmarking programme you can try your theory out with? Eg, even just ttcp.
take what i'm saying with a grain of salt and at least acknoledge it
I acknowledge that you might possibly see differences in performance. However, those differences would undoubtadly be due to differences either in the ASICs or else some details of your motherboard(s) (eg dual-bus, etc.). Eg, try replacing a motherboard with a _good_ built-in PCI network ASIC with a low-end PCI network card.
If you happen to know why this is, then let me know
There is no reason why. Whatever you're seeing, if you are seeing it at all, is *not* due to built-in aspect. If you're seeing differences it most likely because your motherboard's built-in NICs are low-end (and they'd be just as low-end if they were on a PCI card and in a slot) or perhaps bad drivers for those NICs.
But, again, an ASIC on a PCI bus is an ASIC on a PCI bus regardless of whether it's soldered right onto the PCI bus traces on a motherboard, or on a card in a PCI slot. Makes 0 difference. Whatever you're seeing is due to some other factor. So try remove this superstitious idea from your head and figure out the _real_ common denominator to the performance issue you see (if you even really see one).
anyway.. enough.
Do you have an quantitative basis for this? I'm sorry, but this sounds to me like the placebo effect "you can see programs opening faster", "Games also seem to respond a little better", etc. Most telling: "but i could be imagining that a little more". I'm sorry, but unless all the built-in ASICs are utter crap and you're replacing them with good ones in slots, you're simply imagining things I suspect.
that I have found to be tru at several different lcations.
Describe the computers? There is nothing inherently different about a PCI ASIC soldered to the motherboard and one soldered to a card plugged into a PCI slot. Describe these computers, what motherboards? Maybe they all used crap network ASICs? But those ASICs would be just as crap if attached to a PCI card.
Typically an onboard chip/network card will use more proccesor and memory resources then a regular add in card
This is absolute bull. Whether a PCI ASIC is built-in to motherboard or on an add-in card makes 0 difference to performance.
It will yes, and the next version due Real Soon Now(TM). (month or so hopefully).