Also, no DVD with the systems that only have CD-RW. That could be considered a minus but the lus of having a CD-RW outweighs it. Also, you get an extra 64bit PCI slot with AGP-4 but you get one less DIMM slot (3 total). It's all about trade offs. One other thing I noticed is the motherboard PCB and heatsink is much smaller than before.
This is truly funny. The ultimate troll would be someone trolling a story for submission with a redirect link to a real article. Once it gets posted, change the redirect link to goatse.cx. Ta-da! Best troll ever! --
QDR in this case is referring to SRAM. The same kind of RAM that makes up cache chips. One SRAM cell has more transistors than an SDRAM cell, though. But, for embedded applications, this should be pretty speedy. I'm sure you could even use it for a very fast 3D card (250MHz SRAM X 4 = 1GHz). Not bad. --
Well there will be 2 versions on the P4 next year. The second version will have a higher pin count. I wonder if Intel will call this a Pentium4+ just to get out of the agreement.
It's not a P4... it's a P4 plus! No obligation to use Rambus... --
I know you are a troll, but can you "invent" and incompatibility you have ever had with the Athlon? And not with any of the VIA support chips, I'm talking about the processor itself. --
Even the G4+ (enhanced version) won't be able to clock much higher than 1.2GHz unless they lower the process and use SOI. Moving from a 4 stage pipelined design to a 7 stage will boost MHz performance anout 25%. On a present 500MHz part (.22 micron;copper;no-SOI) that alone would result in a 125MHz boost. That's 625MHz top speed. Moving to a.18 micron process we get a slight 20% relative increase topping out the figure to 750MHz. Depending on if Motorola rolls out the G4+ with SOI or not, you can expect a topspeed of 1GHz if Motorola releases the G4+ with copper/.18/SOI. The only way they will attain higher speeds after is to: 1) produce chips on.15-.13 micron or lower, 2) Another redesign of the processor to increase pipeline. The latter is very, very unlikely. The former is inevitable. Although, according to Motorola PowerPC Roadmap(tm), the G5 will have an "extensible architecture" and "new pipeline". This is probably to combat their low MHz yeilds. Time will tell. --
20 stage pipelines are not a good solution. I betthe BPU itself is about half the size of the whole processor. Forget 98%. The BPU better be 99.999% right at prededication of the williamette will have scky performance.
High latency is worse than low MHz when it comes to memory. When you have a high latency design, you need alot of buffer (cache) to overcome the latence and cache costs alot in processor real estate (transistors on the die) or the cost of high capacity SRAM chips. DDR-SDRAM is the logical evolution to desktop memory. It takes modern technology and tweaks it. Maybe it will be around long enough to allow Rambus to catch up.
Rambus of another implimentation (at least 64bit) would be desirable in desktop systems but if you ask me, a serial memory technology for systems that need more than 128MB is absurd. Perhaps high end video cards in the future will use a 64bit Rambus. --
Slashdot Mirror
Things that stayed the same:
Gb Ethernet (expected)
U-DMA ATA/66 (I was surprised by this one)
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I humbly stand corrected, sir!
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MacOS started out as a 16bit OS and later moved to 24bit in System 6.0.X. With the introduction of System 7.0 (1990?) they moved to full 32bit OS.
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This is truly funny. The ultimate troll would be someone trolling a story for submission with a redirect link to a real article. Once it gets posted, change the redirect link to goatse.cx. Ta-da! Best troll ever!
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TiVo is a great name. It's a melding of TV and I/O. Ti(nput)Vo(utput)
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Is it possible? Sure is!
Will it be expensive to implement? Sure will be!
The NB already has a ton of pins on it. I dont think they will want to add 80 or so more to the package. Not enough return in performance)
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I'd move to another state ;)
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QDR in this case is referring to SRAM. The same kind of RAM that makes up cache chips. One SRAM cell has more transistors than an SDRAM cell, though. But, for embedded applications, this should be pretty speedy. I'm sure you could even use it for a very fast 3D card (250MHz SRAM X 4 = 1GHz). Not bad.
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The 760 doesn't support 2 processors. But the 760MP will.
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Well there will be 2 versions on the P4 next year. The second version will have a higher pin count. I wonder if Intel will call this a Pentium4+ just to get out of the agreement.
It's not a P4... it's a P4 plus!
No obligation to use Rambus...
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I know you are a troll, but can you "invent" and incompatibility you have ever had with the Athlon? And not with any of the VIA support chips, I'm talking about the processor itself.
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Even the G4+ (enhanced version) won't be able to clock much higher than 1.2GHz unless they lower the process and use SOI. Moving from a 4 stage pipelined design to a 7 stage will boost MHz performance anout 25%. On a present 500MHz part (.22 micron;copper;no-SOI) that alone would result in a 125MHz boost. That's 625MHz top speed. Moving to a .18 micron process we get a slight 20% relative increase topping out the figure to 750MHz. Depending on if Motorola rolls out the G4+ with SOI or not, you can expect a topspeed of 1GHz if Motorola releases the G4+ with copper/.18/SOI. The only way they will attain higher speeds after is to: 1) produce chips on .15-.13 micron or lower, 2) Another redesign of the processor to increase pipeline. The latter is very, very unlikely. The former is inevitable. Although, according to Motorola PowerPC Roadmap(tm), the G5 will have an "extensible architecture" and "new pipeline". This is probably to combat their low MHz yeilds. Time will tell.
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They sure do only have 8KB of L1 data cache. Check it out: http://www.realworl dtech.com/page.cfm?ArticleID=RWT091000000000
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Remember that the P4 only has 8K of L1 data cache. It's 4 way set associative versus the 2 way of the Athlon but thats got to hurt it in realworld.
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They (LinuxPPC)support SMP now on the G4's, great. But do they support the other features, like firewire, 1Gb ethernet, and Radeon?
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They are huge and geeky looking but I wouldn't mind seeing one on a keychain. I've seen far uglier keychains. I would probably even buy one.
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what we need to find is a way to create gravitons. They would be way more useful than "so-ons:. ;)
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Wario stadium rocks! I love that level.
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There is no Z5, but there is a BMW M5(sport sedan) and X5(SUV).
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They're called books.
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The 512K had a 400K floppy. The Plus had a 800K.
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MacOS up to 8.1 could fit on a floppy. Full GUI but without the frills.
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20 stage pipelines are not a good solution. I betthe BPU itself is about half the size of the whole processor. Forget 98%. The BPU better be 99.999% right at prededication of the williamette will have scky performance.
Check out this article at MDR.
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High latency is worse than low MHz when it comes to memory. When you have a high latency design, you need alot of buffer (cache) to overcome the latence and cache costs alot in processor real estate (transistors on the die) or the cost of high capacity SRAM chips. DDR-SDRAM is the logical evolution to desktop memory. It takes modern technology and tweaks it. Maybe it will be around long enough to allow Rambus to catch up.
Rambus of another implimentation (at least 64bit) would be desirable in desktop systems but if you ask me, a serial memory technology for systems that need more than 128MB is absurd. Perhaps high end video cards in the future will use a 64bit Rambus.
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Forgot the links:
This is a link to the PDF on the 440GP.
And if you don't like PDF, here you go.
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