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What Will Be The Next Generation Of RAM?
Wister285 asks: "I've been hearing a lot about new RAM technologies. Two of the main new forms seem to be RDRAM and DDRAM. Little known to a lot of people currently though is MRAM (magnetic RAM that works more like a hard drive than an electric memory saver, which means that RAM memory is never erased until the computer says so, even through power offs). MRAM seems to be the best form of RAM, but it might not be out for another 1 or 2 years. With these three choices, what is the next generation RAM?"
Does anyone have a clue how flash works? My memory cards for my camera seem to store images indefinetely even without power?
- A.P.
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"Remember when the U.S. had a drug problem, and then we declared a War On Drugs, and now you can't buy drugs anymore?"
- A.P.
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"One World, one Web, one Program" - Microsoft promotional ad
"Remember when the U.S. had a drug problem, and then we declared a War On Drugs, and now you can't buy drugs anymore?"
Intel is struggling with 800MB/s? Sun's latest is at 1.9GB/s and SGI's is around 1.6GB/s. Maybe we should optimize what we've got more - without obsoleting everything we already have like RAM.
Sun hardware goes so far as to allow you to use SIMMs from the SparcStation 20 in the Ultra 2 and even the latest Ultra 60 and Ultra 80 systems!
Obviously, RAM isn't quite the bottleneck as much as Intel and others would lead you to believe.
If you know what you are doing, though, you can get under the hood and get your hands dirty.
And my uncle who runs a donkey farm says the thing really hauls ass.
ducks and runs for cover
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"L'IT c'est moi!"
Any OS worth it's salt will zero out (or otherwise erase) memory it hands to a user to prevent security problems.
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"L'IT c'est moi!"
Cheers,
da Lawn
't used to be LawnMOWER, really...
This also makes creating a hibernation function much, much easier - no more need for a large image file on your harddisk, just let the BIOS know it should *not* erase memory contents after next reboot.
:).
Well, There is actually a function in the BIOS for this, originally intended for 286's to get out of protected mode, because the cpu had too actually be rebooted. I remember playing with it back in my assembly days too see what I could do with it
VK3TST
-- "People aren't stupid. Usually." -- jd
I don't have anything to say on the subject, but am interested in the effect of non-moderated comments on my karma ... does my +1 for registered user count as a +1 moderation? Let's find out, shall we?
The fact that no one understands you doesn't mean you're an artist.
What would happen if a virus was loaded into your memory and you wanted to shutdown and wipe the virus from memory, but your memory was permanent? I don't see that as a good thing at all.
main() { char *c=malloc(4096); int fd=open("virus.bin", O_RDONLY); read(fd, c, 4096);}
OH NO! MY COMPUTER HAS A VIRUS IN MEMORY! AAAH!
Here's a free clue for the clueless: memory is useless unless something refers to it. If you "reboot" a computer without powering down, the RAM isn't cleared. (until the BIOS walks it). Not that it matters, since until something actually jumps to that memory location it never gets executed. What'll happen to your "virus in static ram!"? It'll get overridden by w0rd 2005 when it uses 3-4 gig of system memory, of course. Duh.
Do they actually TEACH you anything in school anymore?
As for the people that think that powering their computer down is safe... Hah! Only if you're sure nobody gets to it for 20 minutes. If you use something more sensitive then a modern motherboard you can get bits off a chip for quite a while. Not that that's practical yet (not portable, so they'd have to get your SIMMS to a lab within 10-15 minutes) don't expect that to last forever.
At least memory isn't as bad as harddrives... when you overwrite memory it basically stays overwritten. Drives have some nasty ghosting of previous data that can be seen at high resolutions.
Besides, any security-concious app rewrites "critical" memory anyway. none of the OSs I've used zero memory before allocating it to a new process.... it's actually quite entertaining to malloc a few meg and read through it. memset(0) is so simple. Learn it. Love it.
--Dan
Mmm, magnetic core. Core wars. Non protected mode. God, those were the days.
Anyone have a good place to send the kids to show them what CORE really was? Most of them have no idea what drum memory was...
--Dan
Um...any efforts at making SRAM more economical would have the side effect of making DRAM more economical. Each SRAM bit is implemented with 4-6 transistors of different types, whereas each DRAM bit is implemented with one n-type MOSFET. That's a huge decrease in size, and is why people put up with awkward timing schemes, address strobes, and pesky refreshes to use DRAM.
I think that it's hard to say what the next RAM will be. I think with the new things that are coming out every day we can't really predict what the next RAM will be. We may look at the current possibilities and say that one looks like the best possibility, or the best technology. However tomorrow any company could put out a new type of RAM that will revolutionize the market.
It's just a matter of looking at the past. Everyone thought that the old add in cards of RAM that you put in your ISA slots to add another meg of RAM (Remember those days? *shudder*) would last forever. The cards would get bigger and the on-board chips would get larger, but nobody could've really said that SIMM's would take over until they came out and suddenly appeared everywhere. I think the next generation of RAM will be the one that nobody sees right now, the one that is in development at the bottom basement of some company, just waiting to be released. Sorta like DUST PUPPY!
Nothing but full speed static RAM. Yum. Using what the rest of us would call L1 cache as main memory. Now THAT had some throughput. I think the research ought to go into making this more economical.
Start Running Better Polls
The ability to erase all your RAM to me is like "starting fresh", similar to rebooting Windows to regain some temporary stability.
No Windows, no problem. Same old story...
It wouldn't be hard to park Linux "nicely" within a few milliseconds, running on power from the capacitors in the power supply just long enough to do this. When the machine is re-powered, Linux can simply reinit devices a la Two Kernel Monte and then pick up where it left off. That and journalling filesystems equals reliability heaven.
Got time? Spend some of it coding or testing
One of the ways you can avoid having a problem like this is to use a log-structured filesystem, which simply writes the data in one long loop around the device, rather than always starting at the beginning of the device. The exact details escape me, but the general idea is correct.
One of the new Linux filesystems, JFFS (journalling flash filesystem) does this, I believe. It was accidentally added to the 2.4 development kernel recently when one of the developers working on a flash driver submitted a patch to Linus, and forgot to remove the JFFS code from his patch... (Please, no flamewar about reiserfs here, there was enough on lkml already).
If anyone recalls, memory used to be magnetic core -- there was a grid of fine wires, with small ring magnets that could flip. Apparently at one point it got quite dense (for it's time).
I wonder if this is where the name "core" came from in respect to *NIX systems.
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I propose PRAM: Paper RAM.
You write information on paper, then stick it inside the computer. Later, when you need to retrieve it, you quickly grab the paper and read it out loud. Fast and cheap solution to everyday computing needs.
This means that RAM needs consistency verified bits like the ones used on hard-drives to tell fsck that things were shut down cleanly.
Someone mentioned that you could have the BIOS auto-detect when you purposely shut things down, or hit the reset button. Well, what happens if the BIOS is buggy and that function doesn't work? It's much better to have a bit that says that something claims that memory is in a valid state for shutdown than something that specially flags that you want to erase memory on startup.
This would cause problems in power failure situations, but that could easily (and cheaply) be solved by having a capacitor bank 'UPS' that could keep the machine running for about 5 seconds or so while the OS went through the motions to put itself in a hibernating state.
Need a Python, C++, Unix, Linux develop
Umm... I think you should read about how OSes actually work before you post again and embarass yourself further.
Programs free up memory all the time and it's cleared by the OS and given to other programs. That's part of the virtual memory subsystem. It's been that way for years and years. The only commonly used OS that didn't do that that I know of in the past 15 years is MS-DOS.
Need a Python, C++, Unix, Linux develop
Well.... When you boot up, your computer starts up from ROM, reads some stuff from disk into memory, runs that etc. So it doesn't really matter what was left in the ram from the previous session, it gets overwritten. And viruses rather infect stuff on your harddrive anyway. Why bother with the memory?
Actually, now that I think of it, if you can count on the ram contents being unchanged after a power cycle, you could just more or less continue where you left off when you turned off the computer. Sort of like normal hibernation, except way faster, because you don't have to save to/restore from disk. Boot up in like a second!
3) You want to get some sleep and the thing is making noise!
About 90% of the time when I boot up it is because the computer was off, not because I rebooted it. If instead I could just hibernate it, that would save me a lot of time.
I think quite often people just leave their computer on all the time because it takes so much time for the thing to boot up again... With MRAM and an appropriate BIOS + OS support, by the time the monitor would finally be fully awake, the system would be up and running.
Actually it will power off completely. Imagine the improvement on notebook battery life if you could just completely turn it of if you wouldn't need it for just a few minutes, without having to wait for ages till it booted up again. (Even save to/restore from disk takes some time)
Scientific American had an article about MRAM a while ago. You appear to be confusing two things.. RDRAM and DDR DRAM are about the way the ram communicates with the rest of the computer, while magnetic ram is a different storage technology on the memory chips themselves, like SRAM, and thus could be used instead of DRAM on both Rambus and regular DDR memory modules.
but think about using an optical interconnect rather than copper wires. No cross-talk, and you could actually send those insanely high-frequency signals the handful of inches between the memory and the CPU with nearly zero latency.
:)
Drool....
Some guy who works across the hall tried using optical interconnects, and got the performance of main memory up to nearly L2-cache levels. Xeon, we don't need no stinkin' Xeon
He wasn't using standard optical stuff. He was using these newfangled solid-state lasers/detectors that aren't available except special made to do research. He determined the performance experimentally (on this really nifty 8-way SMP rig, btw) and saw that the performance of optical interconnects w/out a L2 cache was the same as with L2 cache and standard connections. Both setups also used some aggresive prefetch techniques that are again not available commercially.
Yes, we do.
Look at it this way: you could program the BIOS to always erase the memory on POST, *unless* there was a power faillure (modern ATX supplies can already detect this I believe)
So when you reboot on purpose, everything will be erased, but when power fails, you'll lose nothing!
This also makes creating a hibernation function much, much easier - no more need for a large image file on your harddisk, just let the BIOS know it should *not* erase memory contents after next reboot.
Every expression is true, for a given value of 'true'
In the short term, DDR SDRAM is going to be the man of the day. DDR is an improvement on an existing technology (and quite an ingenious one, at that!) It's easy to work with, well-known and since it works in lockstep with the CPU, it's easy to develop for.
In the long term, however, we will see a transaction to bus-based memory, such as RDRAM. (I personally don't think RDRAM will ever fly; some other incarnation of the same idea will likely spring up, a few years down the road.)
Abstracting your core memory behind a memory bus gives the advantages that your chipset can talk to any kind of memory that supports the bus standard--it could be of any speed, implemented with any technology (for instance, holographic memory.) Its disadvantage--and few people seem to realize this!--is that it's quite slow, compared to SDRAM where the chipset (and the CPU) has direct access to the data lines coming from the RAM.
To compensate for this inadequacy, the makers of Rambus RAM pumped the ram bus's clock rate to some absurd speed--I recall hearing 400MHz mentioned. They should have realized that memory technology isn't sufficiently advanced yet, and left well enough alone.
Thank you for a very interesting and informative post!
I'd say eventually the industry is going to have to give up the idea of expandable RAM, and change the entire architecture of the motherboard so that the CPU and main memory are moved off it, onto a daughter card, like the graphics card is now.
The above, in particular, is extremely interesting. I can see it happening. Indeed, it would fit current trends. We had 30-pin SIMMs forever, but now you're lucky if you keep your memory across two CPU generations. So move all the fast-changing stuff onto a single expansion card, and keep the more stable PCI bus and basic I/O functions on a backplane/mainboard.
I don't think traditional expandable RAM has to go away completely, though. I think the solution would be further extending the NUMA (Non-Uniform Memory Access) concept of cache memory. We've already got very-high-speed L1 and L2 cache. Say this CPU+high-speed-memory card you propose has N ultra-high-speed on-die L1 cache, N*16 super-high-speed off-die L2 cache, and N*(2^10) of very-high-speed, CPU-local RAM. Then have an expandable main memory system of merely high-speed RAM, slower, but expandable and much larger, say, N*(2^12). To fill in some example numbers:
128 KB L1 cache
2 MB L2 cache
128 MB local RAM
512 MB main RAM
That way, you get the best of both worlds.
dragonhawk@iname.microsoft.com
I do not like Microsoft. Remove them from my email address.
Nothing but full speed static RAM. Yum.
The problem is, static RAM (SRAM) fundamentally takes up more space then dynamic RAM (DRAM). SRAM uses six transistors per memory cell (bit) where DRAM uses one little thingy (I forget what it's called) per cell. This means a much larger package. (It also means lower yields, since SRAM is harder to make.) After a while, trace lengths and the speed of light are going to get in your way.
dragonhawk@iname.microsoft.com
I do not like Microsoft. Remove them from my email address.
optical interconnect rather than copper wires. No cross-talk, and you could actually send those insanely high-frequency signals the handful of inches between the memory and the CPU with nearly zero latency.
Hmmmm. While the zero cross-talk is a big benefit, many optical systems actually have higher latencies then their copper counterparts. More bandwidth, but slower response time. This isn't a factor in networks, so fiber is the media of choice, but I imagine it would be inside your computer.
dragonhawk@iname.microsoft.com
I do not like Microsoft. Remove them from my email address.
So given that DRAM is a pain and requires a separate controller to work it, why do we use it? ... performance - for SRAM to change state, one gate has to change and the other gate follows it, so it takes twice as long for a state change. This is all approximate, of course.
I'm confused. They use static RAM as cache memory, right? Because it is faster, right? So how can it also be slower?
dragonhawk@iname.microsoft.com
I do not like Microsoft. Remove them from my email address.
I wonder if this is where the name "core" came from in respect to *NIX systems.
Dead on. Unix geeks often refer to a program loaded into memory as "in core" for this reason.
dragonhawk@iname.microsoft.com
I do not like Microsoft. Remove them from my email address.
Interesting. I'd first point out that, to me at least, what you're proposing sounds a bit more like a gigantic (128 MB) L3 DRAM-cache than traditional NUMA. Of course, I don't know too much about NUMA ...
I don't either, except some basic theory. But basically, good NUMA systems eliminate the duplication of data that traditional PC cache memory systems use. The hardware and OS know that some memory is faster then other memory, and put more frequently used pages in the faster memory.
NUMA is traditionally used in very large microcomputer systems (IBM, Sun, SGI) and clusters. SGI does a lot of this in their high-end number crunchers. Memory on the local processor node is significantly faster to access then memory on another node, even with a 2 GByte/sec backplane.
True, it does require OS-level support for this, and the circuitry is more complex, and blah blah blah, but I think it is worth it for systems where expandability is important (e.g., high-end workstations, servers). I don't see it happening in the home PC market, though. You might as well stick with the "onboard" very-fast-ram then.
And indeed, that would be the biggest problem with this scheme--the latencies.
Well, yes, but without this system, the latencies are even worse. If the data isn't in cache or "onboard" RAM, then it must be on disk. And even 70ns FPM SIMMs are faster then paging to disk!
But still, I think you'd find on such a system that upgrading the main DRAM--like enlarging your virtual memory swap file--wouldn't have the same effect on system performance as upgrading main memory does today.
I'm sure, but I still think the performance and expandability is worthwhile, especially for something like a web server, where some data (e.g., database engine and indexes) are going to be accessed frequently, while other data (random static web content) is less important (and limited by the speed of the pipe in any event).
dragonhawk@iname.microsoft.com
I do not like Microsoft. Remove them from my email address.
There are MANY very interesting problems that have two approaches:
1) nasty heuristics, not guaranteed, but workable,
and
2) brute force, perhaps optimized, but still brute.
and since there are so very many brute force problems, software approaches change in KIND as the hardware scales up.
When I can take the time/space to do a brute force search on a problem, I can guarantee certain things about my answer, which is very valuable computationally.
Translation: software is a gas, it expands to use all the space/time given to it, and it will continue to do so.
If you disagree, well, I guess you wont be using any voice recognition software next year when it hits hard, because that is a clear example of the effect of increased resources.
-- Crutcher --
#include <disclaimer.h>
-- Crutcher --
#include <disclaimer.h>
Well, my (non-coder) idea would be to have two separate areas of memory - volatile and nonvolatile. The VM would be used to execute programs and to store temporary data, while the NVM would be used more for storage and NOT executable code. While this doesn't help that much (virii can simply load from the NVM) it at least ensures that whatever is currently running isn't when you start back up. Of course, now there is no such thing as instant-on as there would be if the entire memory map was NVM.
_______
Scott Jones
Newscast Director / ABC19 WKPT
FC Closer
- Of course this makes the die bigger, but as we get to smaller process technologies this isn't so much of a problem.
Doesn't matter to me. I'd rather have a large processor casing with 128MB+ on-chip, running at full processor speed, than a smaller one with only 256KB-2MB. I wonder why nobody has tried this yet. Especially if AMD were to do something like this, it could blow Intel out of the water on performance. Caveat - current cache memory IIAC* is extremely expensive. But just imagine, 128MB of L1 cache* IIAC - If I Am Correct
_______
Scott Jones
Newscast Director / ABC19 WKPT
FC Closer
chipsets/CPUs need to have crypto on-board, to prevent nasty people from doing a post-mortem debugging session on your RAM.
I find your excessive concern for keeping secrets disturbing. You must be doing something illegal. That's why your computer (and all the other computers purchased with the "secure memory" feature) will, in fact, be equipped with a remote monitoring device which periodically broadcasts a memory dump and can be used to give you a paralysing shock through the keyboard.
We're out to get you, you know. All of us.
---
Despite rumors to the contrary, I am not a turnip.
...are very difficult to make accuratly.
To begin with, may I just point out that most of what has been discussed here about what is, and isn't possable, is actually about what can and can't be manufactured economically.
For example, Ferroelectric DRAM. Basically, a DRAM is a switching capacitor, so stick a ferroelectric in there, and the size of the cappacitor can be made smaller for the same charge storage. The best material to use for this is probably BST (Barium Strontium Titanate). This is difficult to deposit in a standard fab.
It is easy (scientifically) to do. You just etch a flat surface on silicon, and grow a layer by MBE (Molecular Beam Epitaxy). Or deposit a layer by MOCVD (Metal Oxide Chemical Vapour Depositon). Problem is, to get these to work, on silicon, is expensive. It can still be done.
I spend my time surrouned by cutting edge scientific research. Every day I see things that most people would consider impossable, or miraculus. For example, I have seen pure [0] aluminium, as strong as steel. That's not specific (per weight) strength. That's per voulme strength.
Frequency tuneable solid state lasers. Sure. Colour tunable over half the visable spectrum, by rotating a part. Smaller than a drinks can.
A slight digression there, but the point is that to see what the future might hold, is not too tricky for the next the next 3 or so years. After that, you need to look at the skunkworks projects. And then in to the labs of the academics. Because that's where the future can be glimpsed.
[0] A4N standard.
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nothin' says lovin' like an open source penguin.
Generic x86 motherboards are fairly low performance, but are also very low cost (for the most part)... Note also that AGP 2x is essentially DDR (an effective 133MHz), and that there has been 64b/66MHz PCI for quite a long time now, but cheap boards and cheap cards won't take advantage of that (especially since you really need two PCI busses on a system then).
Comparing MHz of a GPU, CPU and RAM module is generally fairly useless... saying that the GeForce2U only runs at 250MHz doesn't really mean a whole lot. A more effective comparison would be the throughput/bandwidth of the chip/memory modules, since that is more immediately relevant.
--
"It's tough to be bilingual when you get hit in the head."
Your disk storage (regardless of whether it happens to be mechanical or otherwise) will still take quite a bit more than 80ns to actually return to the uProc, mainly because of the PCI arbitration, command, disconect, reselection, etc that all has to occur before the actual data gets transferred...
There are solid state drives (HD form factor, basically filled with DRAM) that are rather fast, but one GB will set you back a few thousand $$. That also, of course, isn't preserved across power cycles, but for use as a large cache is rather exciting (see the new pop favorites "Swapping out to disk never felt so good" or "Is My Entire Database is RAM?" and of course the new craze, "Oops, I cached it again").
I gotta get more sleep...
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"It's tough to be bilingual when you get hit in the head."
as long as you don't have a 30GB - 1TB database, that's probably ok (unless you have a machine that has a few hundred GB of RAM... then it's a lot easier).
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"It's tough to be bilingual when you get hit in the head."
DDRII (next-generation DDR) is targeted for cycle times of 2500 ps in large systems and 1250 ps in small ones. In contrast, current DDR runs 2500 in small systems (e.g., video controllers). One hopes that main memory running at 3.2 GB/s for 64-bit memory will stave off disaster for a little while. The truly greedy will just have to go to 128-bit memory.
WRT storage technology, I'm surprised that nobody has mentioned FRAM. Ferroelectric RAM is nonvolatile and much denser than flash; as dimensions sink, it's even denser than regular DRAM. Which is why the big memory houses are furiously searching for a way to reliably manufacture it.
Lacking <sarcasm> tags,
I heard VC (Virtual Channel) RAM is supposed to be the shit. My Asus K7V takes it, but you can't find it anywhere...
-- My neighbors dog has a four inch clit.
'Z' stands for zero. Almost as good as a bit, but half the cost.
Ryan
Most formatting assums block 0 is good. What happens when it goes bad?
I expect the next great thing [tm] in memory will be better interfaces to the cheaper and well known memory that we already have.
There have been people adding things like fast static ram in dram chips for a while but it never took off.
With the widespread use of flash memory, I would love to see a flash package that is smart enough to remap bad blocks once they are detected. Its a real pain that my rio now can't write to block 0 most of the time because its developed a problem.
MRAM has the disadvantage that it can be erased by a strong magnetic field.
Amorphous silicon RAM works by melting the switch element and refreezing it, either so it crystalizes and is very conductive (but still resistive enough that you can remelt it) or becomes glassy and very resistive (but with a "breakover" voltage that lets you drive current into it to remelt it). Selection is by the length of time the write current is on, and thus the amount of heat deposited in the meltable bit.
Magnetic fields won't touch it. EMP strong enough to affect it will fry the whole box anyhow. Ditto heat.
Write time is in single-digit nanoseconds. Read is as fast as ROM.
(But will it ever come to market? Same question for MRAM.)
Bantam Dominique roosters crow a four-note song. Once you've heard it as "Happy BIRTHday" you can't NOT hear it that way
happens to the best of us
Just to nitpick, the Pentium 4 bus is not "double wide double data rate". It is 128 bits wide, and quad-pumped. It does transmit data at 400 MHz. When Intel claims it is a 400 MHz bus, they're just as correct as claiming that AMD claiming a 200 MHz bus, and Rambus claiming an 800 MHz bus.
I'm pretty sure I'm right here. For one thing, the maximum bandwidth of the P4 FSB is 3.2 GB/s, which is 2 "pumps" x 100 MHz x 128-bits. For independent proof of this, note that Intel's top-of-the-line P4 chipset, Tehama, uses dual PC800 RDRAM channels, yielding...3.2 GB/s. If it were quad-pumped, 100 MHz and 128 bits wide as you claim, the FSB bandwidth would be 6.4 GB/s.
For another, there's no way I've ever heard of to actually "quad pump" a clock signal. "Double pumping" works because a clock signal is actually made up of two signals--the so-called "rising edge" when the signal turns on, and the so-called "falling edge" when the signal turns off. In contrast, there's just no natural way to divide a signal into four without using a PLL and a seperate clock generator. How do we know Intel isn't doing that? Well...the question becomes: "seperate" from what? The FSB clock *is* the only clock in a chipset; if they wanted to make it go twice as fast, they would just clock it at 200 MHz.
And no, Kingston's "quad-pumped" SDRAM isn't really quad-pumped either; it's just DDR which is cleverly interleaved to essentially make it twice as wide.
Just a clarification: when referring to RDRAM, RAMBUS decided that PC800 means 800MB/sec, not 800MHz, so it isn't really running that fast.
Just a clarification: you are completely wrong. The various types of RDRAM do in fact refer to their clock speed, not their bandwidth. PC800 does indeed refer to 800MHz; as RDRAM is 16-bits wide per channel, this means PC800 has a theoretical maximum bandwidth of 1.6 GB/s. By way of comparison, PC133 SDRAM is 64-bits wide and 133 MHz, and so it has a max bandwidth of 1.1 GB/s.
So, to reiterate, you're wrong. Now, however, it begins to get confusing. First off, PC800 RDRAM isn't really running at 800 MHz; it's running double data rate--transmitting twice per clock--at 400 MHz. As far as the PC industry goes, it's an acceptable fudge, and not nearly so bad as Intel saying the double-wide double data rate 100 MHz FSB on the P4 is "400 MHz".
Then it gets even more confusing. See, it turns out that PC 700 RDRAM actually runs at 2x356=712 MHz most of the time (good!) whereas PC 600 RDRAM actually runs at 2x266=533 MHz most of the time (bad!). This has to do with the vagaries of timing these cobbled together brands of RDRAM (only marketed because the yields on PC 800 were so awful) to run with 133 MHz FSB chipsets. If run on a 100 MHz FSB chipset--which they never are--they will run at their advertised 600 and 700 MHz rates.
So...in order to get rid of all this confusion but keep the handy-dandy "PC___" designation (and to one-up Rambus in the "my number's higher than yours" game), JEDEC has decided that from now on all its DRAM standards will be numbered based on their maximum bandwidth rather than their clock speed, actual or DDR or otherwise. Thus, the DDR we will see in DDR motherboards in a couple months will either be branded PC1600 (2 x 100 MHz x 64-bits) or PC2100 (2 x 133 MHz x 64-bits).
All done? Not hardly. It turns out that the first generation of PC2100 will have higher latency timings for the various stages of a random access than will PC1600, thus making it slower in certain situations while faster in others. Of course, within a couple months, lower latency PC2100 will be around, which may or may not be designated PC2100A. See how this all helps the customer and makes things easier???
Of course, the DDR for graphics cards is categorized neither by its maximum bandwidth nor its clock rate but rather by its clock period: i.e. 2x166 MHz DDR is called "6ns DDR" when its on a video card (because 1 second / 6 nanoseconds = 166 million); 2x183 is 5.5ns, and the new GeForce2 Ultra's are shipping with incredible 2x250 MHz 4ns DDR SDRAM.
And, of course, any and all of the above DRAM is overclockable to any speeds and latency timings you want; it's just only guaranteed to work at the marketed speed. Oh, and how fast any of this all is depends just as much on your chipset and, in the case of RDRAM, your power consumption settings. (Even if you're plugged into the wall, don't be too profligate with those power settings or the whole thing will overheat!)
And I forgot to mention VC SDRAM, which is available now, and FCSDRAM, eDRAM, DDR-II and DDR-IIe, any of which might/will make the jump to PC main memory in the coming years (at least before MRAM). Isn't it all so simple now?? Good.
Apologies for the uber-post, but man this discussion needed an injection of information.
:)
Myth #1: It's Rambus vs. DDR vs. MRAM. It's been mentioned before, but bears repeating: MRAM will not be the next generation memory technology. It will at best be the next-next-next generation memory technology, as it's at least 5 years from commercial viability. However, I'd guess that even in MRAM's wildest dreams it will take longer than that before it ever makes it to PC main memory; first, it will be used as a replacement for what it is actually most like--not DRAM, but flash memory. While it has the potential to maybe one day be faster, smaller, and cheaper than DRAM, until then it will only be used in those places where its most important attribute--nonvolatility--is actually necessary.
Furthermore, there are any number of exotic competing technologies which are a) going to make it to market first and b) actually aimed at the PC main memory market. These include:
VC SDRAM: like SDRAM with a small SRAM cache--already available, but with disappointing performance, due to a bad implementation of a good idea; don't count it out in a future incarnation
FCSDRAM: which allows a more efficient ordering of access requests to cut down latency
DDR-II: the packet-based successor to DDR SDRAM, and the probable next standard
DDR-IIe: DDR-II with caching technology similar but superior to VC SDRAM's
and eDRAM: an exotic technique for putting DRAM directly on a microprocessor, which allows for extraordinary bandwidth and tiny latencies but requires an entirely new manufacturing process.
In any case, the above are not mutually exclusive (indeed, RDRAM is a DDR type of SDRAM), and I wouldn't be at all surprised to see some VC/e FCDDR-II be the PC main memory of choice in a couple years. (It'll have a better name, though
Myth #2: DRAM bandwidth is holding back the performance of today's PC's. Actually, the problem is not in the DRAM chips but rather in the bus that connects them to the CPU--that is, the Front Side Bus (FSB). The FSB on all current Intel chips is only 64-bits wide, single pumped. That means you only have 1.1 GB/s of bandwidth to the CPU with a new 133 MHz FSB P3, 800 MB/s with a 100 MHz FSB P3 or P2, and a measely 533 MB/s with a lowly Celeron. Not so coincidentally, the maximum bandwidth of the various standard types of SDRAM, PC133, PC100 and PC66 are...1.1 GB/s, 800 MB/s, and 533 MB/s respectively.
Ever wonder why 1.6 GB/s RDRAM wasn't any faster than 1.1 GB/s PC133 on all those P3 benchmarks earlier this year? At the time you probably either heard from someone else (or decided yourself) that it was just because "Rambus sucks," which, while true, isn't the whole story. Instead, the reason that the faster RDRAM didn't perform any faster is because its extra 533 MB/s of bandwidth is all dressed up with no place to go--it certainly can't go to the CPU, because the FSB is in the way, and it only lets through 1.1 GB/s. Now, there are couple edge conditions where that extra bandwidth can be utilized by sending some over the AGP bus and keeping some in buffers on the chipset to send later, but by and large the P3 is completely saturated by plain old PC133. This is the same reason why, when DDR chipsets finally come out for the P3 in a couple months, their performance is going to be a mite disappointing--all this extra bandwidth, no place for it to go. As for why the RDRAM system is actually slower most of the time...well, that's because Rambus sucks. (RDRAM has higher latencies than SDRAM, plus Intel's i820 RDRAM chipset is nowhere near as good as its BX or i815 SDRAM chipsets.)
Luckily, this is a bottleneck that is finally getting removed. AMD's Athlon and Duron CPU's both have double-pumped FSB's, meaning they'll be quite happy slurping up the extra bandwidth they get from their DDR chipsets, due out hopefully by October. Their FSB's can currently be set at either 2x100 MHz (1.6 GB/s) or 2x133 MHz (2.1 GB/s). And Intel's upcoming P4 goes a step further--it has a double-wide double-pumped FSB, allowing 3.2 GB/s @ 100 MHz core clock, and 4.3 GB/s @ 133 MHz.
These steps are, to put it mildly, vastly overdue, as the ratio of CPU-clock to FSB-clock has gone from 1:1 in the pre-486 days, to 2:1 with the 486DX2, to, for example, 3.5:1 on the two year-old P2-350 I'm typing on now, to a ridiculous 8.5:1 on the latest greatest (nonexistant) P3-1133 to a miraculously exorbitant 10.5:1 on a Celeron-700. What this means is that that CPU is spending a whole lot more of its time waiting every time it needs to access memory--10.5 clock cycles for every 1 cycle of memory access, to be exact. While the impact of this can and has been minimized through all sorts of tricks like bigger caches, out-of-order execution, and prefetching compilers, the overall performance impact is "damn."
So thankfully these ridiculous ratios will finally be brought down as the next generation of CPU's with decent FSB's ships.
Having read this, you're probably now lulled into believing our third myth. Unfortunately, you're wrong.
Myth #3: DRAM performance will hold back the performance of tomorrow's PC's. As it turns out, that's not true either. For proof, just take a look at the latest generation of PC graphics cards. The latest and greatest offerings from ATi and nvidia both include 64 MB of double-wide DDR SDRAM at speeds up to 2x183=366 MHz. That's 5.9 GB/s of bandwidth, way more than enough to saturate the FSB of top-of-the-line CPU's for at least the next 18 months. All this is available, plus a very complicated GPU, fast RAMDAC, and some other components, on a card selling for about $400--thus we can guess that that 64 MB of 5.9 GB/s RAM costs around $250--or, humorously enough, about the cost of 64 MB of 1.6 GB/s PC800 RDRAM! Furthermore, nvidia just announced the GeForce2 Ultra, with 64 MB of 2x250=500 MHz DDR. That's 8 GB/s!! The cost? Another $100.
But all of this is disregarding that little something called supply-and-demand. There are several legitimate reasons why such high-speed DDR costs more to make than normal-speed DDR (which costs a negligable amount more than plain-old SDRAM), but the main reason for its (not even so) high price is its scarcity and the incredible demand for it by graphics card makers. On the other hand, the main reason RDRAM has come down in price so much (6 months ago it cost around 3 times as much) is because there is a glut of it on the market. Everyone in the industry (except Dell) has realized that the i820 chipset is a dud, a bomb, already shuffled off to obsolescence. RDRAM on the PC is a no-go, at least until the P4 comes out. Thus, excess RDRAM is being sold-off at fire-sale prices. Once the P4 is out in enough volume to actually impact prices (i.e. January or February if Intel is lucky), expect another surge in RDRAM prices. Back on the other hand, in a year or so that 8 GB/s (!) 500 MHz DDR SDRAM in the new GeForce2 Ultra will be pretty mainstream stuff, going for but a modest premium over even bottom-of-the-line SDR SDRAM (which will still be around for some time).
"So great!" you might say. "Let's make chipsets with 8 GB/s FSB's, and all our problems will be solved!" Well...there's the rub.
See, the point of this story is, the problem in getting a high-speed memory subsystem in your PC is not the DRAM--they can get that damn fast already. (8 Gb/s!! Ok I'll stop now.) The problem is the stuff in between: the motherboard and the chipset. That is, the bus.
It turns out that it's easy to get a super-high-speed bus onto a graphics card, but an electrical engineer's nightmare to get one on a PC motherboard. Let's count the reasons why:
1) The traces (wires) on a motherboard are a whole lot longer than on a graphics card. The higher the capacity of a trace, the higher quality (read: more expensive) it has to be. The longer it is, the higher quality it has to be to have the same capacity. Eventually, it's just beyond the capabilities of our current manufacturing to make traces that are long enough and high enough capacity to work with high-speed DRAM on a big motherboard.
2) There's lots of other components on a motherboard. This means more interference ("crosstalk"). This means--you guessed it--the traces need to be even higher quality.
3) A motherboard has to be designed to work with almost any amount of DRAM--one DIMM, two DIMM's, three DIMM's, of varying amounts, made by anyone from Micron to Uncle Noname. Graphics cards are fixed configurations which can be validated once and forgotten about.
4) The DRAM in a graphics card is soldered to the board. The DRAM in a motherboard has to be removable and communicate through a socket, which adds to the electrical engineering complexity.
Plus there's probably a couple more I can't think of at the moment. The point is, the weak link in the memory subsystem is not the DRAM. Today it's the chip's FSB, next year it will be the motherboard and the chipset, but it's not the DRAM.
However, there are ways the DRAM might be changed to get around this limitation. (Disclaimer: I don't know as much about this part of the equation as I do about the rest.) Apparently the packet-based protocol used in RDRAM is one way to do this--for some reason, communicating in packets minimizes the danger of data loss due to crosstalk. Probably for the same reason it works for networks, the Internet, etc.
Great! The problem is, RDRAM isn't designed to maximize bandwidth, but rather to maximize bandwidth/pin. While this is real neat for itty-bitty embedded devices where you need to keep pin count to a minimum, the problem is that each pin is connected to its own trace...and thus RDRAM ends up requiring the motherboard to carry much more bandwidth/trace than DDR SDRAM. See above (#1) for why this is a bad idea.
So, the packet-based, but-otherwise-more-or-less-normal-DDR DDR-II, due out in 1.5-2 years, looks like a good candidate to solve this problem, at least for the time being.
In my opinion, though, even that is only a temporary solution. I'd say eventually the industry is going to have to give up the idea of expandable RAM, and change the entire architecture of the motherboard so that the CPU and main memory are moved off it, onto a daughter card, like the graphics card is now. That would mean you would have to buy your CPU and your RAM together--no more adding more RAM as a quick performance booster, which would be a considerable loss. However, it seems as if it would get rid of the tremendous memory bandwidth problem PC's are facing today in one fell swoop. In comparison to the performance gains realized, it would be an easy tradeoff for the vast majority of consumers, who never upgrade their RAM anyways.
The other possible solution is similar-but-different: a switch to eDRAM, which I discussed lo these long paragraphs ago (up near the top). This, however, would require an even bigger infrastructure change, although the benefits might be even greater.
One thing I've seen briefly alluded to (such as at the EDTN link - "no exotic materials") but not well discussed is that manufacturing MRAM may be less environmentally damaging than making DRAM. Current DRAM-building practices are pretty vile, which is one reason they tend to be done in export processing zones where poisoning the local flora, fauna and human population is considered acceptable to keep the cost down. Anyone know whether MRAM is really any better in terms of manufacturing process and the effluents thereof? I'd be much more likely to buy into it if it's a more sustainable technology; some of the kind of stuff we've got now in computer production has got to go.
-- Life is short. Forgive quickly. Kiss slowly. ~ Robert Doisneau
Just to elaborate. non-volitile memory would allow incredibly fast boot-times, since all of your drivers (and even your kernel) could remain resident across power-cycles. Assuming a robust enough OS that can withstand months of virtual-uptime (ruling out DOS-derived OSes), the boot-up process shifts from initializing your drivers to checking for HW-changes / crashes.
Just imagine the possibilities for OS robustness. Currently when we lose power (causeing an OS crash), rebooting involves checking for consistency on the file-systems (a painful process which usually involves loss of some information). Yes, you're supposed to UPS servers, but this is of no consolation to the millions of home-PC users who potentially lose hours of work. If memory was NV, then a copy of the write-buffer would still exist, and it would be possible to recover failed disk-updates.
-Michael
The simplest approach would be to have a massive ram-disk.
However, expanding on this possibility, there would be a fundamental change in database structure. Databases are optimized to allow tiny subsets of data to reside in memory. Most queries have to assume that only a couple pages will be addressable / comparable at a time. One of the biggest set-back with this is the lack of "data-pointers". You typically refer to data by it's primary key. Thus referencing data-items requires table-lookups. In most programming languages, you make use of references or even direct pointers (though in DB land, I'm sure references/handles would still be preferred). Thus, if table-joins were based on references (for primary / foreign keys), it would be trivial operation. I know that Oracle supports a sort of reference-type that performs just this sort of activity, but it has to still require disk-index-lookups, since the data is not in a static location.
Another big problems with relational databases is that it is very difficult to map them to program-code. A big push in DB land is to make Object Oriented DBs. Some systems have had more success than others. The biggest problem (as I see it) is to make these objects available to programming languages in a seamless fashion. In an all memory system, you might very well be able to have a local array of data-objects and use them with all the same performance as local objects. The DB would simply have triggers assigned to data-modification method which update internal relationships and enforce data-integrity rules. This much can already be done in a raw programming language, but it is impossible to separate the rule-set from the code (unlike in DB design).
This really does open up a whole new world of computing. Ideally, you have at least three completely independent designs (that can be changed independently of each other): The interface, the data-definition/rule-set, and the glue-code that makes it all work. Currently this is possible if the GUI designer (beit web pages or window-design) talks with the glue logic designer, and a relational DB is used. But there currently is not a seamless integration or high-performance connection between the data and the glue.
-Michael
-Michael
Just how complex is SRAM to build? Please note first that I don't know much about SRAM.
As far as I know, SDRAM requires 1 capacitor and 1 transistor per cell minimum. SRAM requires about 4. With companies today manufacturing 256M SDRAM, could they easily build 64M SRAM modules for a similar price?
The latency of these SRAM (not reliant of capacitor discharge) could push memory bus clock rates up to several hundred MHz. Data from an SRAM is available in a nanosecond or less, not 3 to 5 ns.
The other part of my comment is on a RAM drive. Could a memory manufacturer revive obsolete memory technology (fastpage, 30-pin SIMMs) that is extremely cheap? If so, they could produce an inexpensive 1-2 GB memory module that sits on an IDE interface. You could easily use the full bandwidth of an UATA-66 channel.
Instead of resorting to (comparatively) super-slow hard drive for virtual memory paging, the OS could just use a slightly slower memory technology. Using RAM negates the seek times that are inherent to hard drives.
You will need an exceptional kick-arse interconnect structure to get decent performance out of the various CPUs. This would be especially true if code running on one CPU needed data from another processor.
A couple of extra points:
- What happens when you want to upgrade your CPU?
- Memory becomes more expensive as a processor is tightly coupled to it.
I shudder to think of the kiddies at primary school arguing over the benefits of a hypercube compared to a mesh interconnect structure.
MRAM could be a fun thing. Virii get embedded in the memory and stay in there FOREVER, continually wreaking havoc. Also, hackers could embed flags in your memory so that every time you boot up they know it. Geesh, if it stays in there until the computer says, "erase it" it may be wise to erase every time the machine goes down or boots up so that nasty stuff doesn't stick in there. Catch my drift, or am I way off?
Not to be a prick but "RAM Memory". So is that random access memory memory? Kinda like a NIC card, ya know a net work interface card card. I'm a bastard.
thx
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Nicotine free Amish .sig.
EDTN
Stanford
ABC News
Hope this helps.
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Nicotine free Amish .sig.
I'm not saying its going to be the best way to go, but I can definitly see us using DDR on our desktops and notebooks. It just seems like the next step in the technology. Although personally, I would like to see leaps and bounds in memory technology, DDR doesn't seem like that much of a jump.
First of all, RDRAM, SDRAM, and DDR SDRAM are all forms of DRAM, the only difference is in the interface between the memory array itself and the outside world. SDRAM and DDR SDRAM both accept an address from the address bus and output the data on (or write the data from) the data lines. RDRAM uses a packetized interface which can be more efficient for linearly accessing memory, however, it is extremely slow for randomly accessing data. However, all of these types of memory are forms of DRAM that have single transistor/capacitor cells which can each store a bit. One interesting thing to note about DRAM is that it may not be able to scale down much more: As processes get smaller, capacitances get smaller and transistors no longer completely turn off (meaning charges can leak off). This means that the cells need to be refreshed (recharged) more frequently, limiting the usefulness of the device.
MRAM is a new technology that stores data magnetically. I don't know too much about this, but I would be guessing it would be quite a while until we see this in every computer. It will probably be available in portable devices in 2 to 5 years, however, low production quantites (and high prices that go along with this) will almost certainly keep this memory technolgy from entering the desktop market for ten years or so. Then again, I could be wrong.
I have seen flash memory mentioned as a possibility. Flash works by storing (or not storing) a charge on a floating polysilicon gate. The charge is stored or removed by using a high voltage to tunnel through the silicon dioxide insulator. While flash can be read about as fast as any other memory technology, writing flash typically takes a long time (from 100's of microseconds to milliseconds). Also, the tunneling action erodes the silicon dioxide and can wear out flash cells after 1,000 to 1,000,000 rewrites (depending on the process).
So what is the next big memory technology? For now, I would say it is DDR SDRAM. However, DRAM technology will eventually fizzle out and I am sure that either SRAM (Static RAM), MRAM (if it is available), or some other new memory technology will take its place.
here's a fun thing to do with mac OS 7 (I did this with quadras, pmac8500s, the blue&white G3 the Gray and White G4 and the imac DVs... I think its just a software featuture that takes advantage of something thats been in apple rom for a while now)
Start your machine. Use the memory control panel to make a ram disk of sufficient size to hold a small (or full if you wish) system folder. with 128Mb of ram a 64mb ram disk usually does the trick with a bit of stripping out of crap. Also a minimal system 7.5.5 can be as small as 2-5Mb depending on the machine it supports. Now make that ram disk your startup volume and reboot. Notice how it boots pretty quickly by comparison to disk. Also on a quadra you'll notice the whole thing is faster because loading quicktime or something becomes trivial.
-Daniel
Another type of non-volatile RAM tech I read about just recently is the explicit write/erase kind. That's right... EWE-RAM
(I apologise profusely)
Any sufficiently advanced civilization is indistinguishable from Gods.
Well, may I be the first to say...
Can you imagine a Beowulf cluster of these?
uh... no, I can't either.
(pass the french onion RAM dip)
Any sufficiently advanced civilization is indistinguishable from Gods.
RDRAM is FAR too expensive to be the next standard. 256MB of the stuff is something like $800 or $900.
Just goes to show how much things have changed...
No. That is a power saving mode. RDRAM still forgets everything when the power is cut off.
Oh yeah I can see it now - infinite blue screen !!
Oh yeah I can see it now - infinite blue screen !!
The only solution would be Read Only MRAM - a return to the days of ROMRAM :->
Bubble Memory.
From this site there is this def. A type of non-volatile memory composed of a thin layer of material that can be easily magnetized in only one direction. When a magnetic field is applied to circular area of this substance that is not magnetized in the same direction, the area is reduced to a smaller circle, or bubble.
It was once widely believed that bubble memory would become one of the leading memory technologies, but these promises have not been fulfilled. Other non-volatile memory types, such as EEPROM, are both faster and less expensive than bubble memory.
A better link has actual tech trawings and data sheets.
And the final link for today tells of 128K and 512K devices in 1981! (Hint: that was alot of memory!)
If it was said on slashdot, it MUST be true!
Currently at 5MHz and 256kb the FRAM (Ferrous RAM) ICs that they have available aren't nearly fast enough to work as a replacement for the average desktop system. Ramtron doesn't offer much of a description of *how* FRAM works, but could this currently existing technology be built upon to fit the requirements?
I'm assuming a lot in thinking that this is similar technology (I hear ferrous, I think magnets), so I'd greatly appreciate a good whack on the head from any enlightened people.
While it might not be useful at all in desktop systems, it does certainly look like an excellent replacement for both SRAM and ((E)E)PROMs.
- Ek
I did some work with Integrated Magnetoelectronics (IME), a small company that's developing a nonvolatile *solid-state* memory--solid state meaning it has no moving parts that would slow retrieval times *AND* is random access, unlike flash, which is also solid-state. Also based on GMR, it's called PRAMM (permanent random access memory). It basically works exactly the same as the old addressable nonvolatile core memories from the 60s and 70s, but only much smaller--the GMR effect allows the size of the charges to be reduced so that a few hundred megabytes don't take up an entire basement ;-).
I cowrote an article about it: Magnetic Field of Dreams--if I could plug my own stuff so crassly.
Like every other nonvolatile RAM maker, IME are still in the kilobyte-stage of prototyping and who knows if it'll scale. It would be great if it would though--if so, imagine accessing your entire hard drive as quickly as you would RAM and having your screen return to where it was when the cat tripped over and pulled out the plug . . .
Joab
It's sad to say, but it's likely that the next RAM technology will be the one chosen by inductry, not necessarly for the best performance (or price), but as the technology maximizing profits (while minimizig risks). Taking a look at the what's going on with Rambus, you see that marketing is more important than technology.
I don't think the RAM companies are likely to switch from a technology they fully control to another they're less sure about. The only way I see they could do the switch from Silicon to something else is if they really have no other choice, eg. if some technology comes out and increases by at least a factor of 10 the performance/price ratio. Even in that case, I suspect they'd simply try to buy out the company that produces that.
The only way I see them abandon silicon is when it is no longer feasable to cram more transistors in a fixed area (10 nm? 1 nm? 1 A?).
Opus: the Swiss army knife of audio codec
do you really think it will be as easy to make RDRAM at 1.6GHz as it will be to make DDR SDRAM at 266MHz DDR
I'd like to get a confirmation on this, but I think the "next generation of RAMBUS" will be wider, not faster clocked. As for the rest, I agree that DDR-SDRAM is likely to be the next generation RAM... unless RAMBUS is in bed with more people than we think.
Opus: the Swiss army knife of audio codec
Just why do you think this will help Microsoft at all? The whole reason you had to reboot in the first place was beacuse Windows fscked up in memory and didn't know quite what. Rebooting the computer would mean this: After sitting through your BIOS test sequence, you are presented with a Blue screen.
The P6 bus does only about 1 GB/s, but the Willamette bus does 3.2 GB/s. SDRAM can only do about 1 GB/s, while RDRAM can do 2.1 GB/s (I think that's right...), so RDRAM will be much faster on Willamette than on P6 (which is limited by the bus, not the RAM). The limitation today is the bus, but for the Pentium 4 the limitation will be the RAM. RAM speed is overrated; an L2 miss only comes along once every several million cycles!
Slashdot questions RAM
But no links in this story
Sites stay up today
Yes, there's been talk of making RDRAM data paths wider, but this isn't the point. That discussion is mainly about increasing bandwidth, which helps performance when you have lots of throughput but otherwise faster is better. You can make SDRAM paths wider, too, and add additional channels. There's a lot that can be done to improve either RAM technology, much of which has to do with improving chipset and motherboard design--which IMHO are the big bottlenecks today; the fundamental architecture of x86 mainboards hasn't changed much in far too many years. Personally, I'd like to see a pooled architechture like the SGI Visual Workstations, where the rest of the system is basically built around the memory implementation. But in the world of standard vanilla x86 boards, too much performance and stability is sacrificed to old and slow bus architectures and data paths which aren't wide enough.
But my point about RDRAM is that it has to be clocked at 800MHz to equal the performance of PC133 SDRAM, and that's horrid. Memory performance in SDRAM can also be increased by other means than clockspeed, too, but SDRAM has so much headroom in the clockspeed department that there's no need to worry about that for some time yet, whereas RDRAM clockspeed is horribly fast with so little room for MHz jumps. I mean, most people have CPUs that don't run at 800MHz, ferchrissakes. Even a top-of-the-line graphics processor like the GeForce 2 Ultra runs at a mere 250MHz, with on-card memory running at less than 500MHz DDR. AGP is running at a mere 66MHz. PCI is still the slowpoke at 33MHz, and really needs to be improved because it is a bottleneck. But the point is, the RDRAM is running so fast that it has so little room to increase its clockspeed at all, whereas SDRAM has so much room.
"The more corrupt the state, the more numerous the laws."--Tacitus, *The Annals*
MRAM is probably five or possibly more years away, so it's not going to be anywhere near the "next generation" of RAM tech. Check out the front page of ArsTechnica for some linkage.
The next generation of RAM is clearly going to be DDR-SDRAM, and will be for some time. Cheap modules will be PC-200, but PC-266 DDR will be out at the same time, with very little use of the "mere" 200MHz (effective) variety. The tech is there right now, it's just that there's no demand yet since there aren't any chipsets out (VIA to the rescue, in a few months); so, regular SDRAM is tying up production right now, but the switch to DDR will probably be fairly smooth.
Face it, RAMBUS RDRAM is a terrible idea in the first place. When you have to make a new technology like RDRAM run at 800MHz to get similar performance to existing PC-133 SDRAM, that should be a sign that the new technology is worthless--do you really think it will be as easy to make RDRAM at 1.6GHz as it will be to make DDR SDRAM at 266MHz DDR? Hell no. I predict a quick demise for RDRAM within a few months of the release of VIA's forst DDR-SDRAM chipset.
"The more corrupt the state, the more numerous the laws."--Tacitus, *The Annals*
I tend to like the concept of MRAM. I don't know about anyone else, but I would be willing to wait 1-2 years for it. To me it only means that the currently planned 2nd box will be built on schedule but the also planned 3rd one will wait a while (until MRAM is available.)
Kez
I'm sure that a Male Sheep is the only RAM we'll be hearing about in the future.
Drag n' Drop DVD Recommendations
However, I figure when this comes out that there will be some sort of memory partition between deep storage (which will replace your hard disk) and memory for running programs. Most likely stuff will still have to be copied across during startup, but it will at least take place at a much higher speed.
Oh no! Then what will the Linux advantage be? ;)
I see MRAM and similiar RAM devices which retain data after power down as the definite future. What they do is eliminate the need for a hard drive. Imagine 10 Gigs of MRAM. What do you need a hard drive for?
You would no longer need to boot (or at least not often) because your operating system would be loaded already, with all the programs you were using.
Wasn't Rambus and the i820 chipset supposed to do this, Suspend to RAM, is what I remember intel calling it
Read my plan to save the Bengals
Strange that they'd be EST, considering they're in michigan..
Those who can't do, teach. Those who can't teach either, do tech support.
This could be implemented with current systems with only BIOS update if we had MRAM.
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Spelling and grammar mistakes left as an exercise for the reader.
If you think about it, with a couple GIG of ram on a server why *not* load the entire database to ram? :)
If you think education is expensive, try ignorance
the smart money is on the new Dodge RAM.
with a supercab and a more powerful engine, you just can't beat the deals that most places are offering on it.
FluX
After 16 years, MTV has finally completed its deevolution into the shiny things network
"It is seldom that liberty of any kind is lost all at once." -David Hume
CMOS settings
<O
( \
XGNOME vs. KDE: the game!
Will I retire or break 10K?
I think the next cool idea in RAM is a merging of RAM with microprocessors to create what was once referred to as IRAM. That is, IRAM would have one CPU per RAM chip, like a sort of system-on-chip configuration. With 512MB of RAM on your machine, there are perhaps four to 32 individual silicon chips with RAM memory, depending on the density of the RAM.
Hence, if that was IRAM, you would also have four to 32 individual processors.
The idea, of course, is to distribute processing and increase performance by having the RAM and CPU on the same silicon, thus reducing the path length, eliminate the need to go through a motherboard bus and connectors and all that. More power efficient, lower EM interferance, etc.
The question would remain whether to have a central CPU coordinating all of the individual CPU's, or whether the system would be entirely distributed. I think if there was a central CPU, the system would be easier to make it look like a SIMD machine to software, which would make it easy to program for. That may be possible without the CPU, but the alternative is MIMD.
Who knows, with a kernel made for distributed processing like Mach, which is may see growing attention because GNU Hurd and MacOS X both use it, then a large part of the computer market may benefit from IRAM.
This isn't as much "normalization" as it is "don't take so many drugs when you're designing tables."
Me thinks that if MRAM can store data persistently why have hard disks at all. Give and take another year and we'll be running on RAMs only.
Short for Gaia RAM. How many terrabytes of space are we leaving to waste in all the trees, rocks, people, and gerbils in the world? I/We/Gaia owe it to the harmony of the universe to harness this potential!
There is one company, Micromem, that is developing a ferromagnetic based RAM in conjunction with Honeywell. They describe, from the company website, that their product, MagRAM, as non-volative memory with DRAM "like" speeds. Their R&D is being done at the Center for High Technology Materials located at the University of New Mexico in Albuquerque. There is little technical information at the site about their technology but they claim MagRAM is high density, low power, has no read/write fatigue and is concurrent read/write feasible. It sounds good, but by the look of the website, the company is more interested in their stock price.
.Mike
Write only memory
Oops. Time for my medication again.....
Feed The Need[goatse.cx]
But however good MRAM is it is always going to suffer from the fact that it will receive less investment than other more mainstream technologies such as SDRAM or Flash. The effect of this is that the capacity and storage density of MRAM is going to lag behind the competitors, not because it is inherently a worse technology, but just because it receives less investment.
The only way MRAM is going to get anywhere is if it gets adopted by a major chip company that can afford the $billions initial investment and then pushed hard (e.g. Intel and RDRAM). Even then it has do deliver the goods or it will become a white elephant (e.g. Intel and RDRAM ;-)
A more interesting question is, does this technology mean that on-line storage (currently hard disks) might become faster? If you could have several gigs of magnetic storage in your machine accessible at RAM speeds (lets be sluggish and call it 80ns), then that would mean some very, very, very high-performance systems become viable.
I'm assuming that MRAM is going to hit the market at around the same price as normal memory, so it's going to be a lot more $/Mb than hard disks, but it still presents some interesting oppurtunities.
- Wedg
Jake
Dating: while( 1 ){ call_girl(); get_rejected(); drink_40(); } return 0;
Alright so it doesn't retain the data when it's switched off but it does use it's own power supply so you can turn the host machine off. It's a PCI card and it supports Mac OS, Windows NT, Windows 2000, Linux and Free BSD.
Oh and it's got a good number of flashy lights on it too.
wrighty.
Found out that it had been mention on /. a few months back:
http://slashdot.org/articles/00/ 05/26/127220.shtml
wrighty.
No, I'm not going to declare it the greatest computer ever, but one of the cool features it did have was a Recoverable Ram Disk. It could survive a power outage or even flipping the power off manually. There were even hacks for the game units based on the amiga (since they had no disk drive) where you would use a bootable CD, rebuild the OS on an RRD, and then flip the power switch and actually have it BOOT off of the RRD.
That's just crazy.
- My password is slashdot
If you check out the Matrox Users Resource Centre's news story for August 7th, you'll see a some info from within the latest driver release showing the G800 will be using something called FCRAM. Apparently thats "Fast Cycle" RAM, and is more or less a faster SDRAM. There's a short article here about what FCRAM is. It's built by Fujitsu and is supposedly better for multimedia applications where there is a significant amount of random access. There must be something to the tech, otherwise Matrox would be going with the more standard DDR SDRAM, which must be cheaper to produce because everyone is using it...
I've always been of the opinion that RAM that is erased when the computer is turned off is a good thing. The ability to erase all your RAM to me is like "starting fresh", similar to rebooting Windows to regain some temporary stability.
What would happen if a virus was loaded into your memory and you wanted to shutdown and wipe the virus from memory, but your memory was permanent? I don't see that as a good thing at all.
There are probably many arguments for why static memory is a good thing, but right now I am definitely leaning toward memory that can be erased by powering down.
Magnetic memory? Anyone here old enough to remember PDP-11's with magnetic core memory? Used to be the fastest stuff around compared to the static and dynamic RAM of the day. Someone using nanotechnology to make dense cores?
edo
The other side of optimizing for the latest and greatest is that software must remain compatible with the majority of users' computers, or you won't sell very much. For example, I can't use anything that requires AGP, MMX, or an internet connection faster than 14.4 Kbps.
This same compatibility issue is what causes our computers to pretend to be 8088's when they first start up. You couldn't leave it because nobody would buy the new thing because there'd be no software... and there we sit.
--
LoonXTall
~~~LXT~~~
Life is like a computer program: anything that can't happen, will.
I'm not sure if this has been mentioned yet or not, but Kentron Technologies is developing a technology known as QBM, which, to put it in a nutshell, is basically Quad Bandwidth Memory, which means that it transmits twice each cycle, with overlapping cycles, effectively doubling the DDR effect. Their page on it says that memory running at 100Mhz clock could get memory bandwidth of approximately 3.2 Gigabytes/second.
Heh, that's the stuff I want when I build my Ultimate Gaming Machine (TM).
Friends don't let friends use multiple inheritance.
SLDRAM ( SyncLink ) sounds like a good alternative to rdram. Specs: -200 MHz -64 bit bus -sends multiply data signals during each clock cycle -lower latency than rdram -can be DDR'ed -royalty free I don't see any down sides to it. Anyways, this is my first slashdot post, so I hope it proves useful. -Yrm
I think that this MRAM could be great, it could be used as both storage and as system memory. Like those outrageously expensive SDRAM drives but cheaper and held the info after poweroff.
.08 micron model in the 2.5-3Ghz range, and i go out and buy a "mass storage Device".
.002ms,
For example, i go buy a new athlon hammer in two years, say the
It would be great to just walk in and say, "OK, i need about 1.5Gigz of Random access and another 25Gigz for storage". My friendly non-commisioned BestBuy guy says "you should look at the new seagate drive at 50Gigz" and maybee even give me a pamflet on how to partition the drive so that i can have my Gig anda half of ram. All this with a device using MRAM so it is lightning fast and compatible with ATA-266 with and avarage seek time of
or would that be latency??
Berkeley called it IRAM (for Intelligent RAM). Inferring to the fact that since the DRAM has more transisters than a processor core, it would be more like you have RAM with a processor inside rather than a CPU with RAM inside. I don't think it's that great of an idea now for general purpose CPUs. DRAM latency isn't decreased all that much, and you're stuck with whatever amount of DRAM your processor has built in. You could of course add more offchip as a second level RAM. But if you use the onchip memory as a cache for the offchip memory, the latency to offchip RAM is increases as a result of the additional miss penalty from the onchip memory. This would be more significant than a SRAM cache miss, because SRAM is so much faster than DRAM the miss penalty is almost unnoticed.
DRAM latency is just too slow. The performance gap between processors and DRAM has been widening exponentially. Pretty soon, processors would be spending thousands of clock cycles waiting for DRAM accesses. Increasing memory bandwidth doesn't solve that. Programs often need to read from some memory location before they know where to read/write next or what to calculate next. You'll inevitably be waiting on successive short reads and writes. Prediction, speculation, and parallization can't go far enough to hide DRAM's poor latency. The shortcomings are already very noticeable. Doubling clock rate doesn't make Win2k boot or run near twice as fast. Office applications aren't really getting any faster. We really need a memory technology that can keep pace with processor speeds, if such a thing is even possible.
Acer Labs http://www.ali.com.tw has a chipset out that supports ddram and I think Iwill http://www.iwill.com.tw is already making boards.
Just a Tuna in the Sea of Life
Core memory has been out and around for megayonks!
It was one of the first solid-state memories for early computers before they went to capacitive storage a la DRAM.
The military still uses it because it is largely immune to radiation and EMP.
Recently, they have been able to shrink core memory on to microchip VLSI scales.
Nothing new in it at all...
.. we're just going full circle!
-- The universe began. Life started on a billion worlds...
-- Except on one where stupidity was there first.
Anyone remember the magnetic core store? 256 bits you could hold in the palm of your hand. Ethel.
Great...I certainly hope the memory of the future doesn't have that characteristic....or at least, I hope computers are stable enough in the future that it won't matter. Being a *gasp* user of windows myself, I would be totally screwed if I couldn't reboot every now & then to clear out all the crap & garbage that windows puts in my memory. I personally think the memory of the future will involve fiber optics...I heard that someone once tried to build a computer using fiber. So, if it's possible to reinvent the transistor to store light (possible with mirrors? I don't know, I'm no computer engineer), then I think that is what we'll ultimately be using.
Time is fun when you're having flies.
-Kermit the Frog
First up, it's DDR-SDRAM... DDR is just a modified version of current SDRAM design practices in that the clock rate is half the data rate, rather than the full rate. Since the pads (to connect DRAM chips to the circuit board) only support lower bandwidths than inside the chip, if we halve the clock rate it transitions at the same rate as the data. This means that, if the clock goes at the maximum speed supported by the pads, we get data going twice as fast - hence, double data rate. There is no such thing as "DDRAM"...
RDRAM has some very nice design ideas behind it; I think it is good technology and may have a future one day. However, for a number of reasons, its time is not going to be now:
- Because of the fact that the controller design is totally different to what they're used to, Intel have not lived up to their usual performance in the i820 & i840 chipsets. It's not just latency that's holding RDRAM back in the benchmarks. I would expect DDR designs, because of the evolutionary nature, to hit full performance right away.
- Cost is currently way too high given the performance: at double the price of PC133 (because of lower demand, yields, royalties and various issues) it's simply not good value at the moment
- Rambus has managed to alienate just about every other company in the industry through bad PR, and don't get me started on the appropriation of JEDEC standards as their own patented technology...
I think, had things gone differently, it could have a future - there _are_ some good points to the technology, such as lower pin count - but I can't see it becoming widely adopted outside of consoles & embedded systems (where it is best suited) for the foreseeable future.
" ...Maybe we should optimize what we've got more...."
You know, this principle holds for software development too... The potential for a LOT of what we do with computers today was present in the humble old 486. Maybe this mad dash for better faster hardware spells our own doom. already people are buckling under the complexities of things like the psx2, x86 extensions, massive ram on video cards, etc. the stuff is going to waste just as fast as it can be invented.
it's simply too much to work with or take advantage of with the tools we have nowadays (in the time alotted us). I wish software could advance at the same rate as hardware, but it takes years of tinkering and developing new techniques to get anywhere near taking advantage of ALL of a given piece of hardware's potential.
Just look at an example like 3DStudio: version 3.0 is dramatically more sophisticated and powerful than version 1.0, and v3 runs better (is capable of more, easier to use, faster for certain tasks like modelling low poly stuff?)on p200 than 1.0 would on a pIII. all the hardware upgrades in the world don't help a bad app very much.
As hardware continues to advance by leaps and bounds, will the gap between it and software be growing much? what are the repercussions of this? lazy and imcomplete coding do seem to be becoming the standard rather than the exception...
maybe there'll be an 'Einstein' that springs up to turn the software engineering world on its ear. until then, the over-all essence of computer use will grow at a fraction of what the state of the art hardware is capable of.
:)Fudboy
:)Fudboy
I guess I'm only a Fudboy, looking for that real Transmeta
This MRAM sounds a LOT like old-fashioned core memory.
It didn't lose the data it carried after powerdown, either.
Paul Anderson
"I drank WHAT?!" -- Socrates
Let me see, I used to work on UniSys mainframes, and they all had magnetic NDRAM (Non-Destructive RAM), and the problems were :
1. Slower than solid state devices
To change the state of a register you had
to modify the magnetic field
2. Consumes more power. It is more power hungry to
change the state of a magnet than it is to
change the state of a flip-flop
While the idea of Non-Destructive RAM is nice (Power off your machine, power it on and it picks up where it left off), there are much better ways to do this in solid state. You could easily (UniSys did) create a capacitance based NDRAM that isn't as hard to change the state of, and isn't as power hungry.
Just my humble opinion, maybe it makes someone more informed.
Deven Phillips, CISSP
Network Architect
Viata Online, Inc.
Wherever you go, there I am...
Similar in basic function to MRAM, NonVolatileFerroelectric RAM uses ceramic materials with interesting magnetic properties to store information. By tweaking the impurities in the ceramic, you can get volatile or nonvolatile components. Only problem is getting ceramic thin films to adhere to the substrate and each other.
H. Swan
NMIMT
Materials Engineering
---------------
Vpered na Mars!
Bear in mind that the insanely low cost of current HDDs is based on the same technology (more or less) as MRAM. The people working on this currently are approaching it from a memory poit of view. What happens when the HD companies get a hold of this?
If nothing else they should be able to use the technology combined with current HDD systems to decrease seek times.
the next generation of RAM has got to be "RAM: deep space nine." and after that there'll be "RAM: Voyager."
Malkovich Malkovich Malkovich Malkovich Malkovich, Malkovich.
On a related note: No non-volatile memory will not help you computer boot faster. Why do you reboot your computer? Because 1) something is messed up and you need to reload the contents of your RAM to fix the problem or 2) because a configuration change was made, and the reload is needed. It will however offer a lower power sleep mode.
Wired did an article on this guy at IBM a while a few months ago...am I the only one reading print anymore?? click here.
DDR doesn't quite work as you described. No current memory uses a single clock line, almost all have many clock lines. DDR for instance has matched pairs of clocks 180o out of phase, so when one set is rising the other is falling.
With Quad pumped memory you have 4 sets of clock signals, each 90o out of phase with the previous, thus each part of the cycle is controlled by one of the 4 sets of clock lines.
And no, Kingston's "quad-pumped" SDRAM isn't really quad-pumped either; it's just DDR which is cleverly interleaved to essentially make it twice as wide.
But DDR is just SDR that is cleverly interleaved to essentially make it twice as wide. *8')
Mark..........
--
If the world were an oyster, it would be mine.......
Not like $800 for 128MB of RDRAM. Makes me livid when I think of what I'll have to go through to replace my 320MB of SDRAM.
"Ancillary does not mean you get to rule the world." --U.S. Circuit Judge Harry Edwards, speaking to the FCC's lawyer
The 21264 uses SDRAM, while the 21364 will use Direct RDRAM. Latency is pretty good on both.
I'd like to install AMRAAM on my PC. Any advise?
IBM just created a quantum machine (we all know this) which used 5 molecules to operate as both the processor and the "memory". It seems that the concept of seperate hard drives and ram is soon to be outmoded; since basically every bit of data will be permanently loaded "into memory".
M period. Fresh, comma
When I was in school for my EE degree, in one of my computer architecture classes they handed out an article out of an industry journal (sadly I don't remember which one) that mentioned RAM on the processor die. It said they were talking about 90+ MB of RAM (in addition to an associative cache) but that was all the same registered memory that cache is today...the cache memory is much much faster than any RAM is, and there are no bus lines to worry about...
:)
Of course this makes the die bigger, but as we get to smaller process technologies this isn't so much of a problem.
I wish I still had that article...time to go dig through the boxes in the basement
Are the bozos over at Rambus claiming that they invented this magnetic ram technology as well? I can see it now.... "We sat in on a meeting about it, made some copies and ran and got a patent. It's ours! It's ours!"
~Bout Time for another tea party.®~
Not quite MRAM i'm sure, but maybe interesting to some. (and hopefully not too offtopic) My HP9100B computer from 1969 uses a type of magnetic storage memory. It has some 600 or nearabouts bytes of memory. it also uses magnetism for saving of data via cards. Its nice to see that old ideas can still be good ideas.
remebering an article i saw @ ars it's about carbon nanotube based memory, the memnory had a density of 10^12 bits per square centimeter and a theoretical operational frequency of 100 GHz i'm just supprised no one has mentioned it