Ceffecive is a measure of all the capacitance that will be charged/discharged by the switching. It appears in the equation for dynamic (switching) power. Call it what you will, but this is how we determine dynamic power.
I do enjoy being corrected when wrong, but I'm going to have to ask you for some more reliable source than yourself on this one before I can have the joy. Here are some points for you to ponder while you google for something to back up your claim:
Capacitance varies with gate area and inversely with distance between "plates" of the gate (C = k*A / d). Reducing the gate width (space between the plates) actually increases capacitance, and this itself would increase power. But, you're also able to reduce the gate area (though not as much, but in 2-dimensions, so shrinking gates is usually a slight reduction in C). But, if the (dominant) interconnect capacitance (see next point) requires a larger transistor to drive it (which will be the case if voltage is not reduced) then the Area of the gate will increase, and so the capacitance will be right back up to where it was before you shrank the process.
According to Intel, "transitor loads are comprised of >50% interconnect capactiance." Wiring capacitance does not necessarily decrease with process shrinks (and may even increase significantly from cross-capacitance, depending on wire pitch and spacing.)
Of course, the simplest way to show you that you're mistaken would be to send you some excerpts from process manuals showing that the capacitances do not drop with simple process shrinks in most cases, but that would probably get me fired.
Nobody said anyone was shipping 65nm parts, Mr. Irate. I said NEC and IBM put out 65nm parts. I didn't say they were on the shelves at the store yet.
Just like Intel is doing (internally sampling memory chips at 65nm to test and improve the process,) other manufacturers are using their 65nm fabs to make 65nm parts.
You can't buy anything in 65nm yet, but that doesn't mean they're not being made.
"The iPod group is looking for a Hardware Engineer. This person will be an individual contributor on a top notch team with responsibilities for the design, implementation, and integration of digital and analog electronics. Experience in the following areas is important: system integration, digital logic, SDRAM, Flash, ASIC's, processor selection, ATAPI, various communication protocols (ie: GSM, Bluetooth, IEEE 802.11, Firewire, and USB), display types and video and analog integration."
Does this mean we are very likely to see an iPod with a video display and capable of sending and receiving music via WiFi? This is very likely.
What strange language the author uses there. Is he answering his own question about whether it's very likely by saying yes, it's very likely? Or is he saying that it's very likely that it's "very likely?"
Thanks for the correct, but entirely unrelated comment about interconnect delay.;)
We were talking about power. Or at least I was, and though you were too, given your incorrect claim that "Of cause [sic] if you drop the dimention the power consumption decreases."
And, BTW, most delay does come from wires, but power loss (I^R) in wires is still negligible. Switching and leakage currents dominate. We still neglect I^R power except for it's impact on voltage drop and signal integrity, which has absolutely nothing to do with power.
Yeah, I read the press release. But who pissed in your cornflakes this morning?
I do understand it. It does happen every few years. I did not say it happens by itself. Nor did I imply it. And my statment was not intended to detract from the work involved in process shrinks.
Your silly ad hominem attacks ("must be new to technology") do nothing to support your confused viewpoint and fascination with this press release.
From the sounds of the press release, Intel is far ahead of its competitors when it comes to 65nm.
Maybe you're new to press releases? Because that's what they all try to do -- imply that they've done something amazingly new, whether or not it's necessarily true.
"The competition" is not "just scratching the surface" of 65nm. NEC has had their 65nm fab up as long as Intel, and is producing similar-perfomance parts. TSMC and IBM as well. Just because AMD hasn't put out 65nm parts doesn't mean IBM can't. IBM can, and does.
Not only do you need to do more research and understanding the market more, you need to calm down and learn some manners.
There are three components to leakage current in DSM CMOS devices. From here in order of magnitude: (1) source-drain junction leakage current (2) gate-direct tunneling leakage, and (3) sub-threshold leakage current.
And while neither of us pointed out all three, the fact remains that it's not the "bunching up" of the transistors that increases leakage, it's the gate and transistor sizes (which tend to scale together.) Which was the point I was trying to make.
If you think gate leakage is negligible compared to sub-threshold leakage, you'd better tell the IEEE and all those people working on high-K gate dielectrics.
With all due respect, I think you're confused. For the same operating voltage, dynamic power does not decrease with decreasing gate size/transitor size.
P=1/2*Ceff*V^2*f*N+Q*V*f*N+I1*V
where P is power consumption, Ceff is effective load capacitance, f is frequency, V is source voltage, N is signal switching coefficient, Q is charge due to through-type current, and I1 is leakage current.
While the actual gate capacitance driven may be reduced by virtue of it's smaller size, the effective capacitance (that "seen" by the driver) stays roughly the same, or may even get higher from parasitic capacitance.
The only thing sure to change is the leakage current, which will increase as gates shrink.
Your post is accurate and informative in general, but there's one nit I must pick:
But as a rule of thumb, the closer you bunch up the transistors, the higher the electrical leakage.
It's not the bunching up (density) of the transistors that increases leakage current (static power consumption,) it's the gate size. Narrower gates are less good at being the perfect insulators they should be. The thinner dielectric allows more leakage current, and can even break completely if the voltage is too high, which is why smaller-geometry processes often allow (or require) lower operating voltages, which helps reduce synamic (switching) power.
Of course, it's the shrinking of the gates (and the rest of the transistors) that allows them to be bumched up more (placed in higher density,) so maybe you meant it that way . . .
How do you figure that? You seem to be assuming that operating voltage also drops 30%, which I didn't see anywhere in the article.
That is to say: power is not related to gate size except that smaller gates may allow lower voltage (which affects power in a good way) and smaller gates have much higher leakage current (which affects power in a bad way.)
Just dropping the gate without also dropping operating voltage actually increases power, since dynamic power stays the same and leakage (static) power increases.
And just because gates are smaller doesn't mean voltage can be lowered. There's a lot more to it than that.
"Reduced transistor size by 30%" is an odd way to announce moving from a 90nm to a 65nm process.
Just to help avoid any confusion here, this is not some new clever transistor design or something. It's just another incremental step in process size reduction. It happens every few years. And it's not just Intel -- I know IBM and NEC are doing 65nm right now as well. I suspect TSMC and UMC are also, though I'm not sure (I know UMC had problems in 90nm that they're still fighting with . . )
Smaller transistors generally require less power to operate because they can (actually, must) be operated at a lower voltage. Dynamic (swtiching) power varies with the square of the voltage, so dropping the voltage a little makes the power go down a lot.
But that's just switching power.
As gate sizes shrink, previously negligible leakage (static) power increases. A lot. Now it's no longer negligible at the 90nm and 65nm process steps. In fact, it's getting very close to the same order of magnitude as switching power.
That's a problem because you can limit dynamic power by switching more slowly, or not switching certain transistors at all (think mobile CPU speed throttling.) But leakage power is consumed even if the CPU clock isn't ticking. If voltage is applied to the chip, power leaks.
Good points there. There is, however, one other very important reason why the DNC apparently wasn't protested as much as the RNC, perhaps the most important reason:
Democrats kept protestors in a cage called the "Free-Speech Zone" during the DNC. The RNC isn't limiting free speech to a cage.
Republicans were allowed no such convenience since anti-Republican protestors claimed a law prohibits such caging of dissenters. I bet they'd use it if they could. Having all your vocal opposition locked up in a barbed wire cage makes it much less of an annoyance.
Interestingly, google searches of both the web and the news didn't provide any immediate proof that the RNC can't use the cages, or that DNC organizers apparently violated the law that prevents the RNC from using cages. This is the only reference to the issue I found, and it leaves out a lot of info, but it's worth a read. And, anyone in NYC can confirm that, indeed, there are no cages in use as there were at the DNC. At the RNC protesters mostly go wherever they want except for some excluded areas, where at the DNC protestors had to stay in a small caged area. A "free speech zone."
Moreover, the relative ugliness and chaos of the RNC protestors are helping Bush get re-elected, IMHO. When footage of what the "anti-Bush" nuts are shown on the nightly news in middle America, those swing states are more likely to go Bush because they tend to value niceness and fear chaos. Of course, we know the stuff that will be shown don't represent the majority of the anti-Bush people, but when Ma and Pa Jones see the clip I saw last night of the guy holding the Kerry sign punch the Bush-sign guy in the face, they're going to associate Kerry with these nuts, and it will hurt him in the campaign.
So maybe the RNC is glad they're not allowed to cage protestors, so the protestors can run wild and the wildest of them will be on the news holding a Kerry sign while acting like a nincompoop. Hmmm, are they that smart?
Moreover, the only sort of person who could describe Google's changing of a free beta tool's interface as "cracking down" is someone who has never himself been cracked-down upon.
This isn't "cracking down." But at least it wasn't an YRO story.
If google's free gmail broke your favorite notifier plugin and that really upsets you, then you're taking free email far too seriously.
Are you kidding, or did you not even read the first link?:
Recently there was a post made on the HL2 Fallout Forums under Gabe Newell's account claiming that Half-Life 2 would be going gold on Monday. This post has been confirmed a hoax. An anonymous imposter guessed Gabe's password, "gaben", and made the false claim. Valve has confirmed that this is was a hoax on the Steam Forums.
Here are the full details straight from Mr Bond:
Update: After one crazy night of theories, server mayhem and IP tracing, we've finally gotten to the bottom of this mess. In a twist of hilarity, it seems that Gabe Newell's account password was set to 'gaben'. Person x guessed this and made the "going gold on Monday" post which we've heard so much about. The user (who we believe is the same person x) then made this post just minutes ago using Gabe's account [announcing that he guessed Gabe's pass as "gaben"]
After a quick double-check, it seems that this was exactly what happened. Reminds me of the good old days. For an official response concerning the hoax, see Chris Bokitch's post on Steampowered.
I think Gabe is going to need to start using slightly better passwords on accounts he uses to make public announcements on.
You're so close it's scary. It was five digits, which might be ok, were it not "gaben." Right. His first name and last initial. All lowercase. The guy doesn't learn after getting haxored?
From here:
An anonymous imposter guessed Gabe's password, "gaben", and made the false claim. Valve has confirmed that this is was a hoax on the Steam Forums.
Update: After one crazy night of theories, server mayhem and IP tracing, we've finally gotten to the bottom of this mess. In a twist of hilarity, it seems that Gabe Newell's account password was set to 'gaben'. Person x guessed this and made the "going gold on Monday" post which we've heard so much about. The user (who we believe is the same person x) then made this post just minutes ago using Gabe's account [announcing that he guessed Gabe's pass as "gaben"]
After a quick double-check, it seems that this was exactly what happened. Reminds me of the good old days. For an official response concerning the hoax, see Chris Bokitch's post on Steampowered.
I think Gabe is going to need to start using slightly better passwords on accounts he uses to make public announcements on.
Since your comment achieved +4 Insightful, I'm a bit hesistant to post this, but go ahead and mod me down if you have to because this must be said:
An economic policy based on whether or not YOU (or any one person) personally have (has) a job is certain to be worse for most people in the long run than one designed for the greater good.
I hear what you're saying, but if you would just re-read the argument while trying to avoid attaching any emotion or personalization to it you'll see that it is not at all complicated (though a bit complex) and obviously correct. I realize that's somewhat like hearing that the last available liver transplant was given to the guy right above you on the list, but it's reality.
Unfortunately, "YOU" just fell on the wrong side of the line here. Jobless or not, it's impossible to make a system under which everyone does well. The goal to encourage competition and improvement and to maximize the product of the number of people doing well and how well they do. The goal is not to maximize the number of people doing well irrespective of how well "well" is, because though it may sound "more fair," it doesn't at all encourage competition or growth.
It'g good for "YOU" (read: under-/un-employed) in the short term. Very bad for almost everyone else in the long run.
I hope that makes sense to you; it's very important!
I'll second that, and humbly ask permission to use your fine letter as a basis for (or possibly in toto as-is) my own response to such asshattery, should I ever need it.
Maybe, depending on what your CPUs are doing (one thread split between CPUs sharing all data, two threads sharing some data, or two totally independent threads with no common data, or something in between those three points.)
But he asked why two cores on one die might be desirable over two cores on seperate dice with some interconnect in between. And I answered;)
Interconnect delay (latency) is reduced. Signals propagate traces on a die (silicon chip) are orders-of-magnitude faster than printed-circuit board (PCB) traces.
That means you can get more bandwidth with silicon than a circuit board (each of reasonable size using modern components/processes.)
Also, it takes a lot less power to run lower-voltage drivers on low loads (little resistance and capactiance on die compared to a PCB.)
So, why not stack everything on onw chip? Cost of a chip rises exponentially with die size. Up to about 20mm^2, it's feasible (but pricy) bigger dice are very hard to make, result in lower yields, and hence cost a lot more.
No, most user's don't need to be root most of the time. Yet:
While we are not aware of any malware exploiting this, we think it will only be a matter of time. The one mitigating factor that we found is that to change the WMI, and spoof the Security Center, the script has to be running in Administrator mode. If executed in Windows XP's Limited Mode, it will give an error, and not allow changes. Unfortunately, most home users who will be at risk, run in the default administrator mode.
How can we convince people not to run admin mode? It's easy at work, in UNIX land (most people don't get to know root pw.) But most Windows users I know don't even know the difference.
Every windows security problem I know of can be solved, or at least significanly mitigated, by users not running root.
Slashdot Mirror
Ceffecive is a measure of all the capacitance that will be charged/discharged by the switching. It appears in the equation for dynamic (switching) power. Call it what you will, but this is how we determine dynamic power.
I do enjoy being corrected when wrong, but I'm going to have to ask you for some more reliable source than yourself on this one before I can have the joy. Here are some points for you to ponder while you google for something to back up your claim:
Capacitance varies with gate area and inversely with distance between "plates" of the gate (C = k*A / d). Reducing the gate width (space between the plates) actually increases capacitance, and this itself would increase power. But, you're also able to reduce the gate area (though not as much, but in 2-dimensions, so shrinking gates is usually a slight reduction in C). But, if the (dominant) interconnect capacitance (see next point) requires a larger transistor to drive it (which will be the case if voltage is not reduced) then the Area of the gate will increase, and so the capacitance will be right back up to where it was before you shrank the process.
According to Intel, "transitor loads are comprised of >50% interconnect capactiance." Wiring capacitance does not necessarily decrease with process shrinks (and may even increase significantly from cross-capacitance, depending on wire pitch and spacing.)
Most importantly, but probably too complex for this discussion, is the fast that gate capacitance depends strongly on voltage. This relationship is not well understood or investigated other than empirically.
Of course, the simplest way to show you that you're mistaken would be to send you some excerpts from process manuals showing that the capacitances do not drop with simple process shrinks in most cases, but that would probably get me fired.
Nobody said anyone was shipping 65nm parts, Mr. Irate. I said NEC and IBM put out 65nm parts. I didn't say they were on the shelves at the store yet.
Just like Intel is doing (internally sampling memory chips at 65nm to test and improve the process,) other manufacturers are using their 65nm fabs to make 65nm parts.
You can't buy anything in 65nm yet, but that doesn't mean they're not being made.
Please consider decaf.
From TFA:
;)
"The iPod group is looking for a Hardware Engineer. This person will be an individual contributor on a top notch team with responsibilities for the design, implementation, and integration of digital and analog electronics. Experience in the following areas is important: system integration, digital logic, SDRAM, Flash, ASIC's, processor selection, ATAPI, various communication protocols (ie: GSM, Bluetooth, IEEE 802.11, Firewire, and USB), display types and video and analog integration."
Does this mean we are very likely to see an iPod with a video display and capable of sending and receiving music via WiFi? This is very likely.
What strange language the author uses there. Is he answering his own question about whether it's very likely by saying yes, it's very likely? Or is he saying that it's very likely that it's "very likely?"
I think it's very likely that I'm confused
Thanks for the correct, but entirely unrelated comment about interconnect delay. ;)
We were talking about power. Or at least I was, and though you were too, given your incorrect claim that "Of cause [sic] if you drop the dimention the power consumption decreases."
And, BTW, most delay does come from wires, but power loss (I^R) in wires is still negligible. Switching and leakage currents dominate. We still neglect I^R power except for it's impact on voltage drop and signal integrity, which has absolutely nothing to do with power.
Yeah, I read the press release. But who pissed in your cornflakes this morning?
I do understand it. It does happen every few years. I did not say it happens by itself. Nor did I imply it. And my statment was not intended to detract from the work involved in process shrinks.
Your silly ad hominem attacks ("must be new to technology") do nothing to support your confused viewpoint and fascination with this press release.
From the sounds of the press release, Intel is far ahead of its competitors when it comes to 65nm.
Maybe you're new to press releases? Because that's what they all try to do -- imply that they've done something amazingly new, whether or not it's necessarily true.
"The competition" is not "just scratching the surface" of 65nm. NEC has had their 65nm fab up as long as Intel, and is producing similar-perfomance parts. TSMC and IBM as well. Just because AMD hasn't put out 65nm parts doesn't mean IBM can't. IBM can, and does.
Not only do you need to do more research and understanding the market more, you need to calm down and learn some manners.
There are three components to leakage current in DSM CMOS devices. From here in order of magnitude: (1) source-drain junction leakage current (2) gate-direct tunneling leakage, and (3) sub-threshold leakage current.
And while neither of us pointed out all three, the fact remains that it's not the "bunching up" of the transistors that increases leakage, it's the gate and transistor sizes (which tend to scale together.) Which was the point I was trying to make.
If you think gate leakage is negligible compared to sub-threshold leakage, you'd better tell the IEEE and all those people working on high-K gate dielectrics.
With all due respect, I think you're confused. For the same operating voltage, dynamic power does not decrease with decreasing gate size/transitor size.
P=1/2*Ceff*V^2*f*N+Q*V*f*N+I1*V
where P is power consumption, Ceff is effective load capacitance, f is frequency, V is source voltage, N is signal switching coefficient, Q is charge due to through-type current, and I1 is leakage current.
While the actual gate capacitance driven may be reduced by virtue of it's smaller size, the effective capacitance (that "seen" by the driver) stays roughly the same, or may even get higher from parasitic capacitance. The only thing sure to change is the leakage current, which will increase as gates shrink.
Maybe this will help you understand.
Your post is accurate and informative in general, but there's one nit I must pick:
But as a rule of thumb, the closer you bunch up the transistors, the higher the electrical leakage.
It's not the bunching up (density) of the transistors that increases leakage current (static power consumption,) it's the gate size. Narrower gates are less good at being the perfect insulators they should be. The thinner dielectric allows more leakage current, and can even break completely if the voltage is too high, which is why smaller-geometry processes often allow (or require) lower operating voltages, which helps reduce synamic (switching) power.
Of course, it's the shrinking of the gates (and the rest of the transistors) that allows them to be bumched up more (placed in higher density,) so maybe you meant it that way . . .
How do you figure that? You seem to be assuming that operating voltage also drops 30%, which I didn't see anywhere in the article.
That is to say: power is not related to gate size except that smaller gates may allow lower voltage (which affects power in a good way) and smaller gates have much higher leakage current (which affects power in a bad way.)
Just dropping the gate without also dropping operating voltage actually increases power, since dynamic power stays the same and leakage (static) power increases.
And just because gates are smaller doesn't mean voltage can be lowered. There's a lot more to it than that.
"Reduced transistor size by 30%" is an odd way to announce moving from a 90nm to a 65nm process.
Just to help avoid any confusion here, this is not some new clever transistor design or something. It's just another incremental step in process size reduction. It happens every few years. And it's not just Intel -- I know IBM and NEC are doing 65nm right now as well. I suspect TSMC and UMC are also, though I'm not sure (I know UMC had problems in 90nm that they're still fighting with . . )
Well, sorta.
Smaller transistors generally require less power to operate because they can (actually, must) be operated at a lower voltage. Dynamic (swtiching) power varies with the square of the voltage, so dropping the voltage a little makes the power go down a lot.
But that's just switching power.
As gate sizes shrink, previously negligible leakage (static) power increases. A lot. Now it's no longer negligible at the 90nm and 65nm process steps. In fact, it's getting very close to the same order of magnitude as switching power.
That's a problem because you can limit dynamic power by switching more slowly, or not switching certain transistors at all (think mobile CPU speed throttling.) But leakage power is consumed even if the CPU clock isn't ticking. If voltage is applied to the chip, power leaks.
Good points there. There is, however, one other very important reason why the DNC apparently wasn't protested as much as the RNC, perhaps the most important reason:
Democrats kept protestors in a cage called the "Free-Speech Zone" during the DNC. The RNC isn't limiting free speech to a cage.
Republicans were allowed no such convenience since anti-Republican protestors claimed a law prohibits such caging of dissenters. I bet they'd use it if they could. Having all your vocal opposition locked up in a barbed wire cage makes it much less of an annoyance.
Interestingly, google searches of both the web and the news didn't provide any immediate proof that the RNC can't use the cages, or that DNC organizers apparently violated the law that prevents the RNC from using cages. This is the only reference to the issue I found, and it leaves out a lot of info, but it's worth a read. And, anyone in NYC can confirm that, indeed, there are no cages in use as there were at the DNC. At the RNC protesters mostly go wherever they want except for some excluded areas, where at the DNC protestors had to stay in a small caged area. A "free speech zone."
Moreover, the relative ugliness and chaos of the RNC protestors are helping Bush get re-elected, IMHO. When footage of what the "anti-Bush" nuts are shown on the nightly news in middle America, those swing states are more likely to go Bush because they tend to value niceness and fear chaos. Of course, we know the stuff that will be shown don't represent the majority of the anti-Bush people, but when Ma and Pa Jones see the clip I saw last night of the guy holding the Kerry sign punch the Bush-sign guy in the face, they're going to associate Kerry with these nuts, and it will hurt him in the campaign.
So maybe the RNC is glad they're not allowed to cage protestors, so the protestors can run wild and the wildest of them will be on the news holding a Kerry sign while acting like a nincompoop. Hmmm, are they that smart?
Slashdotted at 7 posts. I think they underestimated the interest in free (as in both gratis and libre) games.
You are correct.
Moreover, the only sort of person who could describe Google's changing of a free beta tool's interface as "cracking down" is someone who has never himself been cracked-down upon.
This isn't "cracking down." But at least it wasn't an YRO story.
If google's free gmail broke your favorite notifier plugin and that really upsets you, then you're taking free email far too seriously.
Are you kidding, or did you not even read the first link?:
Recently there was a post made on the HL2 Fallout Forums under Gabe Newell's account claiming that Half-Life 2 would be going gold on Monday. This post has been confirmed a hoax. An anonymous imposter guessed Gabe's password, "gaben", and made the false claim. Valve has confirmed that this is was a hoax on the Steam Forums.
Here are the full details straight from Mr Bond: Update: After one crazy night of theories, server mayhem and IP tracing, we've finally gotten to the bottom of this mess. In a twist of hilarity, it seems that Gabe Newell's account password was set to 'gaben'. Person x guessed this and made the "going gold on Monday" post which we've heard so much about. The user (who we believe is the same person x) then made this post just minutes ago using Gabe's account [announcing that he guessed Gabe's pass as "gaben"]
After a quick double-check, it seems that this was exactly what happened. Reminds me of the good old days. For an official response concerning the hoax, see Chris Bokitch's post on Steampowered. I think Gabe is going to need to start using slightly better passwords on accounts he uses to make public announcements on.
You're so close it's scary. It was five digits, which might be ok, were it not "gaben." Right. His first name and last initial. All lowercase. The guy doesn't learn after getting haxored? From here:
An anonymous imposter guessed Gabe's password, "gaben", and made the false claim. Valve has confirmed that this is was a hoax on the Steam Forums.
Update: After one crazy night of theories, server mayhem and IP tracing, we've finally gotten to the bottom of this mess. In a twist of hilarity, it seems that Gabe Newell's account password was set to 'gaben'. Person x guessed this and made the "going gold on Monday" post which we've heard so much about. The user (who we believe is the same person x) then made this post just minutes ago using Gabe's account [announcing that he guessed Gabe's pass as "gaben"]
After a quick double-check, it seems that this was exactly what happened. Reminds me of the good old days. For an official response concerning the hoax, see Chris Bokitch's post on Steampowered. I think Gabe is going to need to start using slightly better passwords on accounts he uses to make public announcements on.
Since your comment achieved +4 Insightful, I'm a bit hesistant to post this, but go ahead and mod me down if you have to because this must be said:
An economic policy based on whether or not YOU (or any one person) personally have (has) a job is certain to be worse for most people in the long run than one designed for the greater good.
I hear what you're saying, but if you would just re-read the argument while trying to avoid attaching any emotion or personalization to it you'll see that it is not at all complicated (though a bit complex) and obviously correct. I realize that's somewhat like hearing that the last available liver transplant was given to the guy right above you on the list, but it's reality.
Unfortunately, "YOU" just fell on the wrong side of the line here. Jobless or not, it's impossible to make a system under which everyone does well. The goal to encourage competition and improvement and to maximize the product of the number of people doing well and how well they do. The goal is not to maximize the number of people doing well irrespective of how well "well" is, because though it may sound "more fair," it doesn't at all encourage competition or growth.
It'g good for "YOU" (read: under-/un-employed) in the short term. Very bad for almost everyone else in the long run.
I hope that makes sense to you; it's very important!
I don't get it either. I suspect that it is not prose that we seek in vain to comprehend, but in fact poetry of some kind.
;)
What about the RIAA will become more "loose," or perhaps even more ominously, what the RIAA will let "loose" upon us, is not clear.
But I'm pretty scared anyway.
I'll second that, and humbly ask permission to use your fine letter as a basis for (or possibly in toto as-is) my own response to such asshattery, should I ever need it.
Maybe, depending on what your CPUs are doing (one thread split between CPUs sharing all data, two threads sharing some data, or two totally independent threads with no common data, or something in between those three points.)
;)
But he asked why two cores on one die might be desirable over two cores on seperate dice with some interconnect in between. And I answered
You're exactly right. Sorry, I meant 20mm x 20mm, or 400mm^2.
Interconnect delay (latency) is reduced. Signals propagate traces on a die (silicon chip) are orders-of-magnitude faster than printed-circuit board (PCB) traces.
That means you can get more bandwidth with silicon than a circuit board (each of reasonable size using modern components/processes.)
Also, it takes a lot less power to run lower-voltage drivers on low loads (little resistance and capactiance on die compared to a PCB.)
So, why not stack everything on onw chip? Cost of a chip rises exponentially with die size. Up to about 20mm^2, it's feasible (but pricy) bigger dice are very hard to make, result in lower yields, and hence cost a lot more.
No, most user's don't need to be root most of the time. Yet:
While we are not aware of any malware exploiting this, we think it will only be a matter of time. The one mitigating factor that we found is that to change the WMI, and spoof the Security Center, the script has to be running in Administrator mode. If executed in Windows XP's Limited Mode, it will give an error, and not allow changes. Unfortunately, most home users who will be at risk, run in the default administrator mode.
How can we convince people not to run admin mode? It's easy at work, in UNIX land (most people don't get to know root pw.) But most Windows users I know don't even know the difference.
Every windows security problem I know of can be solved, or at least significanly mitigated, by users not running root.
You're on to something.
And you really need a group hug.
Seriously -- you'll love it (if you haven't seen it.)
Pick yer platform
;)
Stand-alone player sans computer, please.
YOu seem to have left out that link.