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Intel Shrinks Transistor Size By 30%
pinkUZI writes "Intel will announce that it has crammed 500 million transistors on to a single memory chip, shrinking them in size by 30%. " The tech details are sadly lacking in the article - but I'm sure those will follow. Indeed, the Yahoo piece gives the details that "...has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers."
Increase their penis size spam...
Oh, yea right "the size of your transistor doesn't matter"... that's what they all say, but they don't mean it.
Alito: A vote for Alito is a punch in the eye to put that bitch back in her place!
In related news, Intel stated that this new manufacturing process will help their processors more effectively compete with charcoal on a heat density versus cost basis.
Life is the leading cause of death in America.
I'm waiting for Intel to reduce heat output by 30%. 130 watts for a top end P4 is pretty insane, when a top end Opteron is only 100 watts. I don't care how small it is.
He who laughs last is stuck in a time dilation bubble.
it is not the size of the chip she cares about....it is the number of transistors you have.
I submitted this correction to the editor in advance... i guess they don't read their email in time.
Will this be incorporated into the new Unobtainium chip?
~S
Yes, Moore is less - or smaller you could say.
...they've found a way to get rid of the base, collector, or emitter. Unfortunately, these new transistors can only store zeros.
I dont get it.
70Megabit ~= 10 Mbyte. Thats not that big.
Also this would mean each bit uses 14 transistors. I think they mean megabyte and each bit uses ~2 transistors.
Mouse powered Chips, Open source Processors and Lego
Decreasing size is great, sure, but I'm sure any processor built with this process would be at least as hot, if not hotter than a current chip.
...selling methods for reducing the size of our transistors?
Sheesh, evil *and* a jerk. -- Jade
I work for Intel, and I gotta say--we do this every couple of years, and this wasn't a particularly stunning or unexpected part of our roadmap. If you wanted a more sensationalist headline for a pretty expected bit of news you might try the old "Intel Proves Moore's Law Not Dead Yet"
"The tech details are sadly lacking in the article - but I'm those will follow." :P
At least that is one way to reduce typos by slashdot editors, just start leaving out entire words.
Heh, if they don't read their own website, what makes you think they'll read their email about their website? :-(
But you need several inconveniently large buildings to house the cooling system...
Curiosity was framed. Ignorance killed the cat.
This sounds like a great way to tackle heat and power problems with laptops (and PCs, it's not like modern PCs don't have heating trouble too). I'd lay a bet though, that it'll still run hotter than the P4s, it seems there should be an addenium to Moores law.
Okay, that's enough posting for Hemos Today, or atleast leave your ego behind and make 'Im sure', sure, and not just You.
Moore predicted his Law would run out in 2012 when 1 billion transistors are fit on a chip. Looks like we're ahead of schedule.
Support the First Amendment. Read at -1
That's some progress!
If you never make mistakes, it's probably because you're not doing anything.
I'm wondering if this just means they made a NEW transitor OR if they made existing transistor designs smaller and still keep their capibilities.
And the question is: why are them, in the one of the highest performance 32-bit chips nowadays, still preserving compatibility with 4-bit display controllers and why should we pay for compatibly with obsolete software? And don't you think that, for such a price, it would be easier to own 2 systems of different Intel architectures, a fast and a compatibe one?
As you may or may not know, the smaller they can make it the more transistors they can put on it, as a result, more speed is gained as said by Moores Law.
-Joey
From the article:
For its next generation chips, Intel said it incorporated new materials and other technologies to work around the problems.
Wow, what a helpful and descriptive statement. The quality of this article is disgusting. Why even post it?
This can't be any official sort of press release...nowhere do they measure the size of the transistors by how many it takes to equal the width of a human hair!
You're thinking DRAM, with one transister per bit, but slow (plus it needs refreshing every 60msec or so). Static RAM is mucho faster, with 4 to 8 transistors per bit.
Also, your math is in error. 500M transistors for 70 Mbits works out to 7 transistors per bit. I'm guessing the visible portion of the chip will be 64Mbits and 6 transistors/bit, with most the rest of the transistors allocated as spares. When you make a chip that big, you can boost yield by making spare blocks of memory that during manufacturing can be substituted for bad areas on the chip.
--- Often in error; never in doubt!
I remember reading this SciFi book where there is a computer that has three fat tubes sticking out: the first one is for power, the second for icecubes(in) and the last for steam(out).
10 ?"Hello World" life was simple then
They could just say "Clock gating".
What makes a non-technical journalist think "Clockgate" isn't just another White House scandal like Watergate, Flowergate, Whitewatergate, Cattlegate, Travelgate, Filegate, and Zippergate?
Well, I already use my G5 to heat my room and it's more than efficient at this (amongst other tasks of course :) ).
With the switches this small, is it safe to say that they are using nanotechnology? I know it's not the cool molecule-sized-killer-robot style nanotech but this seems to fit the description of devices on the scale of a nanometer.
Blaze a trail to the New World
Yeah, but you don't have that nice heat sink that also doubles as a grill grate for those professional chef-type grill marks. Mmmm....
If you never make mistakes, it's probably because you're not doing anything.
"Reduced transistor size by 30%" is an odd way to announce moving from a 90nm to a 65nm process.
Just to help avoid any confusion here, this is not some new clever transistor design or something. It's just another incremental step in process size reduction. It happens every few years. And it's not just Intel -- I know IBM and NEC are doing 65nm right now as well. I suspect TSMC and UMC are also, though I'm not sure (I know UMC had problems in 90nm that they're still fighting with . . )
everything in moderation
Yes, Moore is less - or smaller you could say.
Can't we all wish Moore was less?
Get your Unix fortune now!
You're correct. Intel commonly uses a 6T cell structure for the SRAMs they use as process testing chips. They used to use DRAMs as a process driver up until the mid-1980s, but then switched to SRAMs after they left the DRAM business. Since most CPUs today are half SRAM (cache) anyway, this makes sense.
I submitted this earlier, but was rejected.
Anyway, here is the offical press release from Intel's website.
In C++, friends can touch each others private parts.
when are they going to start more aggressively perusing other options as opposed to transistors. I do recall hearing Intel was in the process of researching the use of light processors, but haven't heard anything since. Electrons move at about 3cm/s light moves at 3.0x10^08m/s: do the math. A wall will be hit with electricity (no matter how long it takes). Why not think in leaps not baby steps? Personally I could live with 3GHz processing speeds for a few years if that meant that the next step up would be say 10GHz.
A thirty-two bit extension and graphical shell to a sixteen-bit patch to an eight-bit operating system originally coded for a four-bit microprocessor which was written by a two-bit company that can't stand one bit of competition.
Did they announce it? Or is Miss Cleo now employed by /.?
Woops. Yeah youre right.
I just have the 1billion number in my head. My research group leader keeps going on about 1 billion transistor chips and how we can waste^H^H^H^H^H use them. He says neural nets. I say multiprocessors grids.
Mouse powered Chips, Open source Processors and Lego
The actual Intel press release claims that:
"Intel's leading strained silicon technology, first implemented in its 90nm process technology, is further enhanced in the 65nm technology. The second generation of Intel strained silicon increases transistor performance by 10 to 15 percent without increasing leakage. Conversely, these transistors can cut leakage by four times at constant performance compared to 90nm transistors. As a result, the transistors on Intel's 65nm process have improved performance without significant increase in leakage (greater electrical current leakage results in greater heat generation)."
Seriously, I mean advancments in shrinking are good, but wouldn't it make more sense to increase the cpu size (maybe double it). As is, it only takes up a 1 inch space on my motherboard, lets take up 3 or 4 inches. Would it be too hard to cool something that large? I would think by increasing the size we could make more powerful processesors with the same level of technology.
Tomorrow intel will announce it's achieved tempuratures greater than Sun (fire ball in middle of solar system, not server company).
Intel's product line will include an alternative to the popular "George Foreman Grill". Intel's grill, powered by the PIV processor will grill a "Big George" style hamburger in under 30ns.
Microsoft is expected to make an announcement in coming weeks to annouce it plans to dominate the college cookware industry by selling inferior products at lower costs with Hamburger DRM.
May I ask why, every time they shrink the size of components, they feel a need to put more on the chip? I realize more can be done, but with all the heat/power problems with increased density, why not use the space with chip power you already have? The result would be a cooler, lower power device.
Ad Astra Per Asper
The limit of quantum interference will soon be reached below of which no more close packing will be possible since the transistors will not be able to function properly. The electrons will choose to develop superpositions of states (of 1 and 0) with unpredictable results.
Well a fundamental new design has to be implemented, and I guess that's where quantum computing steps in...
Yam, yam, uga booga, yam, yam, yade, yade, uga booga, yam, yam, yade, yade
Umm... if they will announce it, would we be even discussing this now? Somewhere someone at Intel has to have announced this by now...
my sig was dubm so i took it out.
The tech details are sadly lacking in the article - but I'm those will follow
Insert a "sure" between "I'm" and "Those."
You create your own reality - Leave mine to me.
70 megabit = 8.75 megabyte (google)
does this neccessarily mean we are going to get larger capacities of chips ? or does it mean we can run our memory busses faster?
Nick...
Electronic Music Made Using Linux http://soundcloud.com/polyp
Memory chips can get really hot! I have a Athlon 2800+ system at home and I use 2 modules of 512MB Kingston HyperX SDRAM (yeah, those that come with a stylish blue heatsink) in it. Recently, I measured the temperature of various system components and was quite surprized that the hottest parts under heavey loads where actually these SDRAM modules! With a 2,2,2,5 timing I could measure 57C!
There was an article on this case/heat sink on /. a few days/weeks ago. While I think it comes with a 2.8 p4 you could upgrade if you like meat well done.
http://www.logicsupply.com/
# Try to reply to other people's comments instead of starting new threads.
You started a NEW THREAD to tell us this. Hypocrite !!
Score & Karma: SASA: Slashdot Approval Seekers Anonymous
First a story on /. about better lubricated, faster hard drives. Then another story about shinking chips. Is Cmdr Taco trying to give me a complex?
Well, there's spam egg sausage and spam, that's not got much spam in it.
You zee, ferst we take ze reduced size transeestors, and then we use thm in ze new dual core processorz so that even though you zink the procezzor will be smaller - pop - ze prozezzor weeel be bigger and e'more cumbersome and eexpanzive zan before, ja..
Being a computer engineer, I'm quite familiar with Moore's law, it's the reason I continue to find open jobs. Since when did Moore say "doubles every two years"?!? It is "doubles every 18 months" you incompetent journalist!!
</flame>
The Widget
It's not the size of the chip, it's the motion of the FLOPS. This especially negates the Clock Speed myth, after all who want's someone that completes a cycle in 1/100000000 of a second?
retarded... I like that word ;)
has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers
I hope they mean 70,000,000 bits like they're saying...
Remember folks... the 1024 doesn't apply to bits...
Reuters has more detail on the whole process, and how this will help not only in memory, quoting:
"In a bit of semiconductor showmanship, Bohr said Intel had manufactured a memory chip with more than a half-billion transistors using its new 65-nanometer manufacturing process, which was developed at its site in Hillsboro, Oregon. "
First of all, they were talking about memory modules there. The more transistors you can fit on them, the bigger memory modules will be. With 64bit computing on the horizon it's about time they increased module sizes and made 2G and 4G modules as common as 512M and 1G are today.
Second of all, you don't have to put more stuff on the chip. They just say they now can do it. They also can make smaller chips doing the same thing which means better yield and less cost.
smaller = faster
I managed to fit 30% more beer in my stomach last night... Latrobe Brewery predicts higher earnings for the 3rd quarter 2004
is one thing. Producing it on the Production Line is another.
This is why there are Chemical Engineers, as opposed to Chemists. Or Mechanical Engineers, as opposed to Physicists. You can produce a single one at a cost of $10,000 in the lab, and that is an achievement.
But there's another step, and it very quickly leaves the realm of a controlled environment...
pause
Wait, did you say "nanometers"?
mumble "hair diameter - about 80 micro meters"
If you read further on ASML, you would know that the 65nm platform has been well on the market since early 2003. Even the process leader (i.e. Intel) has not delivered a 65nm based product. But they are among the closest, actually demonstrating a functional part as per their press release.
Long after the equipment is available, companies must demonstrate a process, fund, build, and equip extremely expensive fabrication facilities, and finally tune a process that has a profitable yield. The lithography equipment availability is only a small early step you need to realize.
Contrary to your implication, ASML have not yet delivered their 45nm lithography platform. Your link above points to a 65nm lithography page. Note the lead time for 65nm I described above, the many technological hurdles that 65 must clear before appearing in actual silicon on the market, and you will understand that 45nm is still several years additionally further away.
Really, you sound desperate to dismiss Intel's market leadership, when really I think it is exciting that we will again see smaller cheaper memory technology in the next few years. Especially when you notice that 240-pin DDR2 PC2-5300 RAM is still close to $200.
Just look at how well the 486 add-on card and SoftPC for the Mac did on the market! Look how many people bought the Chameleon with it's dual x86/z80 architecture! Unfortunately, non-backwards compatible architectures just don't sell.
"Freedom means freedom for everybody" -- Dick Cheney
Ha, Intel is not the only one. There are at least 3 other fabs/companies, if not more, that have memories 50% smaller than the previous node. Moore's law is not dead, and we do not need Intel to proove that...
Holy cow!!! I bet someday we'll be able to carry a radio in our shirt pocket.
C-effective is a timing construct only, you reach your 50% switching point at different times for the same circuit with different topology. Rather than design for the worst-case Cap, you do timing for the Ceff of the load network.
However, the device STILL switches full rail, which means ALL of the capacitance is charged.
So to correct you, dynamic power absolutely goes down as a result of shrinkng the device, becasue both diffusion and gate cap shrink.
Leakage power is another story alltogether, and it actually gets worse as the channel shrinks, but the process doping and layout rules and can offset some of this.
https://www.accountkiller.com/removal-requested
Carver Mead would say Moore's Law is at an end.
If X is the new Y, and Y is "X is the new Y", solve for X.
The article doesn't mention the speed. However if you reduce the feature size sqrt(2) and maintain the same voltage (questionable), you double the speed.
Intel shrinks the number of commands of the x86 architecture by 30% thus resulting in less heat and a global saving of energy of multiple gigawatts per month.
Suppose we try to achieve high switching speed as well as low leakage.
Consider a design where transistors and circuits shrink when under load in order to switch faster but enlarge at idle time for leakage reduction.
Consider another design where a computer system contains multiple CPUs where the load is shifted with a heat balance scheme. Hot CPUs are idled to cool them. CPUs can be run with very short duty cycles in order to minimize heating. This way extremely small logic circuits can be duplicated within a CPU but are not all turned on at the same time. The load can be moved from circuit to circuit. Switching speeds ought to be super fast.
Know your pads. One time pad: good for cryptography. Two timing pad: where to take your mistress.
I'm not fully understanding why 70Mbit is being treated like it is so dense. I mean we have 16 chip 512MB DDR nowadays don't we? That's 256Mbit and 256 > 70. Am I just missing some nuance or what?
Thanks.
(drool) 500 million transistors to crash in one big gooey, slimy, unstable critical mass of intel goodness .........
Ceffecive is a measure of all the capacitance that will be charged/discharged by the switching. It appears in the equation for dynamic (switching) power. Call it what you will, but this is how we determine dynamic power.
I do enjoy being corrected when wrong, but I'm going to have to ask you for some more reliable source than yourself on this one before I can have the joy. Here are some points for you to ponder while you google for something to back up your claim:
Capacitance varies with gate area and inversely with distance between "plates" of the gate (C = k*A / d). Reducing the gate width (space between the plates) actually increases capacitance, and this itself would increase power. But, you're also able to reduce the gate area (though not as much, but in 2-dimensions, so shrinking gates is usually a slight reduction in C). But, if the (dominant) interconnect capacitance (see next point) requires a larger transistor to drive it (which will be the case if voltage is not reduced) then the Area of the gate will increase, and so the capacitance will be right back up to where it was before you shrank the process.
According to Intel, "transitor loads are comprised of >50% interconnect capactiance." Wiring capacitance does not necessarily decrease with process shrinks (and may even increase significantly from cross-capacitance, depending on wire pitch and spacing.)
Most importantly, but probably too complex for this discussion, is the fast that gate capacitance depends strongly on voltage. This relationship is not well understood or investigated other than empirically.
Of course, the simplest way to show you that you're mistaken would be to send you some excerpts from process manuals showing that the capacitances do not drop with simple process shrinks in most cases, but that would probably get me fired.
everything in moderation
Ok, so they can shrink the transistors. Now you have to have your own commercial deep freeze to keep the chips cooled off LOL jk
The office assistant is an example of a great solution with an awful implementation. It is based on Bayesian operators, which are themselves a great idea, they filter my spam, for instance, and might be of great help in providing hints and tips for newbies. The problem was that marketing thought the clip didn't show up enough, so they made the horror that is Clippo.
But I don't believe Miguel is wrong when saying that is is a great idea. I have been the office assistant of many people that hate me now I'm not willing to do it anymore. It would be nice that a little program did wht they think is my job.
(Watts = Joules per second)
Jumping Gigawatts! Ever read Joules Vern?
(yeah, it was worth the karma)
Required reading for internet skeptics
Too bad you got modded up for misinformation. But hey, that's typical /. fashion.
Thanks for googling and regurgitating first year physics. You understand the equations, but know almost zilch about real world design, it is very obvious.
Now lets talk about the real-world design process.
I hate to repeat myself, but I'll try a little more slowly:
You have not once even attempted to define C-effecitve. C-ACTUAL is the lumped capacitve sum on the node (am I going to fast?). C-effective is the cap a driver sees and is defined as the capacitance that must be charged for the transisto t be out of the noise margin. Normally the upper and lower margin noise limits are 80%, but timing tools (are you familiar with what a timing tool is?) pick the 50% point because they don't consider which direction the transistion occurs.)
If you want to know what a timing tool is I can explain that too.
Now you can model Ceffective many ways, it depends entirely on the layout. The same lumped capacitance (excluding crosscap and MCF) can have many different Ceffectives depending on the layout.
Layout is when you actually draw the devices in the mask/metal layers, rather than a schematic. Devices have to placed somewhere, and the distance between them, and their legging, affects their capacitance (e.g. routing wire pitch and distance).
So we've covered C-effective. However, the charge required to COMPLETELY switch the rail is the C ACTUAL. This occurs during the remained of the clock cycle (assuming we aren't using pulsed logic).
This is what should be used for power.
By the way...
As the devices get smaller, they get closer, interconnect capacitance because a smaller contribution. On the latest intel processor, each one was roughly 33% of total lumped cap on a node, this is down from the p3 where interconnect was ~50%.
And like how you warn me that you might get fired! What a childish copout! You must be 16 or something! Stay in school, you seem to know a few basic things, maybe Intel will hire you some day.
https://www.accountkiller.com/removal-requested
I turned down Intel 8 over years ago. And last year again. I'm a staff-level ASIC designer with 8 years experience in physical design (including cell-based, COT, and full custom,) STA, signal integrity, and mixed signal/analog design. I know what a timing tools is. PrimeTime and NanoSim are my favorites. In contrast, your an angry child who likes arguing on the internet but can't support any of his claims.
I've tried to be nice and explain, with references, and you're still just harping on in your rude style about things you understand just enough about to be assertively mistaken. Despite my patient suffering of your obstinate, yet unsupported claims, you still haven't produced anything to back up your claim that "process shrinks necessarily provide power reduction."
No one is likely to waste much time trying to help a cocky brat like you understand how confused you are, at least I'm not going to waste any more of mine.
Try being nicer, you might learn something.
everything in moderation
Here you go little boy, run along and read this --
... But for the short-circuit component of power dissipation, the load "seen by the gate" affects the regious of operation of the transistors..."
1996 IEEE #0278-0070
"Performance Computation for Precharacterized CMOS Gates with RC Loads"
(If you really do work for a REAL semiconductor company, they should have this or it should be free access to you.)
Section V: Calculating Power Consumption, paragraph One:
"As mentioned previously, the charging/discharging component of the power dissipation is evaluated using the total net capacitance.
Ooooh, that burns, don't it!?
I know we didn't talk about the difference between switching and rush through, but you're still clueless.
https://www.accountkiller.com/removal-requested
The only way I'll let you off the hook is if you admin there is a difference between Ceffective and Ctotal.
If we're mixing up terms, that's understandable, but Ceff is ABSOLUTELY NOT C-Total (lumped, crosscap or MCF).
https://www.accountkiller.com/removal-requested
Listen kid: you're arguing with yourself.
Ceff vs. Ctotal is irrelevant unless you can show that Ctotal (or Ceff, doesn't matter which to my point!) is necessarily reduced by process shrink, and that this reduction is never offset by anything else, so that power consumption is guaranteed to drop if geometry is reduced.
That's the claim you made with which I disagreed. I still disagree. Your capacitance red herring doesn't help you with this unsupportable claim.
Neither does that 1996 IEEE paper.
I remember the fun and games of '96, ignoring signal integrity, "what's cross capacitance?," "why bother with 3d extraction . . . " I guess the relative simplicity of the 0.5um to 0.35um, or 0.35um to 0.25um shrink might yield to your simplistic claim -- though I doubt it -- I can't be sure since every process I know also dropped VDD at that node, which usually happens.)
But I'm holding out for something, anything, that supports your assertion that geometry reduction invariably reduces power, even if voltage is the same. Until such is provided you will ignored.
everything in moderation
I'm on no hook. But of course Ceff != Ctotal. I searched my posts and can't find an example of me claiming otherwise. In the process I also noticed that it wasn't you that said "Of cause [sic] if you drop the dimention [sic] the power consumption decreases" it was brejc8.
This was and is about power and whether or not the same circuit, at the same voltage, will necessarily consume less power.
Apparently you entered the conversation in the middle, and latched onto something (not sure what) I said that made you think I'm arguing about Ceff and Ctotal. I'm not.
everything in moderation
I don't normally do this, but, the parent really should be modded up, for many reasons.
And despite any tinge of Intel-fanboism your fanboiometer may indicate.
That "desperate" bit was just a well-deserved jab at the cluless grandparent. IMHO.
everything in moderation
"But I'm holding out for something, anything, that supports your assertion that geometry reduction invariably reduces power, even if voltage is the same. Until such is provided you will ignored."
Let me see if I understand correctly: you're telling me an optical shrink (screw process for now), has no impact on the diffusion capacitance of a CMOS device?
https://www.accountkiller.com/removal-requested
Nope. Read it again slowly.
:)
I'm looking for anything to backup the claim that geometry reduction invariably reduces power, even if the operating voltage is the same, regardless of wiring pitch or spacing, or any other possible factor.
If you'd just check the thread history without being angry, you'd see this is the only claim with which I've a problem.
Optical shrink has lots of effects. Some good, some bad. Mostly good. But it doesn't guarantee you a drop in total power dissipation for the same circuit at the same frequency.
Other factors also effect power. That's all I've been trying to say. And you keep arguing it, but only talkling about Ceff vs. Ctotal. Until now.
And I'm really spending too much time on it. As are you
everything in moderation
If you'd just check the thread history without being angry
.35 micron, and Deschutes was an optical shrink to .25 micron. Power went from 43 W to 18.6 W (see their Processor Spec Finder website). I have no idea what the leakage component of these guys was, so we can't scale perfectly.
s /L 07.pdf
s .a sp?sSpec=SL28R&ProcFam=47&PkgType=ALL&SysBusSpd=AL L&CorSpd=ALL
s /L 06.pdf
Apologies, my bad. I hear this from my wife once a week (just replace "thread history" with something else). Must be the Italian blood.
Ok, I'm beating a dead horse, but I'm doing it cheerfully (that didn't sound right). If you still are interested in talking about this, cool, if not, I don't blame you...
Problem statement --
An optical shrink within a certain limit reduces switching power invariably. Once you go 65nm, leakage skyrockets, so all bets are off... Lets just operating in the land of giants: 350-250 nm.
Example:
The 300 MHz PII (klamath) was
Note that with the shrink they could lower the voltage from 2.8V to 2.0V. Even assuming leakage scales with V squared (which it doesn't), that's still a 28% reduction in voltage, a 48% reduction in V^2 and a 56% reduction in power. And this is pessimistic due to leakage. Doesn't this imply that there is power loss as a direct result of shrinkage?
Analytically --
Both the gate and diffusion caps scale linearly with W if L remains constant, otherwise the caps scale with area (one dimension vs. both dimension shrink.)
Now, doesn't this automatically guarantee a drop in _switching_ power? Rush-through is more complicated so I don't have a clear answer. I've seen it get worse due to higher current in the linear region and bad project slopes. But I do know leakage gets WORSE as the devices get smaller, and this starts to offset the reduction due to scaling (partially due to channel width decrease, partially due to heavy doping).
In practice --
Downsizing. We use smaller devices on paths with positive margin. The result? Lower power.
So I think based on these three example it is possible to demonstrate that a pure optical shrink results in lower power at the same Vcc/Freq.
Anyway, it is late and I'm enjoying procrastinating too much.
-s
Links --
http://6371.lcs.mit.edu/currentsemester/handout
http://processorfinder.intel.com/scripts/detail
http://6371.lcs.mit.edu/currentsemester/handout
https://www.accountkiller.com/removal-requested
Thanks for apologizing for your bad attitude. Without that I wouldn't be replying. Your wife is right, BTW.
L 07.pdf = Intro to CMOS for the non-engineer. Little stick-man icons, replacing transistors with little switch symbols, and most importantly not a single mention of power comsumption.
a sp?sSpec=SL28R&ProcFam=47&PkgType=ALL&SysBusSpd=AL L&CorSpd=ALL - broken link even after fixing the slashdot mangling. I suspect it has to do with power consumption of specific cores. Which is irrelevant, see above.
L 06.pdf = more of the same, comic sans font, lots of stick men with question marks above their heads. I went to MIT -- this is the stuff they show journalism majors who are naieve enough to take intro to electronics for a science elective.
An optical shrink within a certain limit reduces switching power invariably . . . blah blah irrelevant blah . . . Doesn't this imply that there is power loss as a direct result of shrinkage?
Yes, but an example of a shrink, accompanied by a voltage drop, that reduced power in one case, even if you try to account for the voltage drop, does not show that a shrink implies a power reduction in all cases.
Analytically --
Both the gate and diffusion caps scale linearly with W if L remains constant, otherwise the caps scale with area (one dimension vs. both dimension shrink.) Now, doesn't this automatically guarantee a drop in _switching_ power?
L does not remain constant. W/L is the transistor gain. And you're ignoring the (dominant) wiring capacitance.
Rush-through is more complicated so I don't have a clear answer. I've seen it get worse due to higher current in the linear region and bad project slopes. But I do know leakage gets WORSE as the devices get smaller, and this starts to offset the reduction due to scaling (partially due to channel width decrease, partially due to heavy doping).
I think you're making this up as you go along. Or maybe you got your EE in another country or something. "project slopes?" "Linear region" operation for digital circuits? WTF?
In practice --
Downsizing. We use smaller devices on paths with positive margin. The result? Lower power.
So I think based on these three example it is possible to demonstrate that a pure optical shrink results in lower power at the same Vcc/Freq.
No, based on those three examples and your conclusion, we can only be sure that you need to re-take logic and/or proofs.
Oh, BTW. You accused me of "googling for 1st year circuits material" yet you spew:
http://6371.lcs.mit.edu/currentsemester/handouts/
http://processorfinder.intel.com/scripts/details.
http://6371.lcs.mit.edu/currentsemester/handouts/
everything in moderation
Thanks for attacking me when I offered a truce, flameboy.
:)
Linear region is when the device is switching, between Cutoff and Saturation. You really don't know anything about a CMOS transistor, do you? Man, you must be lying about your job, 'cause I fell for it for a minute there.
I just realized the problem: you're A FUCKING ASIC designer! LOL! No wonder you don't know what I'm talking about! I was gonna say that some day you'll get a real job where this stuff really matters, but nobody would hire someone who doesn't even understand what the linear region of operation is! LOL!
Good luck, loser!
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