Whether he has or hasn't, he may have instead been talking about an electric rocket, such as the one described here and discussed here. I'd say that calling him "stupid" for that was rude, but mostly it was just perplexing.
I've you had read the article, it explains that "The Vasimir involves the injection of a gas such as hydrogen into an engine that turns it into a plasma." The most direct method of doing that would be to pass it through the reactor core. ( assuming you're using a reactor that can produce high enough temperatures ) I admit I thought he was talking about some type of conventional light water reactor, hence my comment. And I did not call him stupid, I called the idea of boiling water to produce energy on a spacecraft "stupid". ( or maybe I should have said "out of place" )
If indeed you were to reject thermoelectrics and go with a turbine design, I would expect it would be a compact closed-loop high temperature gas reactor that used something such a Helium for it's cooling and heat capture.
Maybe you should think before posting patronizing "watch your behavior" comments from your higher level of self decreed moral superiority.
Good luck with that. Not only a nuclear reactor, but a heat exchanger, a turbine, and a generator.
Uhhhhh? Have you ever heard of nuclear thermal rockets? NASA's NERVA program? You know a nuclear reactor can heat substances other than just water. I don't know if you were trying to be funny because "a turbine, and a generator" is just stupid.
That's a lot of complexity for a space mission.
And what space mission is not complicated? There's this thing called "technology" that improves exponentially with time and better technology allows greater complexity.
There are more direct ways to generate electricity with nuclear reactions, but none are really practical for this sort of power output, that I'm aware of. I'm thinking a more straightforward application of nuclear power would work better. Something like this.
I had thought of Antimatter, but we're talking about a near term mission that uses proven and tested technology. ( for its energy source ) Maybe in 50 years we'll be using antimatter for all our energy storage needs, but that implies we'll have large supplies of Anti-Hydrogen ice. Can you tell me where I can buy some today?
( By the way, I'm not a skeptic when it comes to Antimatter based energy storage and propulsion. The problem now is that current particle accelerators are designed to study particle physics, not to produce antimatter. In fact, Robert Forward showed that if we were to build accelerators specifically designed to produce antimatter,( perhaps a special linear wake-field accelerator ) we could potentially produce at least 1 milligram per year at a cost of only around a 10 million dollars. If one where to use many accelerators in parallel that where able to produce higher energies, that amount might be up in the gram-kilogram range.)
I think the parent poster was trying to differentiate between an RTG (like Voyager has) which relies on the natural decay of radioactive isotopes and a full-bore nuclear fission reactor which induces decay with a neutron chain reaction.
Engine?
The scaled down test version might use something "conventional" as its power source, such as
an RTG. But, in order for the VASIMIR to work at full-scale, say in a human Mars mission, the
power source is going need a VERY large energy density -- something not achievable with any known
and tested chemical reaction. I have no idea why they call the power source the "engine" but
perhaps it's to placate the environmentalist wackos who will go nuts after hearing the obvious : the
"engine" or power source is a nuclear reactor. It will be interesting ( and probably funny ) to see how
this plays out in the long run if NASA sticks with this technology.
While I agree with you that isolation based on language feature isn't a particulary new concept, Microsoft's SIP have their own twist: the channel they're using for messaging must repect some kind of FSM for the communication state, which helps in case of error for assigning the blame.
This is just Design by Contract "embraced and extended" from Eiffel. There are a number of concurrent programming languages that have this capability.
The following is copied from my journal. It's a comment concerning the microkernel protection mechanisms of Midori which was intended to be posted in the previous story, but unfortunately I modded that one. This time, dupes actually help;) :
"SIP", or "Software isolated processes" is just MS marketing hype speak for what is known as a Language-based system in which seperate processes can be isolated from one another without paging or other hardware protection mechanisms. This is done using the semantics of the language in which the processes are programmed which excludes any possibility of one process intruding into the address space of another.
One example of a similar OS would be Bell Labs' Inferno. ( thanks to Knots for pointing this out ) Also, there's JX, which is an open-source microkernel based operating system in which the (micro)kernel and the applications are written in Java and run under a modified version of the JVM.
A while back there was an article on/. about a "quantum afterburner" : a device that could directly extract energy from a heat source, say, car exhaust, in the form of a laser beam.
Back in 2003, when rumors were circulating about an AMD "K9" processor, everyone thought that a new, revolutionary, designed from the ground up processor architecture was in the works. Actually, it was. AMD was designing an *8-issue superscalar OoOE* 64-bit x86 processor. Basically the Alpha EV8 reincarnated in the form of an x86 chip. ( remember that AMD inherited a substantial portion of the Alpha design team after DEC was swalloed up by Compaq )
Unfortunately, as usual, management could only see 6-months ahead and the chip was canceled in favour of a 64-bit processor that was cheaper and easier to design and consequently would increase short-term revenue.
No, they canceled it because it was over-ambitious and couldn't work. The thermals of the design were impossible to manage, and the frequency scaling was predicted to be horrible.
Then they should have put it on ice until the K8 had generated enough money and enough time had passed for the process technology to be good enough. Or they could have had a small team working on the design in parallel. There's no excuse.
No halfway-successful CPU company thinks "6 months down the road" like you claim. CPUs take years to design, tape-out, and manufacture, and CPU company management knows this.
Apparently you have problem understanding hyperbolic prose, although I do admit I should have said "week" or used "myopic" instead.
The processor that was hailed as a "revolutionary" x86 design, the Opteron, was, in fact, *directly* based off of the *K7* design. It was basically a K7 with a beefed up datapath, support for SSE2 and other miscellany, an on-board memory controller, and a high speed serial point-to-point interconnect as a replacement for the front side bus ( Hypertransport ) bolted on.
... not to mention AMD64, a new ISA based on x86 -- something Intel wrote off as "impossible".
It includes 2x the number of GPRs (from 8 to 16), and eliminates tons of legacy cruft instructions from x86.
The "mode switching" behavior that allows K8 to switch between 32bit and 64bit modes on the fly is pretty impressive, as well.
A *new* ISA. I think that's a "bit" of an overstatement. Getting rid of some useless opcodes ( if they would have gotten rid of "tons" there'd be little left of the x86 ISA ) and introducing new instruction prefixes could be done by any 15 year old teenage Demoscener who hacks assembly. When I was that age I fully understood the x86 instruction format and I can tell you that this "innovation" is really inflated.
Oh and doubling the GPRs along with the datapath, now that's really innovative. I mean, no one's ever done that in the history of the microprocessor.
As for the "mode switching behavior" now that's an innovation. I mean, nobody has ever thought of a way to save such a complicated processor state
, oh, wait, there was this thing introduced by Intel called Virtual 8086 mode -- you could easily switch to protected mode and back with that hmmm......
So, while AMD basically did nothing essentially new with their architecture over the years, it gave Intel ample time to design, *from the ground up*, 5 new processor architectures : The Pentium-M, Core, Core 2, Nehalem, and Atom.
AMD's worst mistake was the cancellation of the Alpha EV8 inspired "K9" in 2003. Now they are paying for it.
jdb2
What the fuck?
The use of profanity usually signals that one is unable to articulate ones argument because there is none or one knows it is flawed.
Pentium-M, Core, Core 2, etc are not "revolutionary, from the ground up" architectures. In fact, the basic architecture, when you boil it down, is nothing more than a "very beefed up" P6 -- AKA Pen
I think everyone has their own version of what a "ground up" design should be. When I talk about a "ground up" design ( with respect to a processor ) I'm talking about minimal re-use of RTL code. Just because a design re-implements a functional construct or block of a previous design in brand new RTL code, it doesn't mean that the previous construct/block was "copied over" and as such is based on or a "spinoff" of the previous design, no more than one would say ReactOS is "based on" or a "spinoff" of Microsoft Windows. If you're referring to concepts alone, then that's another matter. Under the above definition, the Core architecture is ground-up just as the intuitive software counterpart of this definition means that, say, a new operating system is "ground up" even though it incorporates various pieces of code from other OSs, like a tcp/ip stack.
This is completely wrong. If you would have read the rest of the thread you would know that the Core architecture was a ground-up design that got it's *inspiration* from some of the ideas implemented in the Pentium-M and from completely new ideas. Ideas aren't born in a vacuum. Innovation takes old ideas and combines them into something that is more than the sum of its parts.
As all Trolls, you have no reasoning ability. In the context of this discussion, Intel would have to have bolted more crap onto the NetBurst Architecture, but they didn't -- they saw that they were running into a wall and changed design philosophies. Sounds like innovation to me. Also, Intel designed the Pentium-M around the general architecture/design-philosophy of the P-III architecture -- they didn't directly copy it or reuse its RTL code. The fact that they took what general design philosophies were good in the P-III and ran with them, strikes me as insightful, having the ability to recognize ones mistakes and when one strayed from the correct path, and especially very *innovative*. Those ideas *evolved* ie. innovation. They did not stay static.
Thank you for letting me deconstruct your "argument" Mr. Troll.
Back in 2003, when rumors were circulating about an AMD "K9" processor, everyone thought that a new, revolutionary, designed from the ground up processor architecture was in the works. Actually, it was. AMD was designing an *8-issue superscalar OoOE* 64-bit x86 processor. Basically the Alpha EV8 reincarnated in the form of an x86 chip. ( remember that AMD inherited a substantial portion of the Alpha design team after DEC was swalloed up by Compaq )
Unfortunately, as usual, management could only see 6-months ahead and the chip was canceled in favour of a 64-bit processor that was cheaper and easier to design and consequently would increase short-term revenue.
The processor that was hailed as a "revolutionary" x86 design, the Opteron, was, in fact, *directly* based off of the *K7* design. It was basically a K7 with a beefed up datapath, support for SSE2 and other miscellany, an on-board memory controller, and a high speed serial point-to-point interconnect as a replacement for the front side bus ( Hypertransport ) bolted on.
Now, you would think that the new Barcelona architecture was a great innovation, but not so much. It, like the Opteron, is a heavily leveraged design based off of the previous processor generation, namely the K8.
To get to the point, the fact is that AMD never truly created a new processor architecture -- they never truly innovated beyond bolting new crap onto old designs. In fact, the basic architecture of AMD's latest design, when you boil it down, is the same as the *K7*. Barcelona is just a ( very ) beefed up K7.
When you keep designing architectures like this you eventually hit a wall and start to stagnate due to the law of diminishing returns. So, while AMD basically did nothing essentially new with their architecture over the years, it gave Intel ample time to design, *from the ground up*, 5 new processor architectures : The Pentium-M, Core, Core 2, Nehalem, and Atom.
AMD's worst mistake was the cancellation of the Alpha EV8 inspired "K9" in 2003. Now they are paying for it.
I'm no POWER architecture expert ( as can be seen ) but you need at least 1 execution pipeline to support an SMT thread.
No, in fact. A single pipeline can support an arbitrary number of threads, just taking one instruction from one of those threads in any given cycle.
This is not SMT. It's fined-grained multithreading ( or barrel processing ) ala the UltraSparc T2. ( Niagra 2 ) I'm talking about "threads" in the context of SMT.
From memory, the POWER5 has 8 pipelines, and the POWER6 has 5. I don't think IBM have released details of the POWER7 yet.
Without SMT the execution pipeline represents *1* thread of execution.
Absolutely.
If the processor *also* ( I don't know why you have a problem with this word. How about "in addition to" ?)
How about just saying "has"?
has SMT support, then that gives you support for n additional threads for n execution pipelines.
Not exactly. You can have 2-way SMT on an 8-issue core (POWER5), or 8-way SMT on a 2-issue core.There's no direct relationship between the number of threads and the number of pipelines.
I had thought of this case, but again we're talking about "normal" SMT ie. SMT that gives you the best performance/thread-count. 2-way SMT on an 8-issue core is just wasting resources, especially in the case that the processor is in-order. 8-way SMT on a 2-issue core would result in a significant performance loss as the overhead associated with switching threads would outweigh the gain made by trying to saturate the execution resources of the core.
It should be noted that previous POWER architectures had 2 threads per core.
Correct.
They also had SMT ( Simultaneous Multi-Threading ) support, which gave them an "effective" 4 threads per core.
No, they do not "also" have SMT. It is the SMT that gives them 2 threads per core in the first place.
I'm no POWER architecture expert ( as can be seen ) but you need at least 1 execution pipeline to support an SMT thread. Without SMT the execution pipeline represents *1* thread of execution. If the processor *also* ( I don't know why you have a problem with this word. How about "in addition to" ?) has SMT support, then that gives you support for n additional threads for n execution pipelines.
Power 5 & 6 have 2-way SMT. Power 7 has 4-way SMT.
SMT (aka hyperthreading - Intel P4 HT) is as real as multi-threading per core gets. If you instead duplicated the entire execution pipeline you'd just have another entire core!
Please see my reply to mike260. I don't know where I got the idea that the POWER architecture was scalar.
The execution pipeline of a modern CPU consists of many specialized decode, load/store, integer/logic (ALU), floating point (FPU), etc components (often more than one of each type) that all run independently, maybe idle at any given time if not needed or maybe waiting for operand results of an earlier step in the pipeline, or waiting for memory access (latency).
What SMT essentially does is add mutiple decode streams feeding into the pipeline so that the pipeline and it's constituent components are genuinely exectuting the instruction streams from multiple threads simultaneously. Despite the fact that they are still competing for the shared components there is still genuine parallelism since in a single threaded scenarion many of the units may be sitting idle waiting for operands or memory access. Using SMT means that the execution units are more fully utilized and it prevents memory latency (cache misses) from stailling the core by allowing the pipeline to utilize the execution units (ALU, FPU, etc) for instructions for which the operands are already available.
In summary, SMT is true multi-threaded core multi-threading. The only better (but more wasteful) type of multithreading is to use multiple cores, but they are still not fully indpendent since (at least in a desktop architecture) they are going to be competing for scarce memory and bus bandwidth.
I appreciate your thoughtfulness but I am versed in modern Digital-Logic/Microprocessor Design and Computer Architecture. I have to admit I thought you were patronizing me. ( But that's normal as I have a short temper, which can be intuited from my past posts;) But again, the reason I said "per execution unit" was due to the strange idea that the POWER architecture was scalar. I don't know where I got that in my head -- a scalar processor with SMT is an oxymoron. The current POWER architecture implementation is in-order -- for some reason I mistook that for "scalar" - Brain Fart.:)
It should be noted that previous POWER architectures had 2 threads per core. They also had SMT ( Simultaneous Multi-Threading ) support, which gave them an "effective" 4 threads per core. I wonder. Are the all the threads on the POWER7 "true" threads ( ie. 4 execution units -- 1 per thread ) or is it a 2 thread setup with SMT? On the other hand, if the POWER7 really does have 4 "true" threads, then with SMT you'd get an "effective" *8* threads per core.
D'oh! Forgot to put in the oblig. line "with a street value of $150,000" and yes, the second paragraph was jocular ( apparently we have some immature newbies that can't objectively moderate or else my humor just sucks, which is a distinct possibility:)
But seriously it's actually thought, because of recent research, that chocolate is so pleasurable because it contains trace amounts of cannabinoids.
I can see it now "In an ongoing series of police raids in an effort to stop the illegal use and sale of Cocoa, officials seized 100 pounds of Wonka chocolate bars that were in the possession of a previously cited Cocoa abusing teenager. As a dealer, he faces a possible life sentence if convicted."
Slashdot Mirror
Have you ever heard of nuclear thermal rockets?
Whether he has or hasn't, he may have instead been talking about an electric rocket, such as the one described here and discussed here. I'd say that calling him "stupid" for that was rude, but mostly it was just perplexing.
I've you had read the article, it explains that "The Vasimir involves the injection of a gas such as hydrogen into an engine that turns it into a plasma." The most direct method of doing that would be to pass it through the reactor core. ( assuming you're using a reactor that can produce high enough temperatures ) I admit I thought he was talking about some type of conventional light water reactor, hence my comment. And I did not call him stupid, I called the idea of boiling water to produce energy on a spacecraft "stupid". ( or maybe I should have said "out of place" ) If indeed you were to reject thermoelectrics and go with a turbine design, I would expect it would be a compact closed-loop high temperature gas reactor that used something such a Helium for it's cooling and heat capture.
Maybe you should think before posting patronizing "watch your behavior" comments from your higher level of self decreed moral superiority.
jdb2
Good luck with that. Not only a nuclear reactor, but a heat exchanger, a turbine, and a generator.
Uhhhhh? Have you ever heard of nuclear thermal rockets? NASA's NERVA program? You know a nuclear reactor can heat substances other than just water. I don't know if you were trying to be funny because "a turbine, and a generator" is just stupid.
That's a lot of complexity for a space mission.
And what space mission is not complicated? There's this thing called "technology" that improves exponentially with time and better technology allows greater complexity.
There are more direct ways to generate electricity with nuclear reactions, but none are really practical for this sort of power output, that I'm aware of. I'm thinking a more straightforward application of nuclear power would work better. Something like this.
I had thought of Antimatter, but we're talking about a near term mission that uses proven and tested technology. ( for its energy source ) Maybe in 50 years we'll be using antimatter for all our energy storage needs, but that implies we'll have large supplies of Anti-Hydrogen ice. Can you tell me where I can buy some today? ( By the way, I'm not a skeptic when it comes to Antimatter based energy storage and propulsion. The problem now is that current particle accelerators are designed to study particle physics, not to produce antimatter. In fact, Robert Forward showed that if we were to build accelerators specifically designed to produce antimatter,( perhaps a special linear wake-field accelerator ) we could potentially produce at least 1 milligram per year at a cost of only around a 10 million dollars. If one where to use many accelerators in parallel that where able to produce higher energies, that amount might be up in the gram-kilogram range.)
jdb2
I think the parent poster was trying to differentiate between an RTG (like Voyager has) which relies on the natural decay of radioactive isotopes and a full-bore nuclear fission reactor which induces decay with a neutron chain reaction.
Exactly.
jdb2
Engine? The scaled down test version might use something "conventional" as its power source, such as an RTG. But, in order for the VASIMIR to work at full-scale, say in a human Mars mission, the power source is going need a VERY large energy density -- something not achievable with any known and tested chemical reaction. I have no idea why they call the power source the "engine" but perhaps it's to placate the environmentalist wackos who will go nuts after hearing the obvious : the "engine" or power source is a nuclear reactor. It will be interesting ( and probably funny ) to see how this plays out in the long run if NASA sticks with this technology.
jdb2
There are a number of concurrent programming languages that have this capability.
Oops. That should be "many programming languages that support concurrency combined with this capability."
jdb2
While I agree with you that isolation based on language feature isn't a particulary new concept, Microsoft's SIP have their own twist: the channel they're using for messaging must repect some kind of FSM for the communication state, which helps in case of error for assigning the blame.
This is just Design by Contract "embraced and extended" from Eiffel. There are a number of concurrent programming languages that have this capability.
jdb2
The following is copied from my journal. It's a comment concerning the microkernel protection mechanisms of Midori which was intended to be posted in the previous story, but unfortunately I modded that one. This time, dupes actually help ;) :
"SIP", or "Software isolated processes" is just MS marketing hype speak for what is known as a Language-based system in which seperate processes can be isolated from one another without paging or other hardware protection mechanisms. This is done using the semantics of the language in which the processes are programmed which excludes any possibility of one process intruding into the address space of another.
One example of a similar OS would be Bell Labs' Inferno. ( thanks to Knots for pointing this out ) Also, there's JX, which is an open-source microkernel based operating system in which the (micro)kernel and the applications are written in Java and run under a modified version of the JVM.
jdb2
Two words: filesystem support.
Boot up Linux and all the stuff on your NTFS partition is read-only.
What? You know, Linux has had full NTFS Read/Write support for a while now, see :
http://www.linux-ntfs.org/
Also, ever heard about WUBI ?
jdb2
Here's a link to the pre-print :
http://xxx.lanl.gov/abs/quant-ph/0105135
jdb2
A while back there was an article on /. about a "quantum afterburner" : a device that could directly extract energy from a heat source, say, car exhaust, in the form of a laser beam.
Here's a link to the cached Nature article : http://209.85.141.104/search?q=cache:RV6U7lxRqFUJ:www.nature.com/nsu%255C/nsu_pf/020128/020128-3.html+quantum+laser+heat+car+exhaust&hl=en&ct=clnk&cd=1&gl=us
jdb2
Back in 2003, when rumors were circulating about an AMD "K9" processor, everyone thought that a new, revolutionary, designed from the ground up processor architecture was in the works. Actually, it was. AMD was designing an *8-issue superscalar OoOE* 64-bit x86 processor. Basically the Alpha EV8 reincarnated in the form of an x86 chip. ( remember that AMD inherited a substantial portion of the Alpha design team after DEC was swalloed up by Compaq )
Unfortunately, as usual, management could only see 6-months ahead and the chip was canceled in favour of a 64-bit processor that was cheaper and easier to design and consequently would increase short-term revenue.
No, they canceled it because it was over-ambitious and couldn't work. The thermals of the design were impossible to manage, and the frequency scaling was predicted to be horrible.
Then they should have put it on ice until the K8 had generated enough money and enough time had passed for the process technology to be good enough. Or they could have had a small team working on the design in parallel. There's no excuse.
No halfway-successful CPU company thinks "6 months down the road" like you claim. CPUs take years to design, tape-out, and manufacture, and CPU company management knows this.
Apparently you have problem understanding hyperbolic prose, although I do admit I should have said "week" or used "myopic" instead.
The processor that was hailed as a "revolutionary" x86 design, the Opteron, was, in fact, *directly* based off of the *K7* design. It was basically a K7 with a beefed up datapath, support for SSE2 and other miscellany, an on-board memory controller, and a high speed serial point-to-point interconnect as a replacement for the front side bus ( Hypertransport ) bolted on.
The "mode switching" behavior that allows K8 to switch between 32bit and 64bit modes on the fly is pretty impressive, as well.
A *new* ISA. I think that's a "bit" of an overstatement. Getting rid of some useless opcodes ( if they would have gotten rid of "tons" there'd be little left of the x86 ISA ) and introducing new instruction prefixes could be done by any 15 year old teenage Demoscener who hacks assembly. When I was that age I fully understood the x86 instruction format and I can tell you that this "innovation" is really inflated.
Oh and doubling the GPRs along with the datapath, now that's really innovative. I mean, no one's ever done that in the history of the microprocessor.
As for the "mode switching behavior" now that's an innovation. I mean, nobody has ever thought of a way to save such a complicated processor state , oh, wait, there was this thing introduced by Intel called Virtual 8086 mode -- you could easily switch to protected mode and back with that hmmm......
So, while AMD basically did nothing essentially new with their architecture over the years, it gave Intel ample time to design, *from the ground up*, 5 new processor architectures : The Pentium-M, Core, Core 2, Nehalem, and Atom.
AMD's worst mistake was the cancellation of the Alpha EV8 inspired "K9" in 2003. Now they are paying for it.
jdb2
What the fuck?
The use of profanity usually signals that one is unable to articulate ones argument because there is none or one knows it is flawed.
Pentium-M, Core, Core 2, etc are not "revolutionary, from the ground up" architectures. In fact, the basic architecture, when you boil it down, is nothing more than a "very beefed up" P6 -- AKA Pen
I think everyone has their own version of what a "ground up" design should be. When I talk about a "ground up" design ( with respect to a processor ) I'm talking about minimal re-use of RTL code. Just because a design re-implements a functional construct or block of a previous design in brand new RTL code, it doesn't mean that the previous construct/block was "copied over" and as such is based on or a "spinoff" of the previous design, no more than one would say ReactOS is "based on" or a "spinoff" of Microsoft Windows. If you're referring to concepts alone, then that's another matter. Under the above definition, the Core architecture is ground-up just as the intuitive software counterpart of this definition means that, say, a new operating system is "ground up" even though it incorporates various pieces of code from other OSs, like a tcp/ip stack.
jdb2
This is completely wrong. If you would have read the rest of the thread you would know that the Core architecture was a ground-up design that got it's *inspiration* from some of the ideas implemented in the Pentium-M and from completely new ideas. Ideas aren't born in a vacuum. Innovation takes old ideas and combines them into something that is more than the sum of its parts.
jdb2
As all Trolls, you have no reasoning ability. In the context of this discussion, Intel would have to have bolted more crap onto the NetBurst Architecture, but they didn't -- they saw that they were running into a wall and changed design philosophies. Sounds like innovation to me. Also, Intel designed the Pentium-M around the general architecture/design-philosophy of the P-III architecture -- they didn't directly copy it or reuse its RTL code. The fact that they took what general design philosophies were good in the P-III and ran with them, strikes me as insightful, having the ability to recognize ones mistakes and when one strayed from the correct path, and especially very *innovative*. Those ideas *evolved* ie. innovation. They did not stay static.
Thank you for letting me deconstruct your "argument" Mr. Troll.
jdb2
If I may quote http://en.wikipedia.org/wiki/Intel_Core_microarchitecture :
The Intel Core Microarchitecture is designed from the ground up, but similar to the Pentium M microarchitecture in design philosophy.
Furthermore, if you do some searching, you'll find that the Core microarchitecture was almost completely designed by a team in Israel.
jdb2
Unfortunately, as usual, management could only see 6-months ahead and the chip was canceled in favour of a 64-bit processor that was cheaper and easier to design and consequently would increase short-term revenue.
The processor that was hailed as a "revolutionary" x86 design, the Opteron, was, in fact, *directly* based off of the *K7* design. It was basically a K7 with a beefed up datapath, support for SSE2 and other miscellany, an on-board memory controller, and a high speed serial point-to-point interconnect as a replacement for the front side bus ( Hypertransport ) bolted on.
Now, you would think that the new Barcelona architecture was a great innovation, but not so much. It, like the Opteron, is a heavily leveraged design based off of the previous processor generation, namely the K8.
To get to the point, the fact is that AMD never truly created a new processor architecture -- they never truly innovated beyond bolting new crap onto old designs. In fact, the basic architecture of AMD's latest design, when you boil it down, is the same as the *K7*. Barcelona is just a ( very ) beefed up K7.
When you keep designing architectures like this you eventually hit a wall and start to stagnate due to the law of diminishing returns. So, while AMD basically did nothing essentially new with their architecture over the years, it gave Intel ample time to design, *from the ground up*, 5 new processor architectures : The Pentium-M, Core, Core 2, Nehalem, and Atom.
AMD's worst mistake was the cancellation of the Alpha EV8 inspired "K9" in 2003. Now they are paying for it.
jdb2
No, in fact. A single pipeline can support an arbitrary number of threads, just taking one instruction from one of those threads in any given cycle.
This is not SMT. It's fined-grained multithreading ( or barrel processing ) ala the UltraSparc T2. ( Niagra 2 ) I'm talking about "threads" in the context of SMT.
From memory, the POWER5 has 8 pipelines, and the POWER6 has 5. I don't think IBM have released details of the POWER7 yet.
Absolutely.
How about just saying "has"?
Not exactly. You can have 2-way SMT on an 8-issue core (POWER5), or 8-way SMT on a 2-issue core.There's no direct relationship between the number of threads and the number of pipelines.
I had thought of this case, but again we're talking about "normal" SMT ie. SMT that gives you the best performance/thread-count. 2-way SMT on an 8-issue core is just wasting resources, especially in the case that the processor is in-order. 8-way SMT on a 2-issue core would result in a significant performance loss as the overhead associated with switching threads would outweigh the gain made by trying to saturate the execution resources of the core.
jdb2
Correct.
No, they do not "also" have SMT. It is the SMT that gives them 2 threads per core in the first place.
I'm no POWER architecture expert ( as can be seen ) but you need at least 1 execution pipeline to support an SMT thread. Without SMT the execution pipeline represents *1* thread of execution. If the processor *also* ( I don't know why you have a problem with this word. How about "in addition to" ?) has SMT support, then that gives you support for n additional threads for n execution pipelines.
Power 5 & 6 have 2-way SMT. Power 7 has 4-way SMT.
Thanks for the info, and correction.
jdb2
SMT (aka hyperthreading - Intel P4 HT) is as real as multi-threading per core gets. If you instead duplicated the entire execution pipeline you'd just have another entire core!
Please see my reply to mike260. I don't know where I got the idea that the POWER architecture was scalar.
The execution pipeline of a modern CPU consists of many specialized decode, load/store, integer/logic (ALU), floating point (FPU), etc components (often more than one of each type) that all run independently, maybe idle at any given time if not needed or maybe waiting for operand results of an earlier step in the pipeline, or waiting for memory access (latency).
What SMT essentially does is add mutiple decode streams feeding into the pipeline so that the pipeline and it's constituent components are genuinely exectuting the instruction streams from multiple threads simultaneously. Despite the fact that they are still competing for the shared components there is still genuine parallelism since in a single threaded scenarion many of the units may be sitting idle waiting for operands or memory access. Using SMT means that the execution units are more fully utilized and it prevents memory latency (cache misses) from stailling the core by allowing the pipeline to utilize the execution units (ALU, FPU, etc) for instructions for which the operands are already available.
In summary, SMT is true multi-threaded core multi-threading. The only better (but more wasteful) type of multithreading is to use multiple cores, but they are still not fully indpendent since (at least in a desktop architecture) they are going to be competing for scarce memory and bus bandwidth.
I appreciate your thoughtfulness but I am versed in modern Digital-Logic/Microprocessor Design and Computer Architecture. I have to admit I thought you were patronizing me. ( But that's normal as I have a short temper, which can be intuited from my past posts ;) But again, the reason I said "per execution unit" was due to the strange idea that the POWER architecture was scalar. I don't know where I got that in my head -- a scalar processor with SMT is an oxymoron. The current POWER architecture implementation is in-order -- for some reason I mistook that for "scalar" - Brain Fart. :)
jdb2
Please change "4 execution units -- 1 per core" to "4 execution pipelines, supporting up to 4 simultaneous threads of execution".
jdb2
It should be noted that previous POWER architectures had 2 threads per core. They also had SMT ( Simultaneous Multi-Threading ) support, which gave them an "effective" 4 threads per core. I wonder. Are the all the threads on the POWER7 "true" threads ( ie. 4 execution units -- 1 per thread ) or is it a 2 thread setup with SMT? On the other hand, if the POWER7 really does have 4 "true" threads, then with SMT you'd get an "effective" *8* threads per core.
jdb2
jdb2
I can't remember the exact study, but googling the journals sure turns up a lot of stuff : http://scholar.google.com/scholar?q=cocoa+OR+cacao+OR+chocolate+cannabinoid+OR+cannabinoids+OR+cannabis&hl=en&lr=&btnG=Search
jdb2
But seriously it's actually thought, because of recent research, that chocolate is so pleasurable because it contains trace amounts of cannabinoids.
I can see it now "In an ongoing series of police raids in an effort to stop the illegal use and sale of Cocoa, officials seized 100 pounds of Wonka chocolate bars that were in the possession of a previously cited Cocoa abusing teenager. As a dealer, he faces a possible life sentence if convicted."
jdb2
How the hell is this a Troll?