Cell may not be good for Apple, but that doesn't mean it isn't good for the PS3.
It isn't appropriate for Apple because it doesn't have regular Altivec. So that means that code written for older PPCs wouldn't run well on it. It also wouldn't be appropriate because the Cell doesn't have out-of-order execution (retirement) of instructions. That means that instructions must be scheduled in the proper order, taking memory latencies into account. This isn't possible on a Mac, because Macs change all the time. Today's CPU has a 5 clock latency to memory, tomorrows has a 7 clock latency (because CPUs speed up more rapidly than memory does). If that happened, Cell would start to run slowly because the code isn't arranged correctly for the new latencies.
But on a console, all those relationships are fixed when the console is first built. The CPU doesn't get faster over time, they're all the same until the console is retired.
So, don't jump to conclusions here. Cell may not be for Apple, but it looks like a great choice for a console.
Brand name recognition is highly overrated once a product becomes commonplace, it becomes a product type, not a brand. Ask Sony about "Walkman" sales. Or Jacuzzi.
"Which is immaterial. You can't just pop in the next best memory technology on either Intel or AMD systems - they both put a cap on what you can use. Even going to the next best P4 FSB to use faster DDR2 causes you to replace your CPU, mobo, and memory, so a claimed advantage or disadvantage here would be mistaken."
That's not my point. I think you missed it again. In order to use new memory types on an Intel system, they just need a new chipset, a North bridge. So that means that P4 for example which once used RDRAM and SDRAM later used DDR and DDR2. If Intel chooses not to support a memory type, a 3rd party (who has a chipset license) can support it for them, and the processor can use it. This is not the case on the AMD chips, since the memory controller is in the chip. In order to adopt new memory, AMD must come out with a new chip, and probably a new socket too (as standards often add pins).
This is a big difference.
You don't have to change your FSB to use DDR2 on an Intel. You might in order to get max speed, but I'm not talking about max speed here. I'm worried about pricing. You can leash DDR2-533 to a 800FSB P4 with some degree of effeciency, certainly enough for most people.
As to the non-responsive thing, I say AMD locks you out of DDR2, you respond that who cares, DDR3 is the thing. Well, AMD locks you out of DDR3 also. Your response is non-responsive, it doesn't answer my complaint, it actually states a new one.
As to the CAS stuff, it appears you're right, CAS3 is premium for DDR2. However, I disagree that CAS2 for DDR is cheap. Even at newegg. It's 50% more than regular CAS3 or CAS2.5. It's premium. But you're correct, both modules in the test were premium modules.
Again, as to no real-world disadvantage, you're still wrong. It removes the flexibility of memory module type support from the chipset designer (of which there are at least 4 companies) and puts it in the hand of AMD alone. As DDR2 drops below the price of DDR in the 2nd half of this year, it will hurt AMD, since as you say, they won't have DDR until next year.
My point isn't that you can upgrade yourself, it is that the change in predominant memory type makes the AMD CPU itself obsolete, while on the Intel side, new mobos come out to support the new style.
That hurts AMD in the marketplace. You're right that the impact on individual users is much smaller.
Why do you ascribe this write-once, run anywhere stuff to Java? Look up the UCSD P-System. It used p-code (pseudo code) that was interpreted on multiple platforms. There was a UCSD Pascal released for the Apple in 1979 or so. http://en.wikipedia.org/wiki/UCSD_P-system
So I think you are off-based on the idea that the US had to match the Japanese on this front and that the Japanese and iTron created it.
I know several Taiwanese who would take umbrage and your insinuation that the Japanese created their foundries. It's as if you think all other countries in the Orient are subservient to Japan...
ARM isn't an open core. ARM has been known to sue companies that implement their instruction set.
'In a regular helicopter, the air only ever pushes against the _leading_ edge of the blade.'
That's not correct.
You describe what is going on at mu-1 accurately. But actually, there's another way to use mu. mu is the percentage of the retreating blade which is moving backwards in the air (relative to its direction of rotation).
For example, if a helicopter is stationary (mu-0), then all the retreating blade is moving forward in the air.
At mu-1 the entire blade is going backwards (except for an infinitely small area at the tip).
At mu-0.1, then the inner 10% of the blade is moving forward (along the direction of rotation) slowly enough that the direction of travel overcomes this and it is slipping backwards through the air.
So at any speed over mu-0, a portion of the retreating blade is going backwards. And since regular helicopters can exceed mu-0, your statement that in a regular helicopter air only ever pushes against the leading edge of the blade is incorrect.
So it looks like perhaps you should refrain from teaching both geography and aerospace engineering.
You can calculate the amount of entropy in a document (text or no) and that is a limit to how small you could possibly make it.
I don't recall how close modern methods like arithmatic encoding make it to that limit, but I know it's close enough that we couldn't double the compression ratio of text documents from the current state of the art.
Trellis coding is a system for dealing with induced errors in modem signalling. It allows you to cancel some of them out. It doesn't actually increase the throughput in an ideal situation.
The thing that allowed us to reach the limit for a phone line is combined amplitude-phase coding, or the creation of the "constellation diagram" for modem encoding.
The constellation defines certain combinations of phase and amplitude that represents groups of bits (a baud). Trellis coding simply defines additional combinations that are not sent. If you see any of these on the receiving end, then you realize that the constellation is either being twisted (phase error) or shrunk/grown (amplitude error) and you can try to compensate for it.
The name comes from a trellis, like you grow plants on. The legal signals sent should go through the holes in the trellis. If you receive a signal that falls on the trellis (hits the trellis) you adjust it so that it goes through the trellis and assume this adjustment factor can be used to adjust other, valid hits too to more accurately determine the data that was sent.
artists and movie-goers can benefit?
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Lucas's New HQ
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Artists benefit? It's a commercial complex. It's for making money. This isn't an art enclave any more than Nickelodeon Studios is. This complex is for making art which can be replicated and sold to earn him even more money.
Movie-goers benefit? So he can make Star Wars 3.5? Or remake them all in stupid 3D?
Lucas made a lot of money off his films and effects studios. He used it as hw saw fit, which was to make a place where he can more effectively more money.
That's all fine. It's his money. But pardon me if I don't get all sappy over it.
There are plenty of people who need a heart transplant who simply live with their current faulty heart until one becomes available. These people are what I referred to (somewhat stupidly) as ordinary people. These procedures would reduce their chances of survival, not increase them.
Other people's hearts begin to fail before a replacement is availble, they are candidates for these experimental procedures, as they have no other hope.
And no, the money doesn't go into the pocket of the representative. It goes into their campaign fund. They do not have access to this money for their own personal use. Well, until they retire and don't seek reelection, then they can dip into it. Which is ridiculous in my book.
I am not saying the US system is perfect. I just don't see how the Australian system is much better or even different. The main differences are two things.
1. You seem to not like the American political process, whereas you like the Australian one. 2. You seem to understand the Australian political process well, whereas you only know certain aspects of the American one.
You fill in all gaps in your knowledge by applying and misapplying your biases and misunderstandings as appropriate.
In the US right now, the most troublesome contributions are really to parties and purportedly unaligned groups which are not actually unaligned. These are very unregulated, whereas direct donations to candidates are more regulated. For example, Kenny Lay paid for George W. Bush's gubernatorial and presidential inauguration parties. Is this kind of thing prohibited in Australia? Who's to say you can't rent a hotel across the street from the seat of government the night of the inauguration and invite people to come over there to celebrate? This is basically what Lay does and we can't stop him.
Now, I'm not saying there aren't problems with the US system, but the kind of safeguards you speak of in Australia not only would not solve our problems, but many are substantially already in place in the US!
As to the give-backs, it does happen. But not often. One Democratic candidate did it in the last US Presidential election. But most money (as I said above) actually goes to the parties, not the candidates and that money is usually kept in a "war chest" and used for another candidate for that party in a similar election. Similar means either a later election for the same post, or for a similar office.
AMD locks you into DDR right now. You cannot use DDR3 on an Athlon 66 or FX any more than you can use DDR2.
Your response is non-responsive.
Furthermore, DDR3 is most definitely going to be more expensive than DDR and DDR2 for the near future, probably prohibitively so.
As to memory prices, we'll just have to see. I do not subscribe to the idea that xbitlabs' reprints of stories in the Taiwanese technical news are any better than Tom's. But for that matter, neither is impressive.
I do strongly feel that DDR2 prices will drop below DDR prices. Intel machines use DDR2 now, the majority of the market will be with DDR2, and that'll make that the most common and cheapest form of memory. I could be wrong of course, since RDRAM never dropped in price (although I predicted that correctly too).
I'm not 100% certain Sciencemark measures memory bandwidth completely accurately. I know it is designed to, but it also accidentally measures bus utilitization and certain cache efficiency parameters (more accurately prefetch parameters) also. I do agree it does give an interesting "real-world" counterpoint to the more common mathematical definitions of memory bandwidth.
Finally, this test uses CAS2 DDR, and CAS3 DDR2. Although CAS3 DDR is the most common type of DDR2, CAS2 is by far NOT the most common type of DDR. CAS2 DDR costs about twice as much as regular CAS2.5 DDR (more than regular DDR2 also). The tester should have used lower-latency DDR2 or regular-latency DDR in order to have a more apples-to-apples test.
Finally, your posts are near unreadable due to poor formatting. I used to have that problem too. You should change the pop-up next to the submit and preview buttons to "plain old text" before you submit your post. Leaving it at HTML means that all your paragraph breaks are eaten. Alternately, you could put some explicit breaks in your posts. Using "plain old text" doesn't limit you much, links and such still work.
When they reject something like this, it's typically because there are better alternatives. And no, death isn't considered a better alternative. When this device works better than other procedures, it'll be accepted. And given that it is a dangerous procedure itself, that probably means it'll first be approved for patients that (as you say) are starting death in the face. Once it works really well, it might be ready for ordinary people.
Registration, mandatory with Mac OS X. Activation, no.
And you can even get around the registration if you are a bit crafty.
But either way, Mac OS X won't suddenly decide to stop working on you in the future and make you re-authenticate like Windows can do. (Although this has never happened to me.)
You meant the serial ports on the IIfx, not IIvx. They were 6502s that babysat the ports. Yeah, they pretty much sucked. They were worse at most things. They were actually better at receiving LocalTalk packets with virtual memory turned on than the standard ports though. But honestly, if you paid that much for your computer, you probably had an ethernet card.
My understanding was the PGA actually accelerated autoCAD, which was enough for some people. Overall, it was a huge flop.
Apple also had some video accelerators. The 8*24GC was their first one, it was rarely faster than the regular video card* and vastly less compatible.
*The 8*24GC was faster for line-drawing operations, and also somewhat helped overcome the slow NuBus in the IIfx. But any decent onboard video (like the IIci and later) was much faster at all standard cases.
On the topic, Apple also had a smart ethernet card (it used A/ROSE). It was also slower than a non-smart card. Apple released a "dumb" driver for it at some point that bypassed the coprocessor and was faster than the "smart" driver. They then released a card with all the smarts stripped off. It was much cheaper.
I while I'm posting, I'm gonna say that I think that there is a market for smart NICs, for certain operations. I don't need one, but packet filters/forwarders definitely find them useful.
Even a microcontroller will present some problems to you. This is because wire-wrapping really requires DIP (or other through-hole) packages on chips. And even microcontrollers aren't made in through-hole packages that much anymore.
Honestly, nowadays it is more common to buy a reference board with a prototyping area.
Furthermore, apparently you also have lobbies and lobbyists. Which also is another way money influences the system.
It doesn't sound like our systems are all that different, honestly. I think maybe you just suffer from an overly negative impression of how the US system works.
I appreciate any corrections you can give me. I don't like to be wrong multiple times. You can help me be right more often by pointing out where I am wrong and helping me get the correct info.
My point was that Intel has not been behind AMD in memory bandwidth in recent memory. At most times, including right now, they are ahead of AMD in memory bandwidth. The parent (now super parent) poster was wrong in saying AMD was ahead.
Intel reached the memory bandwidth levels AMD is at right now almost 3 years ago with the 3.0GHz/800FSB Pentium 4.
Being stuck with DDR isn't a problem as far as performance. But right now memory (esp. Taiwanese) vendors are dropping their prices on DDR2 trying to accelerate the switch to DDR2 from DDR. This is presumably to get out from under the license fees they pay to Rambus for DDR. But regardless of the reasons, as DDR2 drops in price below DDR, many Athlon users are going to wish they could use DDR2.
As to your comments that memory manufacturers say DDR2 prices aren't going to drop, I could find nothing like that at all. Most news sources say DDR2 prices will drop below DDR prices in the 2nd half of the year. More specific news says things like I mentioned above. http://www.tomshardware.com/hardnews/20050609_0654 49.html.
As fast as having your own onboard memory controller is, it does stifle innovation as far as what memory can be used on motherboards completely. So you had better be SURE your bet is right. I'm not 100% sure AMD's is.
I dunno about Intel copying AMD's plans. I haven't heard anything of it. To do so requires adding at least 160 pins to the CPU package. And it means you can't do multi-chip multi-processing.
As to your comments that this means that I/O traffic doesn't tie up the FSB, you are incorrect. When you do I/O, the data doesn't go directly to the CPU (into the CPU registers), it goes into RAM. And AMD has the memory controller on the CPU, so that means that when you are moving data from the disk to the RAM, the data on an AMD has to go into the CPU on the HT bus, and out on the FSB (RAM) pins. So I/Os still tie up the FSB.
On an Intel, the data never even goes to the CPU, it comes in the south bridge (ATA, including SATA, most other stuff) or directly into the north bridge (GigE), and then goes out on the RAM pins (the magic of DMA). So there's no more or less competition for memory bandwidth in an Intel than on an AMD.
Essentially, AMD just moved the northbridge into the CPU. Why this decreases the memory latency, I'm not sure. I'm not saying it doesn't either, as the numbers seem to indicate it does.
I dunno if Intel is going to copy AMD. Right now, Intel is busy moving the GPU onto the northbridge to save money (esp. in laptops). That means Intel probably isn't going to move the northbridge onto the CPU, at least not on all systems.
But then again you use the longer latency (30 cycles for an instruction) of the P4 (Netburst) architecture to indicate why it has lower bandwidth (instructions per clock).
Latency and bandwidth are not the same thing, cannot be used interchangably and cannot be transformed one into the other with simple math.
Even with a 30 cycle latency the P4 could easily execute (complete) 1 instruction per clock. And actually, it probably executes (completed) more than 1 instruction per clock.
The reason Athlon has higher IPC is because it has IPC. I know that sounds stupid, but it is the nearest we can come to explaining it. It was designed to do more in every clock, so that it could be faster without going to a higher frequency (lower cycle time). P4 (Netburst) was designed to actually do less per clock so that they could reduce the cycle time and raise the frequency. That's the differences, you could nibble around the edges so more, but that's about as close as you can get without getting into the real specifics of the design.
You're a pretty crappy Computer Engineer from what I can tell.
When Intel came out with the 800MHz FSB (6.4GB/s), they handily beat AMD on benchmarks. AMD didn't have the internal memory controller at the time. Plus they had a slow FSB. Plus they were in that awkward time before NVidia jumped on the bandwagon, and so the chipsets for AMD were terrible, most of them bad VIA performers.
AMD may have the upper hand in many benchmarks right now (I guess you don't look at video compression), but it hasn't been that way for long. AMD's most recent rise above Intel really started with Intel's 3.4GHz offerings. In the period before that (the early 875P chipset days, and the aforementioned 800FSB and 3.0GHz range), Intel was beating AMD handily, although not at nearly equivalent prices. This is especially true on memory-intensive benchmarks. It was quite a step forward for a company that at that time was just emerging from the dark days of RDRAM stupidity.
Also note to say that the hypertransport bus is why AMD's dual cores run faster than Intel's dual cores is pure speculation. Do you have any real reasons to put behind that or just assertions?
Even if Intel does use the standard FSB for inter-processor communcations, their FSB is currently faster than AMD's HT. The bandwidth of the HT on AMD chips is 8.0GB/sec. The bandwidth of the FSB on Intel's fastest processors is 10.7GB/sec.
I'm not dumping on AMD. I like AMD. But the amount of misinformed speculation and assertions as to why they are doing well is astounding.
Also, I find the "troll" moderation on my post above insulting. It's seems silly to me, but disregarding that, I find it ridiculous that people automatically moderate "troll" apparently just for speaking any nice things about Intel.
Intel generally leads AMD in memory bandwidth, at least without any overclocking.
Intel was doing 6.4GB/s (dual channel PC3200 RAM) when AMD was at 2.7GB/sec. (single channel PC2700).
Also, note that memory accesses don't go over HyperTransport on an Athlon. The memory controller is built into the CPU. This is nice for latency, but bad because it means that Athlon users are stuck with whatever memory technology AMD has selected. At the moment, that means Athlon systems are stuck with DDR right now even as DDR2 prices fall below DDR prices.
Also, HyperTransport isn't all that insanely fast. Amongst other thinks, clocking cycles are part of the "GHz" rating on HT, and so the bandwidth is lower than it might seem.
Buffering does not reduce the amount of I/O you do. If you need to read data, you need to read it. It has to come from the drive. Even if it comes from a buffer, it came from the drive to get into the buffer.
No amount of buffering will fix a problem with being truly I/O bound.
Caching doesn't help either, if you are reading a large, sequential data set and producing another. Look ahead caching can maybe help with that, but if you are truly I/O bound, you won't get a chance to read ahead, because you'll be using the I/O for needed operations constantly, with no time for speculative operations.
Because midichloreans are clearly a corruption of mitochondria. Mitochondria are most definitely inherited.
Beyond that, even if it isn't an inconsistency, it is stupid.
The story of Ep 4 is the same as many other stories. A young nobody farm boy in the ass-end of space turns out to be very important, in fact, perhaps the most important person in the world.
It's the same story as "The Princess Diaries". It's the same story as the Harry Potter books. The story is told many times, because people who feel perhaps their life is worthless (and they are worthless) are very receptive to it. It gives people hope that perhaps they are that undiscovered diamond in the rough.
But this story is greatly undercut if you can be accurately tested for your ability (and thus importance) at birth. It becomes virtually impossible for someone to be classified as no one and actually be a big deal. It definitely undercuts the force of the story, because it removes hope that that nobody reader really was already determined to be truly nobody and not an undiscovered gem.
See GATTACA. It's a story of a person truly exceeding their parameters determined of birth. That's a much better story than "we knew he could do this all along".
Slashdot Mirror
Cell may not be good for Apple, but that doesn't mean it isn't good for the PS3.
It isn't appropriate for Apple because it doesn't have regular Altivec. So that means that code written for older PPCs wouldn't run well on it. It also wouldn't be appropriate because the Cell doesn't have out-of-order execution (retirement) of instructions. That means that instructions must be scheduled in the proper order, taking memory latencies into account. This isn't possible on a Mac, because Macs change all the time. Today's CPU has a 5 clock latency to memory, tomorrows has a 7 clock latency (because CPUs speed up more rapidly than memory does). If that happened, Cell would start to run slowly because the code isn't arranged correctly for the new latencies.
But on a console, all those relationships are fixed when the console is first built. The CPU doesn't get faster over time, they're all the same until the console is retired.
So, don't jump to conclusions here. Cell may not be for Apple, but it looks like a great choice for a console.
How's it doing for TiVo?
And when you think workstations, you think SUN!
Brand name recognition is highly overrated once a product becomes commonplace, it becomes a product type, not a brand. Ask Sony about "Walkman" sales. Or Jacuzzi.
And BTW, I think "catsup", I'm old school.
"Which is immaterial. You can't just pop in the next best memory technology on either Intel or AMD systems - they both put a cap on what you can use. Even going to the next best P4 FSB to use faster DDR2 causes you to replace your CPU, mobo, and memory, so a claimed advantage or disadvantage here would be mistaken."
That's not my point. I think you missed it again. In order to use new memory types on an Intel system, they just need a new chipset, a North bridge. So that means that P4 for example which once used RDRAM and SDRAM later used DDR and DDR2. If Intel chooses not to support a memory type, a 3rd party (who has a chipset license) can support it for them, and the processor can use it. This is not the case on the AMD chips, since the memory controller is in the chip. In order to adopt new memory, AMD must come out with a new chip, and probably a new socket too (as standards often add pins).
This is a big difference.
You don't have to change your FSB to use DDR2 on an Intel. You might in order to get max speed, but I'm not talking about max speed here. I'm worried about pricing. You can leash DDR2-533 to a 800FSB P4 with some degree of effeciency, certainly enough for most people.
As to the non-responsive thing, I say AMD locks you out of DDR2, you respond that who cares, DDR3 is the thing. Well, AMD locks you out of DDR3 also. Your response is non-responsive, it doesn't answer my complaint, it actually states a new one.
As to the CAS stuff, it appears you're right, CAS3 is premium for DDR2. However, I disagree that CAS2 for DDR is cheap. Even at newegg. It's 50% more than regular CAS3 or CAS2.5. It's premium. But you're correct, both modules in the test were premium modules.
Again, as to no real-world disadvantage, you're still wrong. It removes the flexibility of memory module type support from the chipset designer (of which there are at least 4 companies) and puts it in the hand of AMD alone. As DDR2 drops below the price of DDR in the 2nd half of this year, it will hurt AMD, since as you say, they won't have DDR until next year.
My point isn't that you can upgrade yourself, it is that the change in predominant memory type makes the AMD CPU itself obsolete, while on the Intel side, new mobos come out to support the new style.
That hurts AMD in the marketplace. You're right that the impact on individual users is much smaller.
Why do you ascribe this write-once, run anywhere stuff to Java? Look up the UCSD P-System. It used p-code (pseudo code) that was interpreted on multiple platforms. There was a UCSD Pascal released for the Apple in 1979 or so. http://en.wikipedia.org/wiki/UCSD_P-system
So I think you are off-based on the idea that the US had to match the Japanese on this front and that the Japanese and iTron created it.
I know several Taiwanese who would take umbrage and your insinuation that the Japanese created their foundries. It's as if you think all other countries in the Orient are subservient to Japan...
ARM isn't an open core. ARM has been known to sue companies that implement their instruction set.
http://www.eetimes.com/story/OEG20000228S0007
You say:
'In a regular helicopter, the air only ever pushes against the _leading_ edge of the blade.'
That's not correct.
You describe what is going on at mu-1 accurately. But actually, there's another way to use mu. mu is the percentage of the retreating blade which is moving backwards in the air (relative to its direction of rotation).
For example, if a helicopter is stationary (mu-0), then all the retreating blade is moving forward in the air.
At mu-1 the entire blade is going backwards (except for an infinitely small area at the tip).
At mu-0.1, then the inner 10% of the blade is moving forward (along the direction of rotation) slowly enough that the direction of travel overcomes this and it is slipping backwards through the air.
So at any speed over mu-0, a portion of the retreating blade is going backwards. And since regular helicopters can exceed mu-0, your statement that in a regular helicopter air only ever pushes against the leading edge of the blade is incorrect.
So it looks like perhaps you should refrain from teaching both geography and aerospace engineering.
You can calculate the amount of entropy in a document (text or no) and that is a limit to how small you could possibly make it.
I don't recall how close modern methods like arithmatic encoding make it to that limit, but I know it's close enough that we couldn't double the compression ratio of text documents from the current state of the art.
Trellis coding is a system for dealing with induced errors in modem signalling. It allows you to cancel some of them out. It doesn't actually increase the throughput in an ideal situation.
The thing that allowed us to reach the limit for a phone line is combined amplitude-phase coding, or the creation of the "constellation diagram" for modem encoding.
The constellation defines certain combinations of phase and amplitude that represents groups of bits (a baud). Trellis coding simply defines additional combinations that are not sent. If you see any of these on the receiving end, then you realize that the constellation is either being twisted (phase error) or shrunk/grown (amplitude error) and you can try to compensate for it.
The name comes from a trellis, like you grow plants on. The legal signals sent should go through the holes in the trellis. If you receive a signal that falls on the trellis (hits the trellis) you adjust it so that it goes through the trellis and assume this adjustment factor can be used to adjust other, valid hits too to more accurately determine the data that was sent.
Artists benefit? It's a commercial complex. It's for making money. This isn't an art enclave any more than Nickelodeon Studios is. This complex is for making art which can be replicated and sold to earn him even more money.
Movie-goers benefit? So he can make Star Wars 3.5? Or remake them all in stupid 3D?
Lucas made a lot of money off his films and effects studios. He used it as hw saw fit, which was to make a place where he can more effectively more money.
That's all fine. It's his money. But pardon me if I don't get all sappy over it.
And not be staring death in the face.
There are plenty of people who need a heart transplant who simply live with their current faulty heart until one becomes available. These people are what I referred to (somewhat stupidly) as ordinary people. These procedures would reduce their chances of survival, not increase them.
Other people's hearts begin to fail before a replacement is availble, they are candidates for these experimental procedures, as they have no other hope.
You think we don't have accountants?
And no, the money doesn't go into the pocket of the representative. It goes into their campaign fund. They do not have access to this money for their own personal use. Well, until they retire and don't seek reelection, then they can dip into it. Which is ridiculous in my book.
I am not saying the US system is perfect. I just don't see how the Australian system is much better or even different. The main differences are two things.
1. You seem to not like the American political process, whereas you like the Australian one.
2. You seem to understand the Australian political process well, whereas you only know certain aspects of the American one.
You fill in all gaps in your knowledge by applying and misapplying your biases and misunderstandings as appropriate.
In the US right now, the most troublesome contributions are really to parties and purportedly unaligned groups which are not actually unaligned. These are very unregulated, whereas direct donations to candidates are more regulated. For example, Kenny Lay paid for George W. Bush's gubernatorial and presidential inauguration parties. Is this kind of thing prohibited in Australia? Who's to say you can't rent a hotel across the street from the seat of government the night of the inauguration and invite people to come over there to celebrate? This is basically what Lay does and we can't stop him.
Now, I'm not saying there aren't problems with the US system, but the kind of safeguards you speak of in Australia not only would not solve our problems, but many are substantially already in place in the US!
As to the give-backs, it does happen. But not often. One Democratic candidate did it in the last US Presidential election. But most money (as I said above) actually goes to the parties, not the candidates and that money is usually kept in a "war chest" and used for another candidate for that party in a similar election. Similar means either a later election for the same post, or for a similar office.
AMD locks you into DDR right now. You cannot use DDR3 on an Athlon 66 or FX any more than you can use DDR2.
Your response is non-responsive.
Furthermore, DDR3 is most definitely going to be more expensive than DDR and DDR2 for the near future, probably prohibitively so.
As to memory prices, we'll just have to see. I do not subscribe to the idea that xbitlabs' reprints of stories in the Taiwanese technical news are any better than Tom's. But for that matter, neither is impressive.
I do strongly feel that DDR2 prices will drop below DDR prices. Intel machines use DDR2 now, the majority of the market will be with DDR2, and that'll make that the most common and cheapest form of memory. I could be wrong of course, since RDRAM never dropped in price (although I predicted that correctly too).
I'm not 100% certain Sciencemark measures memory bandwidth completely accurately. I know it is designed to, but it also accidentally measures bus utilitization and certain cache efficiency parameters (more accurately prefetch parameters) also. I do agree it does give an interesting "real-world" counterpoint to the more common mathematical definitions of memory bandwidth.
Finally, this test uses CAS2 DDR, and CAS3 DDR2. Although CAS3 DDR is the most common type of DDR2, CAS2 is by far NOT the most common type of DDR. CAS2 DDR costs about twice as much as regular CAS2.5 DDR (more than regular DDR2 also). The tester should have used lower-latency DDR2 or regular-latency DDR in order to have a more apples-to-apples test.
Finally, your posts are near unreadable due to poor formatting. I used to have that problem too. You should change the pop-up next to the submit and preview buttons to "plain old text" before you submit your post. Leaving it at HTML means that all your paragraph breaks are eaten. Alternately, you could put some explicit breaks in your posts. Using "plain old text" doesn't limit you much, links and such still work.
When they reject something like this, it's typically because there are better alternatives. And no, death isn't considered a better alternative. When this device works better than other procedures, it'll be accepted. And given that it is a dangerous procedure itself, that probably means it'll first be approved for patients that (as you say) are starting death in the face. Once it works really well, it might be ready for ordinary people.
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http://slashdot.org/comments.pl?sid=05/06/25/2330
Registration, mandatory with Mac OS X.
Activation, no.
And you can even get around the registration if you are a bit crafty.
But either way, Mac OS X won't suddenly decide to stop working on you in the future and make you re-authenticate like Windows can do. (Although this has never happened to me.)
Because Batman spends months in Tibet or China or something basically in ninja school. He wears the ninja mask and everything.
Honestly, I find this terrible. In my book, Batman is NOT a ninja. He learned to kick ass in the good ole U.S. of A.
I don't know why every hero has to be a martial artist now. Even the computer hackers.
I'm gonna go watch Fight Club.
You meant the serial ports on the IIfx, not IIvx. They were 6502s that babysat the ports. Yeah, they pretty much sucked. They were worse at most things. They were actually better at receiving LocalTalk packets with virtual memory turned on than the standard ports though. But honestly, if you paid that much for your computer, you probably had an ethernet card.
My understanding was the PGA actually accelerated autoCAD, which was enough for some people. Overall, it was a huge flop.
Apple also had some video accelerators. The 8*24GC was their first one, it was rarely faster than the regular video card* and vastly less compatible.
*The 8*24GC was faster for line-drawing operations, and also somewhat helped overcome the slow NuBus in the IIfx. But any decent onboard video (like the IIci and later) was much faster at all standard cases.
On the topic, Apple also had a smart ethernet card (it used A/ROSE). It was also slower than a non-smart card. Apple released a "dumb" driver for it at some point that bypassed the coprocessor and was faster than the "smart" driver. They then released a card with all the smarts stripped off. It was much cheaper.
I while I'm posting, I'm gonna say that I think that there is a market for smart NICs, for certain operations. I don't need one, but packet filters/forwarders definitely find them useful.
http://wired-vig.wired.com/news/business/0,1367,64 046,00.html?tw=wn_tophead_1
It hasn't happened again, but apparently some employees were taking shortcuts on their spare day each week.
I have to say I am constantly surprised at how much people value a company who mostly just copies what other companies do.
Even a microcontroller will present some problems to you. This is because wire-wrapping really requires DIP (or other through-hole) packages on chips. And even microcontrollers aren't made in through-hole packages that much anymore.
Honestly, nowadays it is more common to buy a reference board with a prototyping area.
It's not true. Donations are allowed at the local level.
Here is a page talking about how donations must be disclosed. How can you disclose donations if you say they are illegal?
http://www.dfat.gov.au/facts/sys_gov.html
Furthermore, apparently you also have lobbies and lobbyists. Which also is another way money influences the system.
It doesn't sound like our systems are all that different, honestly. I think maybe you just suffer from an overly negative impression of how the US system works.
I appreciate any corrections you can give me. I don't like to be wrong multiple times. You can help me be right more often by pointing out where I am wrong and helping me get the correct info.
My point was that Intel has not been behind AMD in memory bandwidth in recent memory. At most times, including right now, they are ahead of AMD in memory bandwidth. The parent (now super parent) poster was wrong in saying AMD was ahead.
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Intel reached the memory bandwidth levels AMD is at right now almost 3 years ago with the 3.0GHz/800FSB Pentium 4.
Being stuck with DDR isn't a problem as far as performance. But right now memory (esp. Taiwanese) vendors are dropping their prices on DDR2 trying to accelerate the switch to DDR2 from DDR. This is presumably to get out from under the license fees they pay to Rambus for DDR. But regardless of the reasons, as DDR2 drops in price below DDR, many Athlon users are going to wish they could use DDR2.
As to your comments that memory manufacturers say DDR2 prices aren't going to drop, I could find nothing like that at all. Most news sources say DDR2 prices will drop below DDR prices in the 2nd half of the year. More specific news says things like I mentioned above. http://www.tomshardware.com/hardnews/20050609_065
As fast as having your own onboard memory controller is, it does stifle innovation as far as what memory can be used on motherboards completely. So you had better be SURE your bet is right. I'm not 100% sure AMD's is.
I dunno about Intel copying AMD's plans. I haven't heard anything of it. To do so requires adding at least 160 pins to the CPU package. And it means you can't do multi-chip multi-processing.
As to your comments that this means that I/O traffic doesn't tie up the FSB, you are incorrect. When you do I/O, the data doesn't go directly to the CPU (into the CPU registers), it goes into RAM. And AMD has the memory controller on the CPU, so that means that when you are moving data from the disk to the RAM, the data on an AMD has to go into the CPU on the HT bus, and out on the FSB (RAM) pins. So I/Os still tie up the FSB.
On an Intel, the data never even goes to the CPU, it comes in the south bridge (ATA, including SATA, most other stuff) or directly into the north bridge (GigE), and then goes out on the RAM pins (the magic of DMA). So there's no more or less competition for memory bandwidth in an Intel than on an AMD.
Essentially, AMD just moved the northbridge into the CPU. Why this decreases the memory latency, I'm not sure. I'm not saying it doesn't either, as the numbers seem to indicate it does.
I dunno if Intel is going to copy AMD. Right now, Intel is busy moving the GPU onto the northbridge to save money (esp. in laptops). That means Intel probably isn't going to move the northbridge onto the CPU, at least not on all systems.
But then again you use the longer latency (30 cycles for an instruction) of the P4 (Netburst) architecture to indicate why it has lower bandwidth (instructions per clock).
Latency and bandwidth are not the same thing, cannot be used interchangably and cannot be transformed one into the other with simple math.
Even with a 30 cycle latency the P4 could easily execute (complete) 1 instruction per clock. And actually, it probably executes (completed) more than 1 instruction per clock.
The reason Athlon has higher IPC is because it has IPC. I know that sounds stupid, but it is the nearest we can come to explaining it. It was designed to do more in every clock, so that it could be faster without going to a higher frequency (lower cycle time). P4 (Netburst) was designed to actually do less per clock so that they could reduce the cycle time and raise the frequency. That's the differences, you could nibble around the edges so more, but that's about as close as you can get without getting into the real specifics of the design.
You're a pretty crappy Computer Engineer from what I can tell.
When Intel came out with the 800MHz FSB (6.4GB/s), they handily beat AMD on benchmarks. AMD didn't have the internal memory controller at the time. Plus they had a slow FSB. Plus they were in that awkward time before NVidia jumped on the bandwagon, and so the chipsets for AMD were terrible, most of them bad VIA performers.
AMD may have the upper hand in many benchmarks right now (I guess you don't look at video compression), but it hasn't been that way for long. AMD's most recent rise above Intel really started with Intel's 3.4GHz offerings. In the period before that (the early 875P chipset days, and the aforementioned 800FSB and 3.0GHz range), Intel was beating AMD handily, although not at nearly equivalent prices. This is especially true on memory-intensive benchmarks. It was quite a step forward for a company that at that time was just emerging from the dark days of RDRAM stupidity.
Also note to say that the hypertransport bus is why AMD's dual cores run faster than Intel's dual cores is pure speculation. Do you have any real reasons to put behind that or just assertions?
Even if Intel does use the standard FSB for inter-processor communcations, their FSB is currently faster than AMD's HT. The bandwidth of the HT on AMD chips is 8.0GB/sec. The bandwidth of the FSB on Intel's fastest processors is 10.7GB/sec.
I'm not dumping on AMD. I like AMD. But the amount of misinformed speculation and assertions as to why they are doing well is astounding.
Also, I find the "troll" moderation on my post above insulting. It's seems silly to me, but disregarding that, I find it ridiculous that people automatically moderate "troll" apparently just for speaking any nice things about Intel.
Intel generally leads AMD in memory bandwidth, at least without any overclocking.
Intel was doing 6.4GB/s (dual channel PC3200 RAM) when AMD was at 2.7GB/sec. (single channel PC2700).
Also, note that memory accesses don't go over HyperTransport on an Athlon. The memory controller is built into the CPU. This is nice for latency, but bad because it means that Athlon users are stuck with whatever memory technology AMD has selected. At the moment, that means Athlon systems are stuck with DDR right now even as DDR2 prices fall below DDR prices.
Also, HyperTransport isn't all that insanely fast. Amongst other thinks, clocking cycles are part of the "GHz" rating on HT, and so the bandwidth is lower than it might seem.
Where did you get that strange idea?
Buffering does not reduce the amount of I/O you do. If you need to read data, you need to read it. It has to come from the drive. Even if it comes from a buffer, it came from the drive to get into the buffer.
No amount of buffering will fix a problem with being truly I/O bound.
Caching doesn't help either, if you are reading a large, sequential data set and producing another. Look ahead caching can maybe help with that, but if you are truly I/O bound, you won't get a chance to read ahead, because you'll be using the I/O for needed operations constantly, with no time for speculative operations.
Because midichloreans are clearly a corruption of mitochondria. Mitochondria are most definitely inherited.
Beyond that, even if it isn't an inconsistency, it is stupid.
The story of Ep 4 is the same as many other stories. A young nobody farm boy in the ass-end of space turns out to be very important, in fact, perhaps the most important person in the world.
It's the same story as "The Princess Diaries". It's the same story as the Harry Potter books. The story is told many times, because people who feel perhaps their life is worthless (and they are worthless) are very receptive to it. It gives people hope that perhaps they are that undiscovered diamond in the rough.
But this story is greatly undercut if you can be accurately tested for your ability (and thus importance) at birth. It becomes virtually impossible for someone to be classified as no one and actually be a big deal. It definitely undercuts the force of the story, because it removes hope that that nobody reader really was already determined to be truly nobody and not an undiscovered gem.
See GATTACA. It's a story of a person truly exceeding their parameters determined of birth. That's a much better story than "we knew he could do this all along".
Piracy is indeed a social problem. But somehow I think that this abstinence method of solving it won't work any better on this than teenage pregnancy.