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How long will it be before employers start complaining that their UW co-op students don't know Linux or Java and can't work with non-Intel architectures? probably pretty long, seeing as E&CE already has tons of money invested Sun hardware (servers & workstations), Motorola hardware (Coldfire development boards), and Altera hardware for embedded systems development. Furthermore, Java is used for teaching purposes (and don't spout off FUD about how MS .NET will replace it) and I'm pretty sure Linux has a pretty good following in the area.

The demonstration and presentation was about their new display acceleration solution for mobile devices...

The demo they showed was indeed an FPGA. It has around 20k-30k gates, and was running at around 25MHz or so. The demonstration animated filled polygons and bezier curves, with various effects such as transparency at around 30-50 fps.

You shouldn't believe everything you're told. The chip was very clearly marked, it's an Altera APEX EP20K400C PLD. The memory chips on the back are Altera EPC SRAM 'configuration devices'. That means it's got between ~400,000 and 1,051,648 gates, not 20-30k.

While I can't fault them for writing a program that does everything you mentioned for this particular PLD, it's definitely not as impressive as they lead you to believe, and I don't see how this is 'their' silicon at all. The other card, I can't comment on, since it didn't actually do anything. (But we all know that a reputable company like Bitboys is far above faking a demo, right?)

The demonstration and presentation was about their new display acceleration solution for mobile devices...

The demo they showed was indeed an FPGA. It has around 20k-30k gates, and was running at around 25MHz or so. The demonstration animated filled polygons and bezier curves, with various effects such as transparency at around 30-50 fps.

You shouldn't believe everything you're told. The chip was very clearly marked, it's an Altera APEX EP20K400C PLD. The memory chips on the back are Altera EPC SRAM 'configuration devices'. That means it's got between ~400,000 and 1,051,648 gates, not 20-30k.

While I can't fault them for writing a program that does everything you mentioned for this particular PLD, it's definitely not as impressive as they lead you to believe, and I don't see how this is 'their' silicon at all. The other card, I can't comment on, since it didn't actually do anything. (But we all know that a reputable company like Bitboys is far above faking a demo, right?)

The demonstration and presentation was about their new display acceleration solution for mobile devices...

The demo they showed was indeed an FPGA. It has around 20k-30k gates, and was running at around 25MHz or so. The demonstration animated filled polygons and bezier curves, with various effects such as transparency at around 30-50 fps.

You shouldn't believe everything you're told. The chip was very clearly marked, it's an Altera APEX EP20K400C PLD. The memory chips on the back are Altera EPC SRAM 'configuration devices'. That means it's got between ~400,000 and 1,051,648 gates, not 20-30k.

While I can't fault them for writing a program that does everything you mentioned for this particular PLD, it's definitely not as impressive as they lead you to believe, and I don't see how this is 'their' silicon at all. The other card, I can't comment on, since it didn't actually do anything. (But we all know that a reputable company like Bitboys is far above faking a demo, right?)

It is: APEX 20K Devices.

anyone who has anything to do with a standards body nowadays know's that people try and hijack standards so their tech/patent gets into it

this way if you implement the standard you have to pay

you can't have an opensource MPEG 4 without paying 3million bucks when you distribute it and they call that a standard

ok real hardware and software

in terms of a kernel their is in My Humble Opinion

Linux

Open BSD

netbsd for every arch under the sun (joke included)

then we have the problem of hardware

Opencores provides some of the effort BUT my favorate is

LEON-1 VHDL model
- Functional SPARC compatible processor core integer unit. Runs on Altera, Mietec, Temic MG2, Xilinx. Developed for space missions. Implemented as a highly configurable, synthesisable GPL VHDL model.

Altera 10K200E FPGA or Xilinx XCV300 enable this you can also get a LCD and keyboard AMBA devices from www.gaisler.com

what I would like is a machine that you could say that the whole thing is opensource

regards

john jones

Nope.

Transmeta, maker of the Crusoe processor for mobile applications (</marketroid>) contracts the actual manufacturing process out to Texas Instruments.

Moreover, they already have a working model using development boards, for from the front page of the link I quote:
It is written entirely in VHDL. Originally designed and tested using Altera's APEX20K200E FPGA and Nios development board, the design is now ready for the public.

There's a variety of programming boards out there that can program a chip to your specs given the VHDL file. Just check out what Altera has to offer.

There is, basically. Try here. You will need to purchase some type of manufacturing line if you want to mass-produce them. Otherwise, you can just purchase an FPGA from here or here. The only problem is, the would be illegal too when assembled into a computer that could be used for storing movies, music, etc... Unless they had the copy protection built-in. If the SSSCA Bill doesn't pass or the h/w manufactures are allowed to do it on their own w/o law, then you Open Source h/w will be legal. Otherwise it wont be. If it does become law, I'm going to purchase as much h/w as I can and then never purchase again.

Lat I checked, Verilog wasn't even a company. I bet you're thinking of Xilinx or Altera. Note that Xilinx gets badass points for providing free development tools that aren't half bad, even if they are for Windoze.

As far as speed is concerned, there are two big factors that determine how fast you can run a hardware implementation of a design. First, there's the maximum clock speed of the FPGA. This is a parameter of the FPGA used, and, like CPUs, varies with the manufacturer and model. While it is possible to circumvent this with totally asynchronous designs, as you're not required to use the chip-wide clock, it's only practical in only a few unique applications (ARM AMULET). Second, the size of the design will affect the speed at which it will run. A simulation of an Athlon or a Pentium III (excluding large memories, like caches and ROMs) will be forced to run slowly because the propagation delay between far away cells in the FPGAs and, in extreme cases, between individual FPGAs themselves, will be too great to support high clock speeds. Plus, the gate propagation will be slower in an FPGA than on raw silicon. This factor is also somewhat dependent on the HDL CAD tool used and how smart its automatic floor planner is. Now put something simple like an ARM in an FPGA, and you can probably hit much higher speeds.

If someone is looking to tinker with some (F)PGA's I would recommend Altera's student kits and software. You can use the standard part schematics included or you can define your own using VHDL. Only $150 or $105 if you're a Georgia Tech student.

This is rather neat. We've been using PLDs, a different form of FPGAs, in our digital design class here at Georgia Tech. Basicly you can draw up a componet using VHDL or Verilog coding, download it to the PLD and the PLD will act as that componet. We've been using Altera's MAX+PLUS II software and boards to do our lab work. It would be really intresting to see a computer incorperate this into it's architechture. Imaging Q3 running off pure silicon. No more wizzing Hard drive. Now all we need is a VHDL coded version....

I used to work for a company that manufactures a very similar device as an add on card for PCs. True enough, a single transistor on the FPGA in each of these devices is capable of firing much faster than the clock speed of available processors. However, this is the switching speed of a single transistor on the device. When transistors are chained together, you get a phenomenon called gate delay, which is the amount of time each transistor takes to react to its inputs before the output level is changed. So if a single transistor is 1000 times faster than the clock speed of a PII, and we chain 1000 of these transistors together, our usable clock speed is now the same as the PII. Another item of worry for the designers of the image to go on the FPGA is clock tree generation. The clock signal for the FPGA must be generated in such a way that all areas of the chip are synchronized. Very often, the clock tree is the biggest problem in the design as it skews as each route gets longer.

These devices are fantastic if you have a very specific application that you wish to design them for (e.g. Image processing, voice analysis, SETI@Home). With the ability to be reconfigured at a moments notice, they are also much more reusable than an ASIC. But don't be misled by the speeds given in the marketing info. Get a demo chip from Altera or Xilinx and play with it for a while. Then make your own judgements about speed.

It's actually a NAND gate. Every combination of NOT, AND, OR, XOR, and so on can be represented by combinations of NAND gates. Any [logic] circuit could be built with significant numbers of them. That seems to be what Altera and Xilinx do for a living. I know that Xilinx has some pretty great educational prices, and you can pick up a PCI board with FPGA onboard for around $270 if memory serves.

...as long as you aren't looking for top-of-the-line. If you are a hobbyist or student, there are tools for you to use.

You mention Altera. If you are a student you can get the evaluation board (for 5k to 70k gate FPGAs--maybe larger now because the technology is so rapidly advancing) for very cheap--like $200--and it is still a good deal less even if you are not a student.

Furthermore, you can freely download (as in beer, not in speech--the source is closed) the basic MAX+PLUS and Synopsis software for use with the evaluation board. This is perfect for the hobbyist. In fact, these boards are ideal for implementing simple microprocessor cores plus added custom logic, and certainly beats wire-wrapping a bunch of 74hct-series gates and registers and stuff.

The good thing is that FPGA technology is moving so incredibly fast that eventually many more hobbyists could get involved. Plus, VHDL is supposed to be modular, so even if you can't synthesize an Athlon on your FLEX70K you could test and synthesize modules that perform some of its functions at a slower speed. Then if a bunch of hobbyists combined their modules they could come up with one or more open-source VHDL-based microprocessor designs.

If companies with the resources or money to access fabs like the design, with open source they would have ZERO design costs. This isn't so far fetched--I'd say that the Pentium III and PowerPCs could be the Windows 2000 and Mac OS X of the hardware world, and it could be possible to do a Linux or BSD of the hardware world as well. Sure, fab costs are very high, but for a project of that scale, engineering/design costs also play a gigantic factor. I think it could result in lower cost, more interoperable hardware designs. The only resistance is the closed attitude of chip makers (even their support software is closed source despite being downloadable on the net--wouldn't Altera gain a huge amount of support and boost sales of their FPGAs if they allowed the open-source community to develop software tools for their products?)

You could use an Altera with onchip memory and a PCI controller as a single chip solution, or go with a
PLX IOP480 which has an embedded PowerPC processor and an external memory bus. You could easily change your crypto program using one of these.
I'm using a PLX9054 on a board with a PPC G3, they have really nice software support and DMA capability. I'll bet the G4 could really crunch some data with it's vector unit. 3x faster in Distributed Net numbers over G3 from what I've read.

FPGAs with high gate counts (e.g. Flex 10kXXX series) are expensive, and physically quite large. The other problem involved with this is the compilers for FPGAs pretty much suck at laying out the wiring between gates. You end up with layouts that not only waste most of the space available on the FPGA, but are also an order of magnitude slower than you want.
Don't get me wrong. FPGAs are great for prototyping, but for real speed, ASICs will always be the best.