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Field Programmable Gate Arrays at MIT
Rhys Dyfrgi writes "There is an article in this month's Scientific American about the Raw microchip. Based around field programmable gates arrays, they claim it will reach speeds between 10 and 15 gigahertz by the year 2010. Because it's a FPGA, it can be instantly reconfigured to perform any task. It is one of the central items for the Oxygen Project. "
"A user would be able to tell the Handy 21, "Hey, turn yourself into a cell phone." The device would then locate the appropriate configuration software, download it and configure the wires of the Raw chip inside to give it the characteristics of a cell phone."
If this is gonna be reality in 10 years as they say, I'm in heaven.
Haha... I got it! The three kinds of chips; raw, memory, and potato...
But seriously, if this works... who's gonna take the lead in making it? Will this be open to many manufacturers or just one? Can Intel see this and buy it up and keep it to itself and screw us in the future?
If only they can make a raw OS (Linux?)
Out.
DSPs are in every hard drive, every cell phone, yes.. every modem. They're in tons of other places too, DVD players, digital cameras. There is a world of computing you don't see or hear about and that doesn't run Linux (or Windows). DSPs are fast, pretty cheap and in general have low power comsumption. Reprogramable? Realize that DSPs are simply microprocessors with some special architectural features that make them DSPs (harvard memory architecture, mac, etc.) So you program them by storing your programs written in C(++) or assembly into a ROM, the DSP will then execute anything you want from the ROM.
FPGAs are too damn expensive for commodity products. The article really is trying to hype up their research. After reading them compare a 10-15GHz processor in 10 years to a 0.5GHz processor today (more like a year to two years ago) I just had to scream HYPE! Show me the frequency! First Rodney Brooks' robot article then this. MIT is giving itself a bad name allowing these types of articles.
This stuff has all been pondered before, I'm surprised you even have to ask :)
;)
Nanotubes for cpus, one atom width wires = serious speed, run it cold enough and zero worries
Organic 'Puters, biological applications...wet to wire (transitors to neurons...serf the net for life
Quantum 'Puters on the end, logic beyond our capable depth of understanding really...thats the one that will probably end up outsmarting us (note to self: make sure theres always a manual way to pull ye plug)
The - "this isnt new, its been round for years" post
If anyone else has read this article I think they will agree with me. This "Raw Computation" article is complete fluff, basically four pages of nothing. Their 10 to 15 GHz comment reads like this: Raw chips will run at 10 to 15 GHz by 2010 as compared to 500 MHz for today's microprocessors. Ok, and how fast will microprocessors be in 2010?
FPGAs have been around for quite a while, and what is presented in this article shows no new research in this area.
I'm really dissapointed that Scientific America would publish such a weak article. I expect more from them.
PAL's and GAL's (and EPROM's too, while we're at it) have been around for about 20 years. FPGA's slightly less.
However, if you know of 10 GHz reconfigurable-computer, please let us know!
Heck, why stop there? just rearrange the atoms in that apple core and chicken bone you just threw out, and you've got yourself some filet mignon, plus some diamonds to boot :-)
I'll get back to you about 10 years with that 10GHz FPGA. Too bad it'll be smoked by ASICs in 10 years just like current FPGAs are smoked by current ASICs.
A RAW isn't the same as a FPGA. They used FPGA's for a prototype RAW machine which is probably where the confusion came from. A RAW machine has instruction sequencing, faster compile time, faster execution, lower area, and better power efficiency. It also eliminates/reduces most I/O bottlenecks thus allowing it to scale to levels unthinkable by current microprocessors.
...that does the reconfiguring. That sounds like as much as / more of of an advance as/than the chip itself.
Did anyone beside me notice that the text of the article was printed in Scientific American?
SA isn't noted as a journal for computer scientists and Electrical Engineers. Of course the article sounds fishy - it glosses over the all of the engineering problems and calls them wires!
I was halfway done writing a typical slashdot post lambasting the article before I decided to look at the web site for the Oxygen project. A cursory glance shows that they've got a very interesting project. I'm not going to spend any time on their data - I don't know if they're conclusions hold water or not, but it's definitely not a joke.
If you've got the background for it, or the sheer persistence, look at this or
that (basically the same stuff, but with prettier pictures).
It looks to me like they've got a great idea for quickly banging out custom ASIC blocks for signal processing problems. I wonder how well it would work with a general purpose computer.
It seems to me that the greatest general-purpose computing gains are when the FPGA recongures itself on the granularity level of a kernel context-switch or, even a finer level. Right now, FPGAs are REALLY slow to reprogram. If someone could come up with some kind of quickly reconfiguring device, they might be on to something.
The article is full of a lot of fluff. If you check out the articles on the Oxygen project's website, you'll see that they are basically pushing this project as a way of getting chip-level parallel processing.
The reconfigurability part of it just helps them to allocate shared silicon and gate-level resources, like parallel multi-chip machines allocate register and address-level resources.
So, in short, Beowulf on a chip!
The gave the numbers for making the RAW prototype made with FPGA's
2 hours/board using a Sun SparcStation 10/51
with 5 arrays of 64 boards(4013 FPGA's a board)
one of the advantages of RAW is that it doesn't have this huge compilation necessity b/c commonly used computing mechanism are already in the hardware
With "billions of transistors on a chip" and lord knows how many compiled "states" to the chip to do any number of useful things...how large will the software be? Let's hope some corresponding quantum leap in mass storage comes along as well.
It's nice to hear a voice of sanity.
I used to read articles like this and get that wonderful glow of amazement and optimism that gets
you going back to buy next month's issue. But this was before I had done any research myself.
Now it is awful hard to listen to the Dertouzoses of the world for fifteen minutes without thinking
the dirtiest word in the English language is seven letters long and starts with 'f'. Or wondering if any profession can be older than grantwriting.
What does Dertouzos do, anyway? What's his specialty? Compiler optimization? Algorithms? Does he still publish? Does he ever... code?
Does he remember how?
sorry hit the enter too soon...
anyhow from the specs it seems as though this chip could only do one thing at a time. A scheduler in a multitasking OS running on this thing would have to reconfigure the chip each time it switches tasks, or every so often optimize for all of the running tasks simultaneaosly. In either case there would likely be a significant perfomance drop compared to running just one thing, i.e. the sum of the parts would be less then each part taken separately. So it seems like there would still be a practical need to parallelize these chips - one might want to have a cell-phone and an rc5 keycracker at the same time...
You're right - in theory.
Consider temperature problems in the core of such a cubic CPU. Consider manufacturing problems for such a cubic CPU. Consider that it is a complete different paradigm than 2D logic circuits.
Yes - perhaps it will come - but there are way too many obstacles right now.
That patent office thing is always retold, and always wrong. Yes, the head of the patent office said something like that -- as a rhetorical flourish in his farewell speech. And it was more along the lines of "and our great nation is advancing so fast that I believe that it will not be long before we have invented all there is to be invented, rendering this office superfluous".
I don't have a reference, but I've seen several debunkings -- search around, it's fairly well known.
Would a cubic CPU (cCPU?) have circulatory system which carries a coolant? Hmmm.
The key is that you *never* do non-specific things with a computer. You just do different specific things with the same general purpose computer.
The problem with 3D chips is that they require 3D manufacturing. The only reasonable mass production we've been able to use so far is lithography, which is fundamentally 2D.
Yes, that's a workable approach... You can assign a certain number "n" tiles to one task and another number "x" tiles to some other task. Of course, that changes the size and shape of what's available to the compiler, so you need a recompile... The circuit patterns are dependent on the physical size and arrangement of tiles included in the chip.
2. 10-15 GHz, by putting registers along the internal busses so that operations that normally have to take just one cycle can be done in multiple cycles. Good, but not as exciting as it might sound. It could also be applied to normal processors.
3. Fine grained parallelism is hard to find; my professor has a project that is a highly parallel computer, and the biggest problem is not the shared memory, but making the compiler find parallelism to exploit.
4. The article is inconsistent. Is the big thing a reprogrammable device, or a self-modifying general purpose processor?
5. IANAE, but from what I understand, FPGA's are inherently slower than fixed silicon because of the cell arrangement. Although that isn't a problem now, it may be in the quest for the maximum possible clock frequency.
Having done GA's this would be an interesting field to explore. Hardware that you can train.
Only a few problems might arise though. If you train the hardware to do things, like become a mobile phone, act like a printer etc then you have to have some feedback on how well its changed to perfrom those duties, ie a Fitness. christ knows how you could train something to become a mobile phone with unsupervised learning at the moment. I mean the criteria for a human is easy, can i dial it, does it allow me to talk to the correct people ive dialled, does it take short messages etc. How this is going to be modelled for GA hadrware breeding solution is gonna be a bit tricky. I read a paper once of trying to get artificial fish to school (or rather flock like reynolds boids). The experiment failed. The paper is called something like "How not to train fish to school" or something. The crux of the problem was the evaluation by the fish (they were using neural nets mind) of how well it was schooling, as they were trying to evolve their own rules rather than fixed ones like reynolds.
Same could happen in producing GA'ed Hardware.
Brad
Wouldn't it just be easier to implement the cell phone functionality in software? Haven't we already proven many times over that designs using general purpose microprocessors are cheaper and simpler about 90% of the time? Aside from prototyping, the only people who should be using FPGAs are those who do too small volume to justify a fab.
If their pipe dream is true, how many electronics companies will be put out of work? All the jobs will shift to programming and making cheap i/o devices.
Except ASIC's don't let you reconfigure the arrangements of gates. Especially while it's mounted inside the circuit.
"Most personal computers use an interface called the Instruction Set Architecture, or ISA, between the hardware and the software."
I thought "ISA" referred to "Industry Standard Architecture", not "Instruction Set Architecture". The acronym was coined to differentiate the old 16 bit bus from the microchannel architecture being promoted by IBM in the late 80's.
The work of people who take on the right to redefine our acromyms should be looked at carefully. They could be talking horse manure.
I have a problem with anyone who can think that the phrase "Instruction Set Architecture" makes sense. Is he proposing an architecture that doesn't have a concept of instructions?
Let's think about developing a version of Linux that doesn't use instructions.
Another variation of "inbetween-ware" otherwise
called firmware. Has its ups and downs during
the decades.
I don't think people are suggesting that reconfigurable computing can compete with more standard architectures by using off-the-shelf FPGAs, except in very special purpose applications. Many research projects and startups are working on reconfigurable computing fabrics that are optimized for high-performance computation rather than random glue logic and prototyping.
Now regardless of the effectivness of this tech, the hard part will be integrating it into the PC market. The problem being...these chips are 100% useless without software designed for it.
I have two posible solutions to this...design a small FPGA into the current arcehtecture, that specialized software could use...or if the system is large enough have a default config...like if there is no software that has the gates programed in...make the chip automatically configure itself like the latest x86 chip...then it could function at about the same speed (maybe) and still run conventional software.
I also think these FPGA would be perfect in a Dual CPU box.
[1] What's so special about rocket scientists, anyway? There are plenty of professions nowadays requiring greater knowledge and skill.
Because aerospace engineers have to do everything that mech-e's do, plus some chem-e, comp sci, EE, and general systems integration. Other than that, its a peice of cake, trust me on this one, its currently my major.
-CC
"theres only one thing more ill tempered than a yak, and thats a yak herder"
It seems people are misunderstanding exactly what the RAW architecture is. From reading most of the papers related to the project, the RAW architecture is an array of simple pipelined RISC microprocessors each with its own local memory. This is called a Tile. These tiles are interconnected by a very fast statically scheduled switching network and a slower dynamic network.
The compiler is responsible for dividing up a program between the processors and generating the switch schedule so the processors can communicate. If the compiler can schedule the parallelism in the program across the tiles and generate an efficient static schedule, the RAW processor is very fast.
So, the interesting thing about the RAW architecture is the statically scheduled network. It is very fast, so it reduces the cost of interprocessor communication. This allows the compiler to exploit very fine grain parallelsim.
The problem with the static network is that you must know which tile a piece of data will reside on at COMPILE time. In many programs, especially object oriented programs, much data is dynamically allocated without an upper bound on the number of a given object type. This means that accesses to this data cannot be resolved at compile time and thus cannot complete on the static network, and so the compiler cannot exploit extremely fine grain parallelism for operations on these data structures.
On the other hand, many DSP and multimedia algortihms have memory access properties that allow the data sharing to take place on the static network making RAW a very intersting architecture from an embedded systems point of view.
I'm a FPGA designer. I use VHDL to create designs for some of the latest FPGA technology. And I think I can safely say that you are full of it.
There is absolutely no truth to your claim that FPGA's can run at higher clocks than current CPUs. It's the other way around -- fundamental architectural limitations of FPGAs limit them to slower clock speeds. Anybody who tells you otherwise is incompetent or lying. There is no known design technique for avoiding the speed penalty imposed by reconfigurable routing and logic function lookup tables. There isn't even any reason to expect that future technology will solve this, because the basic problem is that to make hardware reprogrammable you have to make it more complex. Fixed function logic and wires are inherently faster than reprogrammable versions of the same, and CPU designers take full advantage of this fact.
Worse yet, the fastest reprogrammable logic technologies available today tend not to be suitable for general-purpose computing, because they can't be reprogrammed on the fly. Only SRAM-based FPGAs are suitable for reconfigurable computing, and they're generally not as fast. For example, Xilinx gives a "marketing figure" of up to 200 MHz for Virtex, but as always that's based on something really bonehead simple, like a shift register or a small counter -- try to do anything useful and you'll be lucky to get it to work at 150, if that much.
The HAL "hyper-computer" appears to be nothing more than an investment scam. They don't have any real technology, their performance claims are at best misleading (who cares about 4-bit adds?) and at worst pure lies, and nothing they have put out suggests that they have any method for getting around the fundamental limitations of FPGAs. (Reconfiguration hurts, I/O is a problem, splitting designs across chips is a big problem, and most important of all, you can't hire software programmers to do FPGA designs and expect to get anything but a mess.)
The SA article was pretty lame. No substance at all, just wild claims about how wonderful the brave new world would be. If there was a "reasonable plan" set forth in the article, I'd sure like to know it. I didn't see any plan worth mentioning at all.
BTW, if you ("Quickening") don't have a CE or EE degree and some engineering experience, you have no ability to evaluate whether anything like a plan is there...
They were freaking amazing...just look at what one nation was doing in the 1930s, at this site. Hello X-33, X-34? And this was 60 years ago.
It's called "reconfigurable computing" and has been around for years. Take a look at http://www.embedded-solutions.ltd.uk/Projects/stor m.htm
It's not all of MIT. At first, it was just the Media Lab, humiliating the rest of us. Now, LCS, once a good, strong, proud lab, picked up Dertouzos as leader. Dertouzos has been doing everything he can to turn LCS into another Media Lab. It gets funding, but it makes us embarrased of our school. In the long run, it'll reduce our school to crap.
As an MIT student, I have to say I'm really embarrased about this. Traditionally, MIT didn't churn out this type of crap hype. Then the Media Lab showed up, and showed us they were willing to do anything for funding. Now LCS picked up Dertouzos as it's head, and it's slowiy starting to do the same thing. Most of LCS is still good, and the AI Lab is still clean, but part of LCS and Media Lab have been infested with this hype machine.
I like the scenario they describe: "You are on business in Paris. You excuse yourself from the meeting, go outdoors, pull out your handy and ask it to contact Joe."
Joe admits to being flattered, maybe a little curious, but is happily married and suggests you put your handy away before somebody sees the two of you and starts spreading rumors.
The First Computer Person :)
Maybe not incredibly technical (this is a _story_ not a proposal), but the idea isn't unheard of. It's a question of being able to make use of a vast number of extra gates- very much a neural net problem rather than a Von Neumann architecture.
I suspect the 'maybe logic' I went on about in the story might be as important a concept: it fascinates me that in _all_ the digital circuits we depend on, there's the capacity for non-boolean logic values. This simply depends on analog characteristics of the digital circuits, which in some cases is quite predictable and in other cases not- but the resolution is phenomenal and there's no delay time for calculating relationships- I've been meaning to torture some random CMOS logic chips with non-logic values and see what comes out the output. Has anybody done this? So far I only know that inverters are relatively linear, which is hardly surprising
Unfortunately, there's a bit too little of #5 lately, and too much of all the other crap.
10 PRINT CHR$(205.5+RND(1)); : GOTO 10
MEEPT!! is an eccentric user of slashdot who has been posting for nearly two years or so. He used to post a lot more in earlier times, but ever since Slashdot killed his account, forcing him to create a new one, he seems to be a less frequent visitor. His posts are usually insightful, but he presents his arguments/information in a humorous or unusual way, such as haikus and other poems, leading many people to misunderstand him. He's also not a Linux zealot, which gets him in trouble with many of the fanatics around here. I personally find him humorous.
"The glorious MEEPT would like to bring all the divided factions of linux into one big divided faction." - The Glorious MEEPT!!
10 PRINT CHR$(205.5+RND(1)); : GOTO 10
What a way to start, the lesson is: preview before posting
Since I have done been researching Slashdot for over 20 years now with a broad range of test subjects from around the world, I have discovered that these comments are posted, without fail, no matter what the article, and usually before the poster has read the article. I will cover them here so no one needs to say them and waste more vaulable space:
1) Does it run Linux?
2) How about a Beowulf cluster(an alteration goes like "Damn, wouldn't a Beowulf cluster of (insert computer chip, iBook, Red Hat Stock, anything really, in here) be sweet?")
3) This isn't news for nerds!
4) FIRST POST
5) MEEPT
6) MS Sucks
7) Apple sucks
8) Where can I get the source code?
9) No source code? Damn this thing is a piece of shit.(note, source code is required even if the item in discussion does not have source code, it's a freedom thing)
If I have missed any, please feel free to contribute to the standard Slashdot response. Once we have a good list, we should work on making a program that will automatically go to a story and post one of these comments at random, saving valuable time for the people who would have had to spend that time letting their brain rot while they typed.
I think the big caveat is at the end of the article which seems to suggest that a compiler for this kind of architecture might be really difficult to develop and have it meet the theoretical performance gains by going to this new architecture.
One thing that troubled me about the Handy 21 example: the author states that he has a pager, a cell phone and a Palm Pilot. He could tell his Handy 21 to become one of those devices. Wouldn't he rather have a device that did ALL of those things? Ummm... I think Motorola has a CDMA Star Tac with a Rex clip on that does all of that and more. Today. Not in the "near future".
Along those same lines, can this architecture be used for general purpose computing? Or for that matter, multitasking? What's the use of having an architecture that can be highly specialized if you're trying to do non specific things with it?
I really didn't buy the article. It all seemed way too pie-in-the-sky with no real accomplishments and nothing new to report.
Right now I hold Starbridge Systems in as much esteem as I hold American Computer. Starbridge systems makes provably bogus performance claims. They're not overstated nor are they misleading, they're bogus. Maybe they do have something but their marketing department is overzealous and/or stupid, either way having such obviously false information sure makes it look like a scam.
People who have programmed FPGA realize that the claim FPGAs run at a faster clock rate are
missing the point.
Creating a chip architecture/micro-architecture is a function of 4 fundamental tradeoffs:
Cycle time, Work per cycle, Area, and Time to market.
FPGA have chosen low work per cycle. In the past, CPUs chose high work per cycle.
Now, they are going in the direction of lower work per cycle (deeper pipelines, more latency).
Just a question of what you want.
Clock rate is just one choice of many, and has little to do with some magic FPGA architecture.
In fact with today's fpga, 200MHz is fast, compare that to your 450MHz pentium III...
The main architectural advantage of FPGAs is that a block of logic only needs to exist when you
are using it. This is simply a form of caching. Instead of having all the HW there (but slower),
you have only the subset you need (so it's faster). However, if you factor in the "misses"
(the time where logic has to be reprogrammed), it's a much more complicated problem which
doesn't have such an "obvious" solution...
Just like there are data sets that blow a CPU cache, there are probably algorithms that make
re-programmability a liability.
On the issue of efficiency, FPGA just have underused programmability and routing logic
instead of underused HW functional units in other architectures. Depends on the problem you are
trying to solve...
-slew
It's amazing how whenever I read about this stuff I get a warm fuzzy feeling. All of this great technology close at hand, a computer that uses a natural interface, human voice, and one that helps bring information closer to you at the beckoning of your voice. Then reality slams in.
Somehow if and when this eventualy reaches the marketplace I forsee a system that is competative within itself and with another, and where the features are broken due to an upgrade in some obscure module. I could forsee an AOL-Oxygen, but if you decided to breath that then you might poison another person who breaths MS-Oxygen if you try to talk together, but then again, AT&T-Oxygen is really poisonous as they own the network....
The scientists who give these speaches always make it sound so cool......
---- Fight to protect your right to keep and arm bears! ummmm... ya I think that's right....
Under the circumstances (unless Rob started this shortly after his birth) I'd say it's safe to assume that the author was deliberately speaking in the vernacular.
I see even classic Slashdot is now pretty much unusable on dial up anymore.
There's a whole lot of computer stuff in the current SA, but it came out a week ago. Did no one post it 'cause everyone assumed that someone else had, or are submissions really that backed-up.
SA had something about chips that could rewire themselves on the fly about a year ago as well.
I see even classic Slashdot is now pretty much unusable on dial up anymore.
Of course this means that you need to invent a new microarchitecture for every problem you want to solve, and that is why reconfigurable computing has not caught on. Very few people have the skill to create an efficient microarchitecture, and even for experts it takes a great deal of time. Software rocks because you already have the microarchitecture defined, you know what the rules are. This gives most folk enough structure to solve their problem.
In regard to "caching", I've yet to seen an application that actually benefits from dynamic reconfiguration at run-time as far as performance goes. In regard to cost, there are many shipping comercial applications of FPGAs that choose the FPGA configuration at boot time, or between operating modes. This isn't the same as reconfiguration as part of the exeuction of an algorithm. If an algorithm does reap a benefit from reconfiguration, it will be because of the FPGA's proximity to external memory, not because of the wacky logic you can build.
FPGAs may rock (as in world-record performance) for certain computing tasks, but for time-to-market DSPs still rule.
But this application of them looks promising. I was in the DSP business for a while, and we used FPGA's on our boards. Unfortunately it is still pretty expensive technology, but give it time.
'Fraid not. I don't understand the obcession with those, anyway. Maybe you should actually check the comment board before saying that. The main site said there were no comments yet, and the "read more" section said there were 4. 5 now, at least.
Wow, that was an unashamed self-promotion
with only promises and no products. I mean,
I know it's research project, but they don't even
have a good compiler and they claim they'll
be THE chips of the future. Now I know why the
horrible monster called X spread around - it must
be MIT flare for hype.
Also, it wouldn't work when hooked up to another computer...it seemed to be using some feedback from the er emitted by his box.
Guess no one else has been paying attention. FPGA's can run at much higher clock frequencies then current CPU's because of fundamental architectural differences. This is what the new HAL hyper-computer (and others) are based on. I read the SA article and it's ground-breaking ideas with a reasonable plan to enable them. Amazing syncronicity that Transmeta's latest patent application would also come out today; read the fine print and you will see that it is also about software changing hardware. All these advances have in common increasing the association of data with processing (the operands with the operators).
tcboo
Isn't this *exactly* what the HAL machines being produced by Starbridge Systems are doing?
This is why I think that a FPGA system would benefit the most from a model-reflective system such as TUNES (http://www.tunes.org)... where tasks would be recompiled on-the-fly to adapt to the current state of the chip.
To the editors: your English is as bad as your Perl. Please go back to grade school.
What's the next (r)evolution in processors after this? How many technologies are possible that'll keep pushing the limit?
Is the 21 postfix a reference to the next century?
Well yeah, but those are all obvious. I'm mean what's next for the silicon beyond the quantum, microminiaturization, and biological/chemical stuff.
I've known about those for awhile now, but I've just heard of fgpa recently. Since fpga is so much closer to a reality than those are, I'm wondering what else I've missed.
I only started reading /. in January and this has
been bugging me. Is it some MS related thing?
The only reason all cover-ups appear to fail is that you never hear about the ones that succeed.
Correct me if I'm wrong, but it seems the article was implying that fpga-based systems would replace current tech for cpu's. This all seems like a bunch of hype to me.
From what I'm seeing in the above comments, fpga's aren't really that good at general-purpose computing. Great. How about we use fpga's as add-on co-processors, programmed by the software that supports their use. Such a system could be used for video acceleration, sound processing, algorithmic acceleration (think: encryption, simulation, etc.), and it would be worlds better for performance, b/c there is still a traditional cpu in the machine.
Anyways, just my US$.02
-- ioctl
What? You mean you didn't produce any source code? Damn this thing is eating at my human rights! Maybe I'll file a petition with the UN.
http://www.jonmasters.org/
Ah, but does your comment run Linux?
http://www.jonmasters.org/
OK, so who's up for a Beowulf cluster?
http://www.jonmasters.org/
It's old. It's been said before.
http://www.jonmasters.org/
Well, not quite.
http://www.jonmasters.org/
Whatcha getting at?
http://www.jonmasters.org/
Yep. They sure do.
http://www.jonmasters.org/
But not as much as microsoft.
http://www.jonmasters.org/
Ah. So where can I get the source code for your article? It sure is a freedom thing. Oh and while your at it, where can I get the source for my bacon sandwich?
http://www.jonmasters.org/
Get my point? You just spent several minutes pointing out the "frequently occuring posts". YOUc could be finding something better to do.
http://www.jonmasters.org/
Oxford University have been doing this kind of stuff for ages - go to the oxford University Wolfson Research Laboratory. I don't have the full link off hand, but you'll find their research in the Parallel Computing department.
http://www.jonmasters.org/
FPGAs can do some neat things, but you are not going to build a fast general purpose computer out of FPGAs. They are relatively slow and make inefficient use of silicon. They do a good job on control and glue logic, plus you can fix design errors and add features without having to rework the hardware.
First, A disclaimer:
The comments I am going to make are not about what we will need in 5 or in 10 years, but what we will need at some unnamed future time when we finally need it. And they are not about the raw archetecture, but about archetectures that follow its general theory.
And Yes, I want quantum computers, but lets leave them out of this discusion.
End Disclaimer
We need this type of chip, because, realy, our current chip archetectures can only scale so far. They have internal bottlenecks, and IO bottlenecks, and though we keep squeezeing more and more out of them, WE CANT KEEP IT UP FOREVER.
So, what is the best archetecture theory we have? What is the most we can squeeze into and out of a processor of a given size?
Well, ultimatly, that is a question of IO. Personaly, I think this form of chip is the best 2D approach (though maybe some wacky fractal aproach might be better), but even it is limited by it's own IO, and keeping all the processor units busy becomes harder and harder with each row and collumn you add (at a damn fast rate).
So, what I am ranting about is that we need this, but we need it to have (at some future time when we can build such a thing) Depth as well, so that we have a smaller bottle-neck, because the area/perimiter ratio is much worse than the volume/surface ratio.
ex:
a square processor with 1,000,000 cells has 3,996 External cells for IO, though the 4 cells in the corners only pipe to other external cells, and aren't really useful (though you leave them in, just in case)
a cubic processor with 1,000,000 cells has 58,808 external cells for IO, with 8 corner cells.
The average distance between cells is also MUCH smaller, allowing for more efficient internal communication.
which one is going to have an easier time connecting to the outside world?
my $0.02
-Crutcher
-- Crutcher --
#include <disclaimer.h>
For our FASTEST computers, we cannot go with pure optical computers, because there are a conditions in which an optical switch is going to be SLOWER than an elctrical one, and have to work on higher energy levels. And If we reach the level where we NEED 3d chips, that will be a liability.
On Cooling, silicon based chips could still be built 3d, if one laid a lattice of a VERY heat conductive material through them (like gold or platinum) and posibliy dunked them in some nitrogen.
In short, lets get some hairy golf balls into our computers.
-Crutcher
-- Crutcher --
#include <disclaimer.h>
what did you think of the book?
Unfortunately, the "subtle properties" aren't consist from chip to chip. That is, the chip manufacturer guarantees that certain properties are the same from chip, and this search process wound up using properties that weren't in the set.
So do I (their website also looks very amateuristic), but it's interesting anyway (to me); it's not just the speed that makes this technology interesting.
0x or or snor perron?!
I believe Starbridge Systems has already sold a supercomputer with a FPGA processor and is developing what they call "a new personal supercomputer that will change the PC industry forever". This has already been posted on /. before. Still very interesting though. They also say "SBS's Hypercomputer systems can emulate virtually any hardware, including other supercomputers", so running Linux or *BSD on it shouldn't be much of a problem :)
0x or or snor perron?!
Also try looking here, I think they were mentioned on /. a while back. They claim to have a "Hypercomputer" that is rated at an overall sustained performance of 100 TFLOPS (100 trillion 32-bit floating point operations per second). Also they say that it takes up 4 cubic feet of space, weighs 150 lbs., and plugs into a 110-volt wall outlet. Pretty cool.
h tm
Starbridge Systems
http://www.starbridgesystems.com/home/mainpage.
I'm pretty sure this is the company you remember.
h tm
http://www.starbridgesystems.com/home/mainpage.
[Apologies if this sounds familiar to long-time readers; I've said this before and I believe it bears saying again.]
In addition to the lower native gate speed and inefficiencies of cell-based logic of FPGAs vis a vis full-custom processors, there's a serious problem with the time it takes to reprogram an FPGA. To put this in perspective, let's say that the time to perform computational work can be expressed as AX+B, where A is the time to perform an operation, X is the number of times the operation is repeated before moving on to a different operation, and B is the time to program that operation into the processor. For a traditional processor, B is zero. For an FPGA, A might be smaller than it is for the traditional processor, but B is very large. It doesn't take a rocket scientist[1] to figure out, therefore, that FPGAs win when X is large, i.e. when a task is very highly repetitive. There are a lot of tasks that fit this mold - audio and video processing, discrete-element simulations, etc. - but many of the most common everyday computational tasks you and I might face do not. For those cases, reprogramming overhead would be a killer.
Is there hope? Yes, absolutely. Lots of people are working on faster reprogramming, because it's known to be the One Big Problem in reconfigurable computing. Even better, work on partial reprogrammability is increasing. This is really cool because it would essentially allow you to dedicate part of the processor to functions you always need[2], and then use the rest to cache logic very much as data is cached now. In its simplest form, this could mean that all the parts of a traditional processor except for the actual functional units are permanent, and the cached items are instructions much like the instructions we have today. Need a population-count instruction? Allocate logic space and an opcode, reprogram the space, and voila! When you no longer need that instruction it'll fall out of the cache to be replaced by another instruction you do need. Of course, when the von Neumann model itself becomes the bottleneck then maybe the cached items would have interfaces other than instruction opcodes and register files, but defining those interfaces to allow the sort of logic-caching I've described is still a major conceptual problem worthy of a doctoral thesis or two.
[1] What's so special about rocket scientists, anyway? There are plenty of professions nowadays requiring greater knowledge and skill.
[2] The permanent part could even be implemented full-custom style, while the reprogrammable part remains cell-based. Altera had something called an SPGA which was like this, but I can't find it any more.
Slashdot - News for Herds. Stuff that Splatters.
Sure FPGA's are incredible things - rewire them do be whatever you want. Same thing goes for erector sets. Hell, I'd bet you could build a interstellar rocket out of erector sets if you had enough of them, and knew how to do it....
Something similar occasionally happens with artificial neural networks. I've read about two seperate projects, one involving vision and other language processing, where the researchers trained the networks to mimic (simplified) human abilities. Pattern recognition and visual attention on the one hand, some understanding of grammar on the other. In both cases the networks were more or less randomly wired at the outset and trained in the dark (without direct intervention by the researchers.)
When they finished the training and cracked open the black boxes, they found that the networks were nearly identical to the corresponding parts of the brain. The visual systems had organized into layers and hemispheres, while the linguistic network was organized geographically by word type--verbs in one area, nouns in another--and by sub-type (object/subject, proper and improper nouns, etc). AFAIK, they haven't figured out how it happened.
There are some interesting implications in all of this.
It was an okay book. I prefered Shakespeare, but it wasn't bad.
ah yes, or the . . .you posted this one last week
Yeah, those and the "if you're a devoted fan of [insert company, "geek" celebrity, etc.] you would have seen this already" and/or "/.'s so slow.. " blah, blah, blah
Also, this seems inevitable when some new software is released, or in response to the d.net cracking situation:
"I tried to tell them already, but they didn't want [my input]/[to give me credit]/[to add another name to their credits list]".. the been-there-done-that attitude.
Insert mind here.
Wasn't this the promise of DSP chips when they were introduced a few years ago?
I remember at that time DSPs were exhalted for their reprogramability and speed. It seems that all most consumers got out of it were software-driven WinModems.. (although I know there are a lot of specialized DSP applications out there).
Will FPGA chips be relagated to similar specialized tasks (like video compression or speech recognition) or will they truly be useful for general purpose computers?
FPGAs with high gate counts (e.g. Flex 10kXXX series) are expensive, and physically quite large. The other problem involved with this is the compilers for FPGAs pretty much suck at laying out the wiring between gates. You end up with layouts that not only waste most of the space available on the FPGA, but are also an order of magnitude slower than you want.
Don't get me wrong. FPGAs are great for prototyping, but for real speed, ASICs will always be the best.
In one of my less-paranoid, more-creative moments a few months ago I found myself thinking about Open Source and Linux -- that there might be some potential for the Linux platform enabled by FPGAs that I haven't seen described or pursued elsewhere.
Ask yourself the question: What is the fundamental architectural difference of an open source environment versus the traditional proprietary-binary environments of the last two decades? Are there any new assumptions in this new era that enable something different? Well, obviously now the OS and hardware can reasonably expect, if not mandate, access to the source code, not just the binary code.
Putting aside all the well-characterized FSF/Raymond reasoning for a sec., could you take advantage of this source-code availability to somehow build a faster, more efficient platform?
I've wondered whether this is indeed possible with FPGAs.
Since with FPGAs, you can actually configure the circuits to perform a specific algorithm which might be faster than performed by general-purpose circuitry, and since the FPGA can be programmed as often as needed by having a C compiler generate the appropriate netlist and send it to the FPGA, why not build a run-time Linux environment that on-the-fly recompiles the FPGA circuitry for the specific tasks (processes) being executed?
I've glossed over the various reasons why this isn't a cake-walk as anyone with FPGA expertise would realize, but I would be interested in an FPGA expert's assessment of either A) why this will never work, or B) what the top barriers to overcome would be. Is the gap between general purpose CPU clock rates and FPGA clock rates too great to ever realistically be surmounted in such a scheme? There's a big payoff for FPGA vendors if they could ever figure out how to make a competitive general-purpose platform; from an open source perspective, a platform that requires open source to deliver faster performance than Wintel would likewise be quite attractive.
--LP
There's a really interesting article on New Scientist, Creatures from Primordial Silicon, on the application of genetic algorithms to FPGA chips. In this case, the researcher was able to let natural selection design a chip that was capable of producing a 5v output when he said "Start" and stop producing the output when he said "Stop".
The cooler part is that no one can figure out how the chip works; he didn't implement a clock -- one evolved using fewer components than the simplest example given in any engineering text. There are a few components in there that don't seem logically neccessary, but their removal results in a non-functional chip. Theoretically, using the evolutionary procedure allowed the chip to utilize subtle properties of the materials used in its composition, like the small resistance changes caused by heat or electromagnetic induction.
It's a good read if you're interested.
"h3y 1c3 kr34m!! 4r3 j00 3r33+!?" "y3z crackd, 4nD n0w 3y3 w1lL h4xx0r j00r m0u+h! h0h0h!!0"
Does this remind you of the Cyberdyne Systems chip from Terminator 2 or what?
http://www.sciam.com/1999/ 0899issue/0899agarwalbox1.html
;)