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Even though slavery is forbidden the most common form of it is through aquired or even inherited debts, and there is no better way to tax money of someone than to drag him through the US legal system - no matter how legit the case may be.

I stumbled upon a fresh article on this subject:
Zombie contracts in the EDA industry

As a former employee of one of the big three in CAE (Mentor Graphics) and as someone who keeps in touch with people in the industry at companies such as Synopsys, Cadence, and (yes) OrCad, I can testify that building this type of tool requires a large amount of specialized knowledge, effort, and testing to bring to life. And, when the tool works, the job has just begun as you need models, both device and process, to feed them. It is a testament to the dedication of a few very motivated people that projects like Open Cores (which seems to have been down for the past few days), GHDL, and others are made available to the public.

Given the size of today's designs, the days of putting together a four-state logic simulator in a couple weeks of work is long over. Given the technical depth needed to do this work today, it's not a surprise that this is a niche market where open source isn't doing very well.

65 nm promises to be a similar order of magnitude of problems. I'm not convinced, and I won't be until I see more details on what problems have been encountered in the rush to 65 nm, and how they were overcome.

Don't be silly. Here is the change in question.

System Verilog

Pretty much a HDL of the future that's still being developed, has all the best features and none of the bloat of VHDL and some other HDL languagues.

..is where this sort of stuff really belongs.
A family member is working here, and the biggest markets they have lined up for their new design are the mobile-phone vendors, and image processing. They aren't interested at all to pitch it towards general-purpose computing.

Interestingly enough though, the software-defined-radio teams have been eyeing the product with drool in their mouth ever since it was demonstrated. Said family member remembers trade conventions the company's been to, where the SDR teams showed up and literally begged for a test chip to play with.

I love PostgreSQL, have used it in a small (million-record) transactional application with great success, and am pleased to see the implied advocacy of having .org run on it. Nonetheless 2.4 million records is hardly enterprise-level stress. I would really like to see some serious benchmarks against Oracle. My tests on a small PC-based Linux server last year showed that pg beat Oracle mainly because the bloat of Oracle caused excessive thrashing, but on a large mainframe-type application - billion-record type stuff - I simply have no idea. A couple of years ago some benchmarks were published on the web but got quickly taken down by Oracle under threat of lawsuit - their license doesn't allow publication of benchmarks - and I never got to see them. I think this is wrong. Perhaps the recent ruling against EDA benchmark restrictions will open a door towards Oracle benchmarks?

• Any FPGA design can be converted into an ASIC design with minimal or zero modifications, and usually with a substaintial performance improvement. There are several companies out there that will take your synthesized netlist and give you an ASIC, and will do it cheaply. The FPGA vs ASIC break even point is in the ball part of 100,000 units and it's getting better every day.

• While it may take a Virtex-II to compete with a decent accelerator for all applications, it may be possible to have multiple optimized implementation that are specific to specific applications. For instance, you could program the FPGA with an image optimized for 2D applications for general purpose use and then reprogram it with an image optimized for 3D applications as soon as you run your favorite FPS. Also, A decent sized Virtex-II can be purchased for US $323 in single quantities, and roughly half that in quantities of 1,000 or more.

• Design tools from Xilinx are less than US $1,000. And if you use their web-based tools, they are free.

• The circuit board would not be a major problem. I recently designed a PCI board with an FPGA and SDRAM on it (and wrote the FPGA code) and we got our 10 board for less than US $2,000. Most of this is set up cost, of course, so it gets really cheap really quickly as the numbers go up.

• 266 Mhz DDR RAM really only runs at 133 Mhz, and high end FPGAs can run at 300 Mhz. FPGA vendors often have hardware build into the FPGA to suppport high speed interfaces like that, or provide HDL source so that you can implement your own.

• Even if it takes 5A to run these chips (slightly excessive IMHO), the requirement is at the core voltage (1.5V for the Virtex-II mentioned earlier). With a 85% efficient switching regulator (typical), that would equal 2.7A @ 3.3V or 1.8A @ 5V or 750mA @ 12V (all of which are available on the AGP connector). Besides 5A @ 1.5V is just 8W after you include the switching inefficies, and you probably have at least a 300W power supply, so it's less than 3% of your total power budget.

• We do need to factor in assembly costs, which for a prototype run of 10 boards is going to to be about $3000 total, but the costs get really cheap if the quantity goes up, especially if the through-hole components are soldered by the enthusiasts who buy these cards.

  So, you don't really need all that much capital, and the open-source development model will provide the large teams of engineers.

  Unfortunately I can't contribute to this project because I code not in VHDL but in Verilog (which gets a lot more done for the same amount of effort in my opinion and others here and here).