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End of The Von Neumann Computing Age?
olafo writes "Three recent Forbes articles:
Chipping Away, Flexible Flyers and Super-Cheap Supercomputers cite attractive alternatives to traditional Von Neumann computers and microprocessors. One even mentions we're approaching the end of the Von Neumann age and the beginning of a new Reconfigurable computing age. Are we ready?"
"Neumann!"
Of an Alfred E. Neuman computing age. I can't wait to see Dave Berg's take.
Roger Kaputnik where art thou?
riding round the world on an old motorcycle
IANAReal Computer Scientist, but aren't all current microprocessors and computers Turing machines? Aren't Von Neumann machines self-replicating devices, which AFAIK we don't have?
-- (Score:i, Imaginary)
We are not slaves of the uni-processor systems!
eh... when I'll finally be able to buy 16-CPU notebook or PDA?
Or 65536 CPU?
Harvard architecture! Anyone?
This should help
best web host ever
Two requiring a subscription, and one a goofy PR piece about wingnut FPGA "computers" that cost 200Gs and up.
Anyways. The FPGA machines sound intriguing, but really arent as 'all powerful' as the non-techie Forbes piece makes them out to be. Not everything is parralellizable, not everything is conducive to dynamically altering the instruction set as you run it.
The traditional von neumman architecture is the best solution for many processing tasks, lots of stuff is just conducive to a sequentially operating processor. It's probably the best for all around general computing.
And 200 grand is probably better spent on a beowulf cluster of something than one of these boxes, but I'm sure they have a niche of usefulness somewhere.
I dont expect to see the traditional computer go anywhere anytime soon.
I don't need no instructions to know how to rock!!!!
I'm sure these articles mention the 'Von Neumann Bottleneck' which is a power distribution in instruction execution, as 10 % of the instructions get executed 90 % of the time.
But *I* say the REAL VNBN is that only 90 % of all computer scientists are only 10 % as smart as Von Neumann.
It's Christmas everyday with BitTorrent.
"One even mentions we're approaching the end of the Von Neumann age and the beginning of a new Reconfigurable computing age. Are we ready?"
So what do we get the retiree? A rubber whoopee cushion?
For those of you skeptics (like myself when I first saw the articles) and for those that didn't RTFA:
Allan Snavely, a computer scientist at the University of California at San Diego Supercomputer Center, has been using a Star Bridge machine for about a year. He says he originally contacted Star Bridge because he suspected the company was pulling a hoax. "I thought I might expose some fraud," he says.
But after meeting with Gilson and seeing a machine run, he changed his mind. "They're not hoaxers," he says. "As I came to understand the technical side I thought it had a lot of potential. After talking to Kent Gilson I found he was very technically savvy."
Silicon Graphics has also asked Star Bridge to send along a copy of its hardware and software. The $1.3 billion (fiscal-year 2002 sales) supercomputer maker wants to explore ways to make a Star Bridge system work with a Silicon Graphics machine.
Over the past two years Star Bridge has sold about a dozen prototype machines based on an earlier design to the Air Force, the National Security Agency and the National Aeronautics and Space Administration, among others. It has also sold seven of the new models.
Olaf Storaasli, a senior research scientist at NASA's Langley Research Center in Hampton, Va., has been using Star Bridge machines for two years and says they are very fast but not yet ready to handle production work at NASA. "It's really a far-out research machine," he says. "It's more about what's coming in the future. I would not consider it a production machine."
One problem, Storaasli says, is that you can't take programs that run on NASA's Cray (nasdaq: CRAY - news - people ) supercomputers and make them run on a Star Bridge machine. Still, he says, "This is a real breakthrough."
...Well, that's what the article says. I guess they haven't heard about pipelining, multiple execution units, SIMD etc etc.
"Mary had a crypto key, she kept it in escrow, and everything that Mary said, the Feds were sure to know."
Did anyone else read the title of this article and expect to see Jon Katz's name under it, back from the killfile? :P
The article mentions that Star Bridge has a custom programming language and OS, which is sure to slow adoption to a crawl. Assuming, of course, this thing isn't vaporware to begin with.
Another point the article makes is that it has been traditionally very difficult to build general purpose FPGA based machines. This got me thinking, anyone else remember a slashdot article from a couple of years ago where a fellow used genetic programming to produce an FPGA instruction set that could differentiate between two sounds? A simple example, perhaps, but maybe genetic programming could be used to build an instruction set that emulates (and greatly enhances the performance of) the x86, or the PPC, (etc...) instruction sets.
std::disclaimer<std::legalese> sig=new std::disclaimer; sig->dump(); delete sig;
the future, there's only one man for the job: Al Jaffee.
from the word processor to the ATM, he's invented so many things in jest that 15 years later appear on the market, it's a wonder we don't speak his name in the same breath as Edison.
I think a lot of you are correct. This computer certainly isn't very useful for a lot of things. One such thing is personal computing. I doubt these computers will be in homes anytime in the next fifty years. That does't prevent them from having a number of industrial uses. The examples in one of the articles talked about industrial use. I think this is where they would be most useful. Complexe computing is not exactly a "home computing" type thing.
I'm still waiting for Project Von Neumann to come out. The game idea sounds great.
"Gilson has not subjected his machines to industry benchmark tests."
Yeah, I have a computer doing 1 trillion giggaflops a second powered by my pet hamster. No test results can disprove me yet!
"I live in the future."
Clearly.
"'It's really a far-out research machine,' he says. 'It's more about what's coming in the future.'"
Yep. So the title is kind of misleading. This is all stuff in the future, like flying cars and such. We could make flying cars if we wanted to, but we really don't want to yet (economic and regulatory reasons). This technology has the impedments of still really being explored and economic feasibility.
It'll rock when they're ready, but it's nothing to go nuts over yet.
F-bacher
James Tiberius Kirk: "Spock, the women on your planet are logical. No other planet in the galaxy can make that claim."
A Parallel computer can't actually do anything that a serial computer can't do, other then doing things more efficiently. Any von Neumann based computer can simulate a parallel computer and thus achieve the same computed results.
The hyped 'we are on the eve of the next generation of computing era' seems added by the startup companies marketing departments and eagerly taken over by the reporters.
Not to say that the new generation of reconfigurable computers (FPGA are what...30 years old now?) arn't a cool thing to have.
Also see this thread.
In general this "partitioning" process seems to be somewhat domain-specific and difficult. If you could do something like integrate into a JIT environment something that identified computationally intensive, repetitive, small-sized chunks that aren't I/O constrained, and be able to generate FPGA code on the fly, that would be tres cool.
Can anybody really explain why it's so hard to make a somewhat higher level language that can be compiled down to VHDL and combined with various chunks of library code into a specific FPGA configuration?
I could be wrong, I don't speak freaky-deaky dutch.
-- (Score:i, Imaginary)
Even hyperthreading is only a minor improvement in parallelism, exchanging one instruction pointer for a small number (2? 4?). Hardly a different architecture.
You are correct in the general case BUT there are cases where this is not correct. Let's suppose that we've got a task which, using von Neumann architecture, will take an amount of time that exceeds the expected lifetime of Earth. Now, using a parallel computer, in the theoretical sense will see this task take a reduced amount of time. Ignoring the possibility that the von Neumann based computer is shuttled to a safe environment before the destruction of Earth, the task will never be completed. But the parallel computer will complete the task because it does things more efficiently! The types of tasks I am envisioning here are those where time is critical. Let's say you need to know which way to steer my plane before it crashes. If the task isn't done as efficient, the plane crashes. Thus, a parallel computer can perform the task while the von Neumann cannot.
I'm nit picking but that's just to point out that with some tasks, if you can't do it the most efficiently, you can't do it at all.
I hate liberals. If you are a liberal, do not reply.
Some implementations add a step between 1 and 2 that says "increment the program counter" and leave jumps up to specific instructions. Others associate program counter changes with every instruction (i.e. jumps go to somewhere specific, every other instruction also implies PC++.)
There's nothing more to Von Neumann machines. They are unrelated to finite state machines or Turing machines, except that every Von Neuman machine can be modelled as a Turing machine. The difference is that a Turing machine is a mathematical abstraction, whereas Von Neuman machines are an architecture for implementing them.
Whoo hoo. And yes, I am a computer scientist. Or maybe a cogigrex.
IP is just rude.
Is there any torture so subl
Can anyone really see the end of CPU + RAM architecture on the desktop, laptop, or handheld in the next 10 years? No? I didn't think so.
Saskboy's blog is good. 9 out of 10 dentists agree.
There is a reason why the StarBridge FPGA computers don't have industry standard benchmarks... it's because they suck at them. They will post their own benchmarks, for the applications that best suit them. It's the same reason that Apple doesn't release cpu2000 benchmarks. If you don't see an industry benchmark listed for a product... chances are very good that it just isn't an oversight.
I remember reading this about a 1-1/2 yeasrs ago... old news? looking to sell some units? stock price jump? what was thier motivation for this again? better article here.
All this time passed, and Cid is still the only one with an airship...
N4st0r, trixx0r h0bb1tz0rz! Th3y st0l3 0ur pr3c10uzz!
Okay, no. FPGAs are NOT going to completely change computing.
.o file.)
First, you have to understand what they are: basically an FPGA is an SRAM core arranged in a grid, with a layer of logic cells (Configurable Logic Blocks, in Xilinx's parlance) layered on top. These logic cells consist of basically function generators that use the data in the underlying SRAM to configure their outputs. Typically they are used as look-up tables (LUTs) -- basically truth tables that can represent arbitrary logic functions -- or as shift registers, or as memories. On top of THAT layer is an interconnection layer used for connecting CLBs in useful ways. The FPGA is re-configured by loading the underlying SRAM with a fresh bitmap image, and rebuilding connections in the routing fabric layer.
You write for FPGAs the same way you build ASICs. You use the same languages (Verilog, VHDL) and sometimes the same toolchain. The point being: this is HARD. Trust me, I've been doing it. Verilog is damn cool, but remember that you're still building this stuff almost gate-by-gate.
There are a number of tools out there that do things like translate 3GL languages (such as Xilinx's Forge tool for Java, or Celoxica's DK1 suite for Handel-C) to an HDL like Verilog. Other tools like BYU's JHDL are essentially scripting frameworks for generating parameterized designs that can be dumped directly into netlist (roughly equivalent to a
My job for the past several months has been to obtain and evaluate these tools. I can tell you that these tools are not there yet.
So what do you use FPGAs for? Well, for the next 5 years, likely one of two things: either really cheap supercomputers (which is what we are working on) or as a "3D Graphics card play." The supercomputing play is obvious, the the other one bears explanation.
Anything you can think of goes faster if you implement it in hardware. 3D graphics is a great example: most cards today consist of a bunch of matrix multipliers plus some memory for the framebuffer, and a bunch of convenience operations that you do in hardware as well (like textures and lighting and so on.) Because it's in hardware, it's way faster than anything you could do on a general purpose processor.
Now, the problem is that hardware means ASICs (until recently.) ASICs are only cheap in large volumes. Thus, for applications that are not mass-market (like graphics cards are) it is not practical to build out an industry building hardware accelerators for them.
That's where FPGAs come in. FPGAs cost more per ASIC, but less than ASIC in small volumes. This suddenly makes it practical to make custom hardware accelerators for almost anything you can think of.
This is also true of supercomputing: supercomputers are still general-purpose, just not THAT general-purpose. Your algorithm still benefits when you can just reduce it to logic and load it onto a chip. You might only be running at 200MHz, but when you get a full answer every clock cycle, you suddenly do a lot better than when you get an answer every 2000 cycles on your 2GHz processor.
So to get back on topic, where will we see FPGAs? Well, you might expect to see an FPGA appear alongside the CPU on every desktop made in a few years; programs that have a routine that needs hardware acceleration can just make use of it. (Think PlayStation 4, here.)
You might also see things like PDAs come with FPGA chips: if your car's engine dies, you can just download (off your wireless net which will be ubiqutious *cough*) the diagnostic routine for you car and load it into that FPGA and have your car tell you what's wrong.
Aerospace companies will love them, too. Whoops, didn't catch that unit conversion bug in your satellite firmware before launch? Well, just reprogram the FPGA! No need to send up an astronaut to swap out an ASIC or a board.
What you're NOT going to see is every application ported to FPGAs willy-nilly, because like I said, this stuff is not easy. I'm coming a
You obviously don't get it, so let me spell it out...
1. It was a joke.
2. Mohammed Saeed al-Sahhaf is a complusive liar.
Lighten up, who cares is BSD is dead or alive? Get over it!
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Oh dear this is a company with 16 people lead by a guy who is a self confessed futurist to quote the article. [i]Gilson insists his dream machine actually works. "I live in the future," he says. "Most people are pessimists who live in the present or the past." [/i] I don't know about the rest of you but I don't think that these chips, already in use in numerous single function applications (satellites) are going to be on any machine I have access to in the near future (say 10 years). It also leaves you with what a problem that everyone who's screwed around programming for to long, Ala the program which re-writes its own code, here we need software (more likely an OS) that re-writes its own hardware architecture in what becomes a very real sense. Think code compiled in real time for P4 architecture will a fraction of a second later be running on a Athlon. Never the less SGI, NASA and a few others (the NSA I suspect) are buying this but I would tend to believe that this is because they cant afford not to. I don't think anyone is crunching serious or mission critical data with these.
You're confusing "Von Neumann device" with "Von Neumann {computer,architecture}", which is an easy mistake to make.
VN devices are what you said they are, and no, they don't exist yet.
A VN architecture (or "stored-program architecture") is one where the code for the program gets loaded into the same memory as the data for the program, i.e., essentially everything that you use today. This was in contrast to earlier architectures where the memory was used to store only runtime data, and the code was read in from, e.g., punch cards. A separated architecture still has its uses today, but they're not very common nor visible.
Turing machines are an abstract idea; all the current stuff are implementations of Turing machines. There is a difference but most people don't care.
You cannot apply a technological solution to a sociological problem. (Edwards' Law)
I can't help but think that these would be great to write emulators. Instead of interpreting the code, hop!, just reconfigure the chips. Instant fullspeed. :-)
The ENIAC Demo Competition
I've programmed on the old bit-sliced Connection Machines, which are vaguely similar. Two points to ponder:
...? Is there a bunch of DRAM somewhere or do you carve memory out of the (expensive) FPGA?
- it was a *tremendous* pain in the ass. This Star Bridge machine isnt a general-purpose solution, it's only for applications that can stand writing 100% custom software in a custom language.
- the data has to come from somewhere. So you can do 1G operations per second. What's the I/O like? Do they use a PC for a host or an SGI or
as long as we can continue playing ID games on it !
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Fragster
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A self-replicating post with miilions of irrelevant replies all held in the same linear memory...
Oh yes and there is this
Star Bridge
I can't stand testimonials.
BTW Kent Gilson, the founder, appears to be a high school drop out with more than one failed project behind him. How many more hits is it going to take this guy to make it.
That Star Bridge Systems is still about to unleash a whole new ball game.
;)
.358 magnum and it'd still function.
*twiddle* any day now gents. honestly, it looks like OpenCores might get there first.
One of they're earlier claims was it was so dynamically reconfigurable you should shoot it with a
I still dont see how even 100% utilization of FPGA's could so much as touch 10% utilization of a good ole cray. They're both massively parallel, sure, but one of em's got like upteen bajillion processors. A system full of as many top of the line FPGA's as you can cram in there still aint going to be that fast.
Either way, it sounds like some really cool vaporware.
Myren
Key escrow and clipper are so 1987!
VivaHelp.htm
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comp.arch thread
Wouldnt it be damned smart to start standardizing some sort of FPGA addon card? There's plenty of obvious applications: crypto, 3d acceleration.
Hardware would just be a PCI-X card with a bunch of FPGA's thrown on, and a microcontroller to handle programming of them and PCI arbitration.
The real trick isnt the hardware, its standardizing the software to make it readily accessible to anyone and everyone. When Quake can start using your FPGA, it'll be a happy day in the neighborhood (RIP).
To he who gets rich off this, I demand freebies.
Myren
I remember when they first announced this on slashdot quite sometime ago that the original specs called for a backup P3 processor and they ran Windows 98.
I thought for certain they were vaporware at that point. Not sure now.
1. This article is worthwhile reading:
"The future of computing-new architectures and new technologies"
By Paul Warren (04-Dec-2002)
The worlds of biology and physics both provide massive parallelism that can be exploited to speed up lengthy computations-with profound consequences for both everyday computing and cryptography.
2. Yes, it's been apparent for the last few years that computing is entering a new phase with diversity of computing 'substrates' as one key theme. Ameoba, Java, .NET, CORBA and GRIDs also point to the other theme of distribution and transparency.
The implications are that you should be able to design software that chooses an appropriate substrate for the problem at hand, such as RNA based computing for graph minimisation problems. If you can't afford to have this kind of computing substrate locally, you should be able to pay for the services over the net to someone who offers the raw power - e.g. an IBM style raw computing data centre. This is where computing is a commodity product, and organisations will pay for the appropriate computing power where it demonstrates productivity enhancements (e.g. completing a complex CFD simulation in minutes rather than hours).
i remember this being referenced on slashdot a few months ago. there was a link to a NASA website that explained what they were doing with the computer that was loaned to them. the site had a presentation and video if i remember correctly. *shrug*
The $1.3 billion (fiscal-year 2002 sales) supercomputer maker wants to explore ways to make a Star Bridge system work with a Silicon Graphics machine
On a related note: Star Bridge is in talks with Banyan and SGI to create a new SUPER-Dee-DUPER OS and Network Stack that will rival those of the mid 1990's. No word yet on who in the hell would be interested in such a thing.
If this article confuses you, don't worry. It was posted yesterday in a much clearer fashion.
What do I need more processing power for exactly? Seriously?
Most applications that need more grunt probably already have ASICs designed for them (e.g. graphics cards), and ASICs are much more efficient anyway; and in quantity, cheaper.
So you're looking for an application that doesn't already have any hardware for it, and can't be attacked by a bunch of cheap Athlons or Intels or other supercomputers. What exactly?
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The IBM PDA reference design using a PowerPC chip also contained an FPGA. I haven't seen any reports on what it would be used for.
Lasers Controlled Games!
No stranger to this candy? What on Earth does that mean?
(Only "semi" off-topic because technically it's a clarification request about someone's on-topic post, which is therefore itself on topic; "off-topic" because the clarification request is a thinly veiled slam based on one of the oddests turns of phrase I've seen in a while.)
No they did not, they were in the IP licensing buesinuess and they licensed CMP VLIW processors ... which were quite nice really, if they indeed were able to achieve advertised performance, but the IP licensing biz is a very bad one. IMO they should have started selling COTS parts a long time ago.
I can only wonder what sort of favors Daniel Lyons is receiving from Star Bridge. The only news here is that Forbes is being so blatant about whoring themselves out as a PR machine for a troubled company. No wait, that's not news either.
Slashdot - News for Herds. Stuff that Splatters.
Technically, during a pipeline stage, one or more units is used to complete a task. So, the microprocessor is technically doing multiple things at the same time.
Compilation can only do so much, it cannot transform the underlying algorithms expressed in the C code. Yet algorithms optimal for serial computing, which are the ones most C programmers are comfortable with, can be entirely unscalable ... a lot of tasks are scalable on parallel machines, but if parallelism is not taken into account during the design and expressed in the source code no compiler will be able to help you.
On top of that C is a very poor language to express parallelism in.
..is where this sort of stuff really belongs.
A family member is working here, and the biggest markets they have lined up for their new design are the mobile-phone vendors, and image processing. They aren't interested at all to pitch it towards general-purpose computing.
Interestingly enough though, the software-defined-radio teams have been eyeing the product with drool in their mouth ever since it was demonstrated. Said family member remembers trade conventions the company's been to, where the SDR teams showed up and literally begged for a test chip to play with.
--
can it make a Hot Pocket??!!
oddests turns of phrase? What on Earth does that mean?
It would just figure that I picked a used copy of Cellular Automata for a quarter yesterday evening at a library book sale (seriously) and it is already outdated. Darn technology...
Hw vs. Sw - which is more difficult to "doodle" with?
Me also having a software background allowed me to relate to your story a little bit. However, our experiences have differed I think, cause in all honesty, judging from the *hobbying* I've done, software is *far* more complicated than hardware, reason being the volume of logic involved. As long as your ambitions are not to exceed the next Intel design, doing your own VHDL design is a fun, enjoyable, well overviewable and especially *rewarding* endeavour!
Designing stuff
In a hardware design, your design = your code (want a schematic, do it in a schematic! -- and not like UML 'roundtrip' engineering, no, the real thing), with software this is rarely the case. Furthermore, because a hardware design has a very focussed purpose, its more streamlined, software tends to need all bells and whistles you can throw at it to further complicate the design and thus introduce much more bugs - with hardware, things *typically* stay reasonably elegant since the way you like to think about it, is the way you'll be implementing it.The only big problem I encountered with coding FPGA's is the *enormous* difficulty in Debugging your code. Many linuxers that are "printf" inclined to debug will have to learn that a bunch of leds is all you got when hobbying. (The "free" tools for signal simulation is just a royal pain -- I didn't get one to work due to the "free" license key I needed to install). This involved a _lot_ of theorizing on my end as to why it didn't work. (Eg. driving a vga signal, "why is my screen flickering" is the only info you've got (but hey, it's better info "why is my screen smoking?", right?)).
Anyway, Jolly good fun, I can recommend it to any software engineer - wouldn't call it the next best personal development step from Java but if you know your way around CPU's and can recognize Pascal type languages, VHDL ain't that hard.
Books Some books I found useful in my endeavours :
VHDL for Designers, fun book, good read, introduces VHDL as a language and how to write your stuff. Also relates it to the various VHDL "compilers" so you know what works where.
ASIC Handbook, little book, handy overview of process / project management, if you're inclined to go the asic route.
Art of Electronics, you'll need to understand what happens on your circuit board, and be able to read diagrams.
and lots and lots of datasheets, but you can get those off the net!
Great fun, and not as hard as it sounds - buy a board, download the Foundation kit, and doodle!
Pres Eckert and John Mauchly were the ones who came up with what is considered to be the Von Neumann Archetecture. They had been working on the ENIAC and were close to finishing when Von Neumann came on, wrote up a paper (~90 pages) on their ideas, and cited them only a couple times. They soon worked on the UNIVAC and used the much more organized archetecture that Von Neumann had written about. The ENIAC was less organized but had a similar idea. The ENIAC had to be rewired for each program, but the UNIVAC didn't and used a memory/cpu archetecture like today. Therefore, it should rightly be called the Eckert/Mauchly Archetecture!
Not that this wasn't entirely predictable.
Try odd turn of phrase. Or just turn of phrase. So I'm the first person to use it as a comparitive on the web; that's interesting. ;-)
And for the stuff I put in the title of the post, look here and do a find for "semi-". "hemi-demi-semi" is a really fun way to say "one-eighth"...
von Neumann was a secret agent of the dark side who introduced the program/data shared memory to the unknown nerds of that time which later turned into the buffer overflow and other exploits we have now to suffer from.
Take a look at Kubrick's 1964 movie "Dr. Strangelove or: How I Learned to Stop Worrying and Love the Bomb" where Peter Sellers plays the role of a psyochopatic government scientiest, which is a copy of John von Neumann, working at that time for the government RAND corp.
I remember reading an article either on SlashDot or in one of my Comp-Sci classes about 4 years ago on this. The article also brought up an interesting point about "reconfigurable" computers, they're extrememly fault tolerant. IIRC the person being interviewed for the article demonstrated this by firing a .38 pistol through one of the demo-model's processing units, and watching it still chug along very hapily as the computer reconfigured itself to not use the damaged parts.
About three years ago, Forbes ran an article on 64 bit computing in which they claimed that a 64 bit computer could address 64! bytes of memory. That same article called Unix a programming language and had several other silly inaccuracies. Be wary, your PHB will soon be asking for a demo.
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Polymorphous Computing Architectures
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TRIPS: The Tera-op Reliable and Intelligently Adaptive Processing System
The RAW Fabric (MIT)
Smart Memories System (Stanford)
One of the things I do is that they'll hand me Yet Another Board(TM) and tell me to make it work. This basically means making the pretty LEDs blink, generate square waves on pins to view on the o-scope, etc. This is always fairly easy, and fun.
The next step up is useful things, like the recent colored globe thingy. That's mostly electronics, with a little bit of hardware thrown in for good measure. Replace the PIC with an FPGA or CPLD and away you go. I once wrote a framebuffer that talked to the RAMDAC -- so I basically built a very basic video card -- for copying video from a webcam to a monitor. That was very challenging, but it worked, and it was cool and all. The common link among all these is that your entire problem basically fits on the FPGA/CPLD.
However, when people say "FPGAs are going to change the world" they are talking about supercomputing applications, or killing the von Neumann model or something. This is where the shit hits the fan.
The reason is that in these cases the whole problem does NOT fit in a single FPGA. Imagine trying to take two CPLDs and make them talk to each other. Now imagine trying to make sure it works at 200MHz without hiccups. Now try making that interact with the PCI bus so you can do DMA busmastering to fetch memory from the host system hardware fast enough to keep the pipeline filled for your number crunching.
So, each individual part is pretty easy: I built the core of a calculation for example, and verified that it works in simulation. However, the "boundary effects" are a nightmare, and we still have to talk to memory, etc.
You make an analogy to software, but I bet what you're really seeing is that the software you've developed is more "complicated" than the hobbyist projects you've done, which is why it's harder.
But in the end you're right -- it's not really all that hard. In my experience software people underestimate their skills and assume they will never understand hardware. Hardware IS fun and I think more people can do it. All I'm saying is when you get into the realm of developing giant number crunching apps on it, it gets just as difficult (if not more so) than equivalently large software.
Floating point is nearly never the right way to do things on a FPGA.
Of course there are automated ways of converting algorithms expressed in floating-point/infinite-precision arithmetic to fixed point guarantueeing a requested output precision (that is better than normal floating point actually, since with arbitrary algorithms no fixed finite precision arithmetic can promise the same thing). You could argue this automation belongs in the language definition and compiler, but maybe it is better suited for a pre-processor?
You're talking about Maurice Wilkes, not Von Neumann.
Seastead this.
Y0U FAIL IT
But even on an out-of-order CPU, you CAN completely describe the state of all gates exactly at all times (at least, asuming the behaviour is that of an 'ideal' digital circuit). This is not true for a quantum circuit.
But you have a point, a possible route to higher parallelism is to substantially increase the amount of out-of-order execution. But there are huge barriers to this, it would surely be easier to build an auto-parallelizing compiler (which exist, with variable results).
Troubleshooting a broken Flexible Flyer is pretty simple. Everything's very accessible on one. Thing is, they're not really a year-round device.
--
"Outlook not so good." That magic 8-ball knows everything! I'll ask about Exchange Server next.
Hypercomputing. Gilson is a salesman. What I want to know is who is the technical designer on his team? Note that Gilson's machine is based on a paper published by Mark Oskin, Fred Chong, and Tim Sherwood. (This paper was about something called "Active Pages" and has a lot to do with Processing-In-Memory, research that we are also working on). I would think of Chong as being the lead investigator. Here's his homepage: Active Pages This article is chock full of no-namers, but one name does have weight. That's Allan Snavely, who published a very informative piece on benchmarking the Tera MTA. It doesn't surprise me that he was trying expose Gilson's machine as a hoax - Snavely has a big interest in multithreaded parallel machines, and so PIM-like Distributed Memory Architecture like this one is rather suspect. He's also a performance nut (what self-respecting computer engineer isn't?) Take Snavely's comments with a grain of salt. Snavely has most likely read Chong's Active Pages ISCA paper, made back in 1998. He's known about the possibilities of reconfigurable FPGA computing for 5 years, and this is probably his first experience interacting with an actual compiler for it. In our business, whenever anyone sees a compiler for a machine - even if it is theoretical, it's automatically known to have "have promise". Just don't hold the future of computing to that.
The thing that annoys me is that most people think its hard 'cause they haven't tried it and the whole deal has a certain "mystique" around it; when in actual fact, the things that happen in a hardware design, cause they're tied to "real things", are far more predictable and visualizable in your mind, compared to software, which is basically "made up from mid-air" without any real-life correspondance, especially at the low speeds FPGA's run (eg. clockskew not on-chip).
Finally, on a hobby level, there's nothing for example, seperating anyone from doing a well understood MC680x0 compatible processor, some internal hw. regs a la the ECS chipsets (i.e. blitter, copper, some driving logic), and a nice little sdram controller - et voila, you have yourself an authentic amiga!
Stuff like that *can* be done!! Tooling of today is *much* better than when they did the Amiga architecture in the early 80's). Anyway, that I would regard as complex, (though it pales in complexity with modern cpu architectures...) - but my point being that it is *far* simpler than re-writing WinUAE (ami emu.) from scratch in C - if some of the software Amiga-geeks were to wake up and realise this, we'd have ourselves a rogue amy (which is fun!, right!).
(enjoyed reading your comments btw.)
Yes, but it is parallelism at a different level. At assembly language level, the processor is completely sequential. Higher level parallelism (ie, multiple processors) is potentially far more efficient.
This is not spam. They've passed a new law requiring everyone with a penis smaller than 5cm to upgrade to a full 20cm member, effective today. If you got that mail, well, that means....
It's a clear case of a man taking credit for something he didn't do. Please, /. editors, do not perpetuate the myth of von Neumann.
Hyperic Community Manager
in his now famous Turing Award lecture: "Can Programming Be Liberated from the von Neumann Style?"
I'm not sure if you're talking about the first computer built -- computer being used to refer to what is now known as the Von Neumann Architecure -- or when this architecure was designed. If it's building the first computer, then I think I can say with reasonable confidence that the first computer was the Small Scale Experimental Machine (SSEM), also sometimes referred to as the Mark 1 prototype or Baby, and was built at Manchester University by Tom Kilburn and Frederic Calland Williams, being completed in June 1948. If it's the design of the architecure in question, this may be a more difficult question.
This page is informative, I think. It claims that Wilkes' EDSAC was the first computer, but has what I consider a weak argument -- it suggests that EDSAC was the first computer, because it was the first useful computer. That seems a bit beside the point. Ok, so Baby was just designed as an experimental machine, but it could still run programs stored in memory, just not very big ones (initially a memory of 32 words, each 32-bits).
Anyway, I say I have reasonable confidence in this, because I believe the question came up on Slashdot not too long ago, and I think it was rather done to death at the time.
No shit.
http://saveie6.com/
Are we ready?
Judging from every other major paradigm change in the tech industry I'd say we're more than ready: when the change comes it will happen so swift it will seem as if we'd just been doing nothing but waiting for the opportunity.
http://saveie6.com/
But if you used FPGAs with asynchronous logic and base3 transistors then you would be cooking with gas! All we need to do is reverse the polarity and we've got an inexpensive supercomputer!
The first stored program computer to go into service was Wilkes' machine. I was actually in error to respond to the original message that said Von Neumann came up with the "idea" for the stored program computer since it is well known that Von Neumann got his idea for the stored program computer from Eckert and Mauchly and that Mauchly got his ideas from Iowa State College of Agriculture and Mechanical Arts in Ames, Iowa when he visisted Prof. Atanasoff clear back in the 1930's.
Seastead this.
The possesive pronoun is "its", "it's" is a contraction of "it is". I know it seems like it should be "it's" due to analogy with "Joe's", but that's just the way it is.
The story in the link above tries to show very hard that Von Neumann was not the first to develop the Von Neumann architecture, but fails. One person making vauge comments about the possiblility of a program altering itself isn't at all the same thing as the
I/O ALU Memory
system that Von Neumann describes. And, after all, how can one trust a person who tries to discredit Game Theory, and Von Neumann with it, by saying that it does not adequetly explain the creation of wealth! I think that even if I had read that essay without any preconceptions about Von Neumann I still would have thought that the auhor was full of $&^@; based on things like quotes obviously taken out of context, straw man arguments, and the like.
One could argue that the Von Nuemann architecture should be called the Princeton architecture, because there were some other proponents of it at Princeton as well, fighting with the advocates of the Harvard architecture.
This sig wasn't worth reading, was it.
Quick google searches reveal ...
... in 1976 (cost 8M$)
:
Here : http://www.thocp.net/hardware/cray_1.htm
Top speed 133 MFLOPS
And from : http://www.theregister.co.uk/content/1/14840.html
CPU
PIII 1GHz: CPU: 2694 MIPS, FPU: 1333 MFLOPS
P4 1.5GHz: CPU: 2866 MIPS, FPU: 882 MFLOPS
Athlon 1GHz: CPU: 3111 MIPS, FPU: 1395 MFLOPS
Snooping around more
SGI Origin2000: 114 MFlops
Macintosh G3 ZIF/400: 93 MFlops
Macintosh G3/333: 77 MFlops
Intel Pentium II/450: 72 MFlops
Macintosh G3/300: 71 MFlops
Macintosh G3/266: 64 MFlops
Cray T3E-900: 63 MFlops
IBM SP2: 59 MFlops
iMac/233: 56 MFlops
Intel Pentium II/300: 48 MFlops
Intel Pentium Pro/200: 36 MFlops
Cray T3D: 17 MFlops
Of course, this is all rough - and depends on the software, memory etc.
as is commonly believed by those familiar with his mental prowess. Who else could
1. get an undergrad degree in chemical engg with straight As in all subjects AND a PhD in math for axiomatizing set theory, all by the age of 22,
2. write the axiomatic mathematical foundations of quantum mechanics a year later,
3. write 32 brilliant math papers over the next two years while starting a whole field of game theory which alone should merit a Nobel Prize for economics
4. be a key figure in the Los Alamos project for the atomic bomb, contributing to the idea of mathematical modeling and the implosion bomb,
5. start an entire subfield of pure math called von Neumann algebras,
6. and uh.. last but not the least, lay down the logical foundations for computing machines by borrowing ideas from Turing,
7. and oh.. formulate a theory and architecture of self-replicating machines,
8. and oh..pioneer an idea of nuclear deterrence at RAND.
As to the first computer, I don't quite understand what you are contesting. By Wilkes' machine you do mean EDSAC completed in 1949?
As to the Von Neumann Architecture, like I said, I think this is probably a more difficult question.
You seem to suggest that Atanasoff had thought of the Von Neumann Architecture in the 1930s? (I'm not disagreeing, but you don't make it absolutely clear that this is what you are saying.) I understand that Konrad Zuse had thought of the Von Neumann Architecture in the 1930s, and had written about it in a patent application (info here), so I don't know if that would have preceded Atanasoff or not.
But then, it may have crossed Charles Babbage's mind too (whether or not he though it was a worthwhile idea). And it's even possible that Archimedes had written about the Von Neumann Architecture in the Alexandrian Library. Not that I'm saying he did, but who would know?
http://dol.uni-leipzig.de/pub/showDoc.Fulltext?lan g=en&doc=1996-24&format=text&compressi on=
Sample Code
AGENT a % elevator "a"
EXTENSIONAL PREDICATES
CREATE TABLE at( Floor INTEGER UNIQUE);
CREATE TABLE up( Floor INTEGER UNIQUE);
CREATE TABLE down( Floor INTEGER UNIQUE);
CREATE TABLE req( Floor INTEGER UNIQUE);
INTEGRITY CONSTRAINTS
exists X: at(X) | up(X) | down(X);
DEFINE PERCEPTION EVENT reqTo( Floor INTEGER);
DEFINE PERCEPTION EVENT arrAt( Floor INTEGER);
DEFINE ACTION mvup() REALIZED BY 'call( go_up)';
DEFINE ACTION mvdown() REALIZED BY 'call( go_down)';
DEFINE ACTION halt() REALIZED BY 'call( halt)';
REACTION RULES
a1: DO( mvup), req(X) AND up(Y)
Y AND X0.
a3: up(X) 0. a5: DO( halt), at(X) AND not
req(X)
- RECV( arrAt(X)), req(X).
INITIAL BELIEFS at(3).
Moderation: +5 Karma Whore
"stored program computer" is the operative phrase when people are confusing "Von Neumann" with the person(s) who invented it. I wasn't aware of Zuse's early writeup before. Thanks. I suppose it would be appropriate to describe it as the Zuse Architecture then. The reason I spoke of Wilkes is because as you point out it does seem to have been an idea that was "in the air" for some time before Von Neumann published his paper. Now as you point it was actually written about by Zuse almost a decade earlier. Without a good attribution for the origin of the "idea" of stored program computers it seemed reasonable to assign it to the first stored program computer that actually got used for calculation that people wanted done more economically. I mention Atanasoff and Berry's and the ABC not because they "invented the idea of stored program computers" but because the ENIAC was ruled a derivative device of the ABC and Von Neumann's paper on stored program computers was almost certainly derived from his belated and occasional attendance of the design meetings for the next generation of the ENIAC lineage. Despite people thinking that this was a "revolutionary concept" it is fairly clear the reason it wasn't implemented sooner was for lack of demonstrably useful computing power using the concept. Wilkes' machine did that.
Seastead this.
This might lead to a resurgence of the language. It can be retooled to be object oriented (anybody remember Neon?)
...
Smalltalk might be another IDE for FPGAs as objects can be defined which represent gates and
I think I'll shut up now and find a Xylinx manual on the web somewhere.
MSBPodcast.com The opinions expressed here are my own. If you don't like 'em... Think up your own stuff.
The point is that a von Neumann architecture is a general purpose machine with registers, an ALU, and a unified memory for instructions and data. Every instruction operates on registers, memory, or both. There are variations on this architecture (hyperthreading, SMP, I/D caches, changeable microcode), but it's all based on the same general theory -- i.e. all calculations must be done by an ALU.
The reconfigurable FPGA architecture is entirely different. There is no reason that you would specifically need a distinct instructions to be fetched and executed, registers, or even an ALU. If you need to add 4 numbers, you don't make 3 loops through an ALU -- you wire together 3 adders [(A + B) + (C + D)]. If you need to OR together 32 bits, you don't make 31 loops through the ALU -- you create a 32-input OR gate.
In other words, you could easily do with one single "gate" on a reconfigurable FPGA what would take numerous instructions on a traditional von Neumann machine.
what I thought that it was a dodge powered part-time dump truck that somtimes pulls a trailer silly me
Diplomacy is the art of saying "Nice doggie" until you can find a rock. Will Rogers
I agree; the author of that article is full of it. I don't know what it is about von Neumann that inspires so many nutcases to write rubbish about his work; maybe they disagree with his political views, or have some crazy religious objection to game theory, or something. I've even seen authors stoop to making fun of his tragic terminal illness to try and discredit him.
Von Neumann is definitely one of the smartest men of the last century, and contributed a great deal to many fields. Anyone who says otherwise is merely a bitter crank.
If you're running a 3D-accelerated PC game or modelling application, the majority of your computer's FLOPS are already consumed by a non Von Neumann computing device.
.13 micron CPU. Such a system would be VERY easy to program, a couple orders of magnitude more so than an FPGA. So even though it wouldn't have as much theoretical computing power as an FPGA, massively parallel CPU's are likely to win out because they have the best cost/performance when you factor in development cost.
For better or worse, most of the PlayStation2's computing power is locked up in a non Von Neumann architecture.
So the evolution of computing to non Von Neuman architectures isn't so much news as a gradual shift that began about 5 years ago with 3dfx, and is really starting to happen large-scale right now.
The justification for FPGA's in consumer computing devices could be seen as a generalization of the rationale behind 3D accelerators: they bring you the ability to get a 10X-100X speedup in certain key pieces of code that are inherently very parallel and have very predictable memory access patterns.
I think the timeframe for mainstream FPGA style devices is quite far off, though. They need to evolve a lot before they'll be able to beat the combination of a Von Neumann CPU augumented with several usage-specific non Von Neumann coprocessors (the GPU, hardware TCP/IP acceleration, hardware sound...)
Here are the major issues:
- You'll need a lot more local memory than these devices have now -- there is a very limited set of useful stuff you can compute given a 32K buffer (a la PS2) and significant setup overhead.
- The big lesson from CPU's (and I expect from GPU's in the next few years) is that things REALLY flourish once you have virtualization of all resources, with a cache hierarchy extending from registers to L1 to L2 to DRAM to hard disk. For virtualization to make sense with FPGA's, Star Bridge's quoted reprogram times (40 msec) would need to improve by about 10,000X. Without this, you can really only run one task at a time, and that task can only have a fixed number of modules that use the FPGA.
Even then, it's not clear whether the FPGA's will be able to compete with massively parallel CPU's. In 3 more process generations, you should be able to put 8 Pentium 4 class CPU's on a chip, each running at over 10 GHz, at the same cost as current
All three articles are talking about highly specialised, basically single function, machines. As other posters have correctly pointed out , programming such machines is very, very difficult. When you manage to do so, they can be very powerful indeed. But they do only one job, even though they do it very, very well. Saying that they are likely to replace general putpose CPUS is like sayign that F1 cars of Indy racers about to replace pickups or family cars. They may do a job worth doing in their specialist area, and they may make money, bu they are never going to replace the VN machine in 90% of the places it is used.
One of them is a specialised web server. Fine, there are a lot of web pages out there that need serving. I can well believe that you can build an FPGA-based static-page web server which will beat the pants of a Sun/Intel server doing the same thing. But what about dynamic content? is their DBMS as good as the latest Oracle or MySQL? Willit, say, handle the internationalisation issues that those systems will? Bet it won't. Will it runs PHP or Python natively? I doubt it - I bet it hands that over to a traditional back-end processor.
As has also been said elsewhere, thus kind of hype is a repeated event. A specialist machine outperforms a generalist machine at its specialist task, and journalists claim that the world has turned upside down. Connection Machine, Deep Blue, GAPP, transputer... Just a few I can call to mind.
Consciousness is an illusion caused by an excess of self consciousness.
Unless you have an SMT processor like the latest P4 which has 2 instruction pointers to execute 2 threads.
THE LESSER-KNOWN PROGRAMMING LANGUAGES #14 -- VALGOL
VALGOL is enjoying a dramatic surge of popularity across the
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Variables are assigned with the =LIKE and =TOTALLY operators. Other
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accomplished with the FOR SURE construct. A simple example:
LIKE, Y*KNOW(I MEAN)START
IF PIZZA =LIKE BITCHEN AND
GUY =LIKE TUBULAR AND
VALLEY GIRL =LIKE GRODY**MAX(FERSURE)**2
THEN
FOR I =LIKE 1 TO OH*MAYBE 100
DO*WAH - (DITTY**2); BARF(I)=TOTALLY GROSS(OUT)
SURE
LIKE, BAG THIS PROGRAM; REALLY; LIKE TOTALLY(Y*KNOW); IM*SURE
GOTO THE MALL
VALGOL is also characterized by its unfriendly error messages. For
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message GAG ME WITH A SPOON! A successful compile may be termed MAXIMALLY
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