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It's a nice step but I look forward to so much more.

http://www.fpgacpu.org/usenet/fpgas_as_pc_coprocessors.html (1996): "... So as long as FPGAs are attached on relatively glacially slow I/O buses
-- including 32-bit 33 MHz PCI -- it seems unlikely they will be of much use in general purpose PC processor acceleration. ..."

Well, it's not cheap but it's already there: For example the HC-1 delivers the envisioned performance for specific applications using FPGAs as a second CPU in a dual-socket system, so the bandwidth is not an issue. Of course, developing for a FPGA is an effort of its own, but for this they offer pre-defined personalities for the FPGAs by which the FPGA can be used using an extended instruction set as a co-processor for a specific task.

Before you all speculate widely, try reviewing the actual product brief. http://download.intel.com/embedded/processors/prodbrief/324535.pdf . In which you will see this is an MCM with an Atom E6xx SoC die and an Altera FPGA die, interconnected by 1-2 PCIe x1 links. It has an amazing 1466 ball grid array package.

It's not clear to me what this level of packaging and integration achieves compared to mounting a (not integrated) E6xx BGA and a separate Altera or Xilinx FPGA BGA onto the main PCB, interconnected by PCIe x1 or perhaps even x4. Then you would get a broader choice of FPGAs -- and perhaps a simpler PCB escape for the two packages compared to one 1466 ball beast.

The advantages of this MCM as stated in the brief include:
* reduced board footprint
* lower component count
* simplified inventory control / manufacturing
* single-vendor support

True, but forgive me if I'm not over the moon. The dream of integrated FPGA fabric into a heterogeneous SoC (same die) includes a very low latency and possibly cache coherent interconect between the processor(s) and the FPGA. But here the FPGA is on the other side of a narrow PCIe link. It can't share the Atom SoC's memory hierarchy / DRAM channels very effectively. It is probably a very long latency round trip from x86 software control / registers and L1$ data, to some registers or function units in the FPGA, and back to the x86. So I think of this as more of a super-flexible Atom SoC platform than a dream reconfigurable computing platform.

It's a nice step but I look forward to so much more.

http://www.fpgacpu.org/usenet/fpgas_as_pc_coprocessors.html (1996): "... So as long as FPGAs are attached on relatively glacially slow I/O buses
-- including 32-bit 33 MHz PCI -- it seems unlikely they will be of much use in general purpose PC processor acceleration. ..."

MIPS is not open source. MIPS is a proprietary, licensed technology.

There are a few OSS processors out there, but they're pretty rare. One example is the xr16.

See earlier postings and blog entries on this concept:

http://www.fpgacpu.org/usenet/fpgas_as_pc_coproces sors.html
http://www.fpgacpu.org/log/aug01.html#010821-dimm

The latency to the FPGA fabric largely determines what kinds of coprocessing workloads are feasible.

When hypertransport came out, we (FCCM'ers) knew a HT-based lower latency interconnect should be possible. (Though I wouldn't call 75 ns +/- "low" latency -- that's a couple of hundred instruction issue slots, or a bit more than 1 full cache miss.) But DRC has gone and done it. I love the way it (apparently) just drops in and can even use that socket's DRAM DIMMs. Congrats to Steve Casselman and co.

See earlier postings and blog entries on this concept:

http://www.fpgacpu.org/usenet/fpgas_as_pc_coproces sors.html
http://www.fpgacpu.org/log/aug01.html#010821-dimm

The latency to the FPGA fabric largely determines what kinds of coprocessing workloads are feasible.

When hypertransport came out, we (FCCM'ers) knew a HT-based lower latency interconnect should be possible. (Though I wouldn't call 75 ns +/- "low" latency -- that's a couple of hundred instruction issue slots, or a bit more than 1 full cache miss.) But DRC has gone and done it. I love the way it (apparently) just drops in and can even use that socket's DRAM DIMMs. Congrats to Steve Casselman and co.

Yes -- Xilinx and Altera (and probably others as well) will let you download toolkits for free. They allow you to work in Verilog/VHDL or schematics (though most people use the latter primarily to see what the V* has produced).

If you only want one chip, you're probably best off using an FPGA or CPLD. Xilinx has a development kit (using a Digilent board) available for $100US. It has a 200 Kgate Spartan 3, which is plenty to build a variety of CPUs. If you really want to low-ball things, they have a $50US kit with something like a 50 Kgate CPLD. While that should be plenty for something like a Z80, it's still half the price for a quarter the gates...

Of course, Altera has some cheap development kits as well, but at least the last time I looked, their low-end kits didn't look (to me) like nearly as good of deals.

If you really want custom hardware made: well, the cheapest I know of for a one-off chip is around $10K. That's a lot better than the $100+ K just for maskwork to do conventional fabrication, but still way too high for most hobbyists. Below that, you're more or less stuck with an FPGA/CPLD or else hardwiring from individual gates.

Elsethread there was mention of the "big guys" with their Verilog tools not being able to do things like this. While opencores.org certainly isn't Intel, it also certainly has enough IP that putting together something on this order wouldn't really be a particularly huge challenge. They have a number of CPU cores, including some that emulate things like MIPS, so compilers aren't a major problem. Using the Wishbone SoC bus, connecting one of those to their Ethernet core should be fairly simple, and you're already about 90% done. Alternatively, you might want to look at the 10M Ethernet circuitry at fgpa4fun. The Ethernet core on opencores.org is only a MAC (so you'd need a separate PHY), but this outlines an on-chip PHY.

Those who are sufficiently serious that they don't like fpga4fun very well might prefer to look at the FPGA CPU site instead.

As you'd expect from the name, opencores.org is devoted to open source. The IP on the others varies, but IIRC, most of them are open to at least some degree as well.

• comp.arch.fpga Google archive of Usenet groups, where people interested in FPGA hang out.
• Opencores A set of free IP cores that can be implemented in FPGAs
• Comprehensive tutorial on FPGA
• A comprehensive list of FPGA CPUs
• A good FPGA tools overview
• FPGAworld news, jobs, forums, demos etc.(http://www.fpgaworld.com)
• FPGA Basics by Ray Andraka
• Fpga4Fun various fpga projects
• FPGA Boards
• AP100 PCI Platform FPGA Development Board
• Information about signal processing on FPGA by RF Engines
• FPGA manufacturers
  • Xilinx Xilinx has traditionally been the FPGA leader. Their general philosophy is to provide all the features possible, at the cost of extra complexity.
  • Altera Altera is the second FPGA heavyweight. Their philosophy is to provide the features that most people want while keeping their devices easy to use.
  • Lattice Lattice's focus is on low-cost, feature-optimized FPGAs and non-volatile, flash-based FPGAs.
  • Actel (http://www.actel.com/) and QuickLogic have antifuse (programmable-only-once) products.
  • Cypress
  • Atmel
  • Debian FPGA.

Xilinx have silicon with embedded PowerPC processors, BlockRam (chunks of pre-generated SRAM) and huge swathes of FPGA cells and interconnect. The chips have other abilities too - built-in 18-bit multipliers and communications channges (10 Gbps/channel, 20 channels!). All very cool stuff. Very expensive too :-(

I'm sort of surprised there aren't more FPGA-hackers than there appears to be. It's not hard to learn verilog (very similar to pascal), and despite what most FPGA designers will tell you, as long as you keep your mind focused on 'everything happens in parallel', a decent programmer can produce good FPGA code too. The start kits (300,000 gates, about enough for a hardware JPEG core and maybe a network MAC) are cheap (100 or so), and designing a processor is a pretty simple operation, and immensely gratifying :-)

Just my thoughts,

Krik

Xilinx have silicon with embedded PowerPC processors, BlockRam (chunks of pre-generated SRAM) and huge swathes of FPGA cells and interconnect. The chips have other abilities too - built-in 18-bit multipliers and communications channges (10 Gbps/channel, 20 channels!). All very cool stuff. Very expensive too :-(

I'm sort of surprised there aren't more FPGA-hackers than there appears to be. It's not hard to learn verilog (very similar to C), and despite what most FPGA designers will tell you, as long as you keep your mind focused on 'everything happens in parallel', a decent programmer can produce good FPGA code too. The start kits (300,000 gates, about enough for a hardware JPEG core and maybe a network MAC) are cheap (100 or so), and designing a processor is a pretty simple operation, and immensely gratifying :-)

Just my thoughts,

Simon

http://www.fpgacpu.org/links.html

http://www.aracnet.com/~healyzh/pdp_fpga.html

Michael Sokolov is rumored to be working on a FPGA VAX-inspired CPU with intent to fab eventually.

There's also an FPGA CPU mailing list, with almost 500 subscribers. Send mail to fpga-cpu-subscribe@yahoogroups.com to subscribe.

Many of us FPGA CPU hackers also frequent comp.arch.fpga on Usenet.

"I used to envy CPU designers, those lucky engineers with access to expensive tools and fabs. Now field-programmable gate arrays make custom processor and integrated system design accessible to everyone. These days I design my own systems-on-a-chip, and it's great fun."

Jan Gray, Gray Research LLC

There's also an FPGA CPU mailing list, with almost 500 subscribers. Send mail to fpga-cpu-subscribe@yahoogroups.com to subscribe.

Many of us FPGA CPU hackers also frequent comp.arch.fpga on Usenet.

"I used to envy CPU designers, those lucky engineers with access to expensive tools and fabs. Now field-programmable gate arrays make custom processor and integrated system design accessible to everyone. These days I design my own systems-on-a-chip, and it's great fun."

Jan Gray, Gray Research LLC

There's also an FPGA CPU mailing list, with almost 500 subscribers. Send mail to fpga-cpu-subscribe@yahoogroups.com to subscribe.

Many of us FPGA CPU hackers also frequent comp.arch.fpga on Usenet.

"I used to envy CPU designers, those lucky engineers with access to expensive tools and fabs. Now field-programmable gate arrays make custom processor and integrated system design accessible to everyone. These days I design my own systems-on-a-chip, and it's great fun."

Jan Gray, Gray Research LLC

Schematic entry is for people who do not know VHDL. There is hardly any other reason to use schematic entry when doing CPLD or FPGA programming, because schematic entry does hardly give you more control over the PAR process.

Cleverly done VHDL can also give you close control over the actual logic. Just look at this CPU: 8 Bit CPU in CPLD. Even though it is done in VHDL it is optimized to fit just into the smallest CPLDs available.

Btw. I found above link on http://www.fpgacpu.org which is another good starting point for FPGA based cpus.

With no prior knowledge of verilog, I followed Jan Gray's articles in Circuit Cellar and extended the design on my own. Verilog is superficially similar to 'C', so long as you remember that each "function" will operate in parallel.

Boards are cheap (approx $110 US for a 200k gate chip that could easily hold 4 processors and a lot more).

My own direction is interfacing stuff to my own processor that is based heavily on Jan's design. It's for purely personal use, and saying that you are running code (assembly language only :-) on your own processor rates up there, as far as geekdom is concerned. At least to me, but maybe I'm biased :-))

Jan's site is at fpgacpu.org if you're interested. There are lots of details about all sorts of issues on the site. Some technical, some not so technical. Have a look under GR CPU's or XSOC :-)

Simon.